KR930009811B1 - Mes fet transistor and manufacturing method thereof - Google Patents

Abstract

A MESFET is prepared by (1) forming an isolation well on a semi- insulating substrate by photo-etching, (2) growing a 1st conductive barrier in the isolation well by micro crystal growth, (3) growing a 2nd activated layer on the barrier, (4) growing a 2nd conductive gate buffer layer on the activated layer, (5) forming an ion implanting region by annealing and doping high concentrated impurities upto barrier layer, on the edge of the barrier, the activated layer and the gate buffer layer, (6) forming a source/drain region on the ion implanting region and (7) forming a gate electrode on the gate buffer layer between ion implanted regions.

Description

Metal-semiconductor field effect transistors and manufacturing method thereof

1a is a vertical cross-sectional view of a mesa-type metal-semiconductor field effect transistor.

Figure 1b is a side cross-sectional view taken along the line M-M 'of Fig. 1a.

2 is a vertical cross-sectional view of a metal-semiconductor field effect transistor in planar form.

3 is a vertical cross-sectional view of a metal-semiconductor field effect transistor according to the present invention.

4A to 4D are process flow diagrams of an isolated well type metal-semiconductor field effect transistor according to the present invention.

* Explanation of symbols for main parts of the drawings

1: semi-insulating substrate 2: n-GaAs buffer layer

3: n GaAs active layer 4: n ⁺ ion implantation region

5 source electrode 6 drain electrode

7: gate electrode 8: p ⁺ GaAs barrier layer

9: n ⁺ GaAs active layer 10: n ^- gate buffer layer

20: n GaAs active layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device and a method for manufacturing the same, and more particularly, to a metal-semiconductor field effect transistor that enables high integration and high speed of the device, and a method for manufacturing the same.

The necessity of the high integration and speed of semiconductor devices is increasing with the rapid development into the information and communication society. Group III-V compounds, in which the elements of group III and group V are covalently bonded on the periodic table, have high electron mobility, high insulation, and direct transition band gaps. Lightning consumption Among the III-V compounds, researches are being actively made to manufacture ultra-high speed, low power consumption GaAs digital ICs using the excellent material properties of GaAs. In particular, ohmic junctions of two sources and drains are formed at both ends of the conductive layer. In addition, a metal-semiconductor field effect transistor (hereinafter referred to as MESFET) that controls current by forming a Schottky junction and changing the width of the conductive layer due to voltage change is a basic device that determines GaAs digital IC performance. His improvement is becoming more important.

MESFET manufacturing methods include Mesa type (Fig. 1a) using epi wafer and Planar type (Fig. 2) by ion implantation method, but by ion implantation method with good device characteristic uniformity and no device separation. Manufacturing is dominant

Each device manufacturing method will be described with reference to the drawings.

1 shows a mesa type MESFET using an epi wafer.

A semi-insulating GaAs that minimizes the parasitic capacitance of the variable that determines the operation speed and facilitates the isolation between devices is used as the substrate (1), and the n-GaAs buffer layer (2) is placed on the molecular beam epitaxy (MBE). ) Or growing by the Metal Organic Chemical Vapor Deposition (MOCVD) method, growing the n GaAs active layer (3) on the buffer layer (2) in the same manner as described above, the buffer layer (2) and ha Implanting silicon ions to n-GaAs buffer layer 2 at the edge of layer 3 and then annealing, forming source electrode 5 and drain electrode 6 using conventional photolithography; A mesa type MESFET comprising a process of making a gate electrode 7 by using an undercut phenomenon of a resistor is obtained by using a GaAs as a semiconductor material to obtain a high speed semiconductor device that cannot be obtained by a silicon semiconductor device. Although, a large source resistance occurs because when using the n GaAs active layer has a doping concentration of the channel formed in the gate electrode lower part is lower than the concentration of the ion implantation region is a transconductance: no good low noise characteristics degrade (g _m Transconductance) do. In addition, an increase in the depletion region due to low concentration doping increases the gate capacitance, thereby degrading the high frequency characteristic. When the gate electrode length is shortened for high integration, the parasitic current caused by a part of the current flowing through the active layer to the buffer layer 4 is problematic because the energy barrier is low between the n GaAs active layer 3 and the n-GaAs buffer layer 4. In addition, it is difficult to make a propagation type / depletion enhancement mode MESFET (ESSFET) essential in a digital integrated circuit. In addition, a separate etching process is required to make the gate pads and isolation between important devices in the integrated circuit manufacturing process, which causes difficulties in the process. FIG. 1B is a cross-sectional view of the gate pad formed after etching along the line M-M ′ of FIG. 1A. This etching process has a disadvantage in that the process itself is cumbersome, but due to the unplanarization of the uppermost layer of the device due to the step generated after etching, there is a problem in the reproducibility when manufacturing an integrated circuit such as monolithic microwave IC (MMIC).

Figure 2 shows a planar type MESFET by ion implantation.

Implanting silicon, sulfur, or tellurium (Si, S or Te) ions into the semi-insulating GaAs substrate 1 to form an n GaAs active layer 20 whose current is controlled by a change in the gate voltage, the active layer 20 A process of forming an ion implantation region 4 by annealing after doping a high concentration of impurities at an edge, forming a source electrode 5 and a drain electrode 6 by a conventional photolithography method, and an undercut phenomenon of a photoresist. Is formed to form the gate electrode 7.

The planar type MESFET by the ion implantation method has a simple process and good device characteristic uniformity. Since the ion implantation is directly performed on the semi-insulating substrate 1, it is necessary to separate the elements for isolation or gate pad formation required in the mesa type. No etching process is necessary. However, when trying to make multiple impurity doping layers under the gate electrode without damaging the transconductance to improve the device characteristics, the interface between each layer is not accurately separated and low energy ion to make the MESFET with high transconductance. Injection and RTP (Rapid Thermal Process) activation processes are essential, which reduces the depth of impurity implantation, making it difficult to form multiple impurity doped layers. In addition, a high current density causes a leakage current problem in which a part of the current flowing through the semi-insulating substrate flows.

SUMMARY OF THE INVENTION An object of the present invention is to provide an isolated well type metal-semiconductor field effect transistor for solving various problems of the conventional metal-semiconductor field effect transistor.

Another object of the present invention is to provide a method of manufacturing the isolation well type metal-semiconductor field effect transistor.

The object of the present invention is to isolate a well formed as an element formation region on a semi-insulating substrate, a first conductivity type barrier layer and a second conductivity type active layer, each of which is sequentially filled with a predetermined thickness by a microcrystalline growth technique. And an ion implantation region doped with a second conductivity type impurity at a depth to the barrier layer at edges of the second conductivity type gate buffer layer, the barrier layer, the active layer and the gate buffer layer, and formed on the gate buffer layer between the ion implantation regions. And a source electrode and a drain electrode formed on the ion implantation region.

Still another object of the present invention is to provide a method of manufacturing a compound metal-semiconductor field effect transistor, comprising: forming an isolated well on a semi-insulating substrate by a conventional photolithography method; Growing a conductive barrier layer, growing a second conductive active layer on the barrier layer with the growth technique, growing a second conductive gate buffer layer on the active layer with the growth technique, growing the gate buffer layer A process of forming an ion implantation region by doping and annealing a high concentration of impurities to the barrier layer at the edge of the barrier layer, the active layer and the gate buffer layer, and forming a source electrode and a drain electrode on the ion implantation region after the annealing process And forming a gate electrode on the gate buffer layer between the ion implantation regions. Characterized in that consists of.

Therefore, the present invention solves the planarization problem, leakage current, and parasitic current problem that occur when device isolation and gate pad are formed in the mesa type MESFET (FIG. 1a) by the multi-layered device formation region by the isolation well and the microcrystal growth technique. It is possible to obtain a metal-semiconductor field effect transistor that solves low noise and high frequency characteristics, and solves the difficulty in improving the device characteristics caused by the difficulty of forming a multilayer impurity doping layer in the planar type MESFET (FIG. 2).

The invention will be described with reference to the accompanying drawings.

The metal-semiconductor field effect transistor according to the present invention of FIG. 3 has an isolation well formed by etching on a semi-insulating substrate 1, and a first conductivity type barrier layer 8, second formed by epitaxial growth in the isolation well. A conductive active layer 9, a second conductive gate buffer layer 10, and an ion implantation region 4 are formed.

In the figure, an isolation well is formed on the semi-insulating substrate 1 by a conventional photolithography method. The first conductivity type barrier layer 8 is formed by stacking microcrystalline growth techniques in the isolation wells. The second conductivity type active layer 9 is formed on the barrier layer 8 by the growth method. The second conductivity type gate buffer layer 10 is formed on the active layer 9 by the growth method. Ion implantation regions doped with impurities of the second conductivity type to a depth up to the barrier layer 8 are formed at the barrier layer, the active layer and the gate buffer layer, and at the edges. A source electrode and a drain electrode are formed on the ion implantation region and a gate electrode is formed on the gate buffer layer between the two electrodes. The current is changed by the channel change by the gate electrode.

4a to 4d illustrate the process sequence of an improved metal-semiconductor field effect transistor according to the present invention.

4A is a view obtained by etching isolated wells in which elements are formed in a semi-insulating GaAs substrate 1 that minimizes parasitic capacitance, which is one of the variables that determine the operation speed, and facilitates isolation between devices. When forming devices by forming isolation wells as shown in FIG. 4A, isolation is performed before the process, so that the problem of unstable isolation caused by isolation between devices at the time of high integration can be solved. It can be formed directly on the semi-insulating substrate without the etching process, so that the planarization problem can be solved naturally.

Figure 4b is a p ⁺ GaAs barrier layer containing any one of impurities such as beryllium, magnesium or zinc (Be, Mg or Zn) in the isolation well formed in Figure 4a by using MBE or MOCVD microcrystalline growth technology ( 8) and an n ⁺ GaAs active layer 9 and an n-GaAs gate buffer layer 10 containing any one of impurities such as silicon, sulfur, or tellurium (Si, S or Te) in order to grow. . In the conventional mesa type MESFET (FIG. 1a), a parasitic current problem occurs due to a small energy barrier between the n-buffer layer and the n active layer. However, in the present invention, the n ⁺ GaAs active layer 9 is formed on the p ⁺ GaAs barrier layer 8. The parasitic current problem is solved by using a high energy barrier between the two layers. In addition, since the source resistance is reduced by the high concentration of impurities, the transconductance is improved to improve the noise characteristics. Since the thickness of the active layer 9 can be arbitrarily adjusted, it is possible to enable a propagation type / deficiency type MESFET essential for digital integrated circuits, and the n-GaAs gate buffer layer 10 containing a low concentration of impurities on the n ⁺ GaAs active layer 9 By increasing the gate capacitance, the gate capacitance can be reduced, improving the high frequency characteristics and solving the leakage current problem.

FIG. 4C is a diagram illustrating annealing by implanting any one of ions such as silicon, sulfur or tellurium to the barrier layer 8 at the edge of the barrier layer, the active layer and the gate buffer layer. When the above ions are injected into the III-V compound semiconductor, the ions act as donors to form an n ⁺ type ion implantation region. The n ⁺ ion implantation region is in ohmic contact by the junction between the source electrode 5 and the drain electrode 6.

FIG. 4d is a view showing the completed embodiment of the present invention in which the source electrode 5, the drain electrode 6, and the gate electrode 7 are formed after the processes of FIGS. 4a to 4c. After the metal is coated on the surface of FIG. 4C, the source electrode 5 and the drain electrode 6 are formed by ordinary photolithography. The gate electrode 7 is in rectifying contact with the gate buffer layer 10 by using a lift off method using an undercut of the photoresist. The reason why the lift-off process is used in forming the gate electrode 7 is that a plurality of metal etchantes also etch the GaAs substrate itself, and metals such as AuGe, Ni, Ti, Pi, and Au are difficult to etch by a chemical method. Because. In the III-V compound semiconductor, ohmic contact generally uses Au-based Ni, Ti, Ag, Zn, and doping metals such as Ge, Zn, In, and Al, Ti, Pt as the rectifying contact material. Heat-resistant metals such as W are used.

In the above embodiment, GaAs, which is a group III-V compound, was used as the compound semiconductor material. However, it was not added to the detailed examples that the same purpose can be achieved with other various types of compound semiconductor materials. It is obvious by the one who has.

As sanggigwa according to the present invention, a metal-semiconductor field effect transistor to form isolated well before the step, since the epitaxial growth by forming a device in the isolated well solved naturally the isolation, leveling problem in the conventional mesa type MESFET p ⁺ barrier Layer, n ⁺ active layer and n-gate buffer layer are grown in order to solve the leakage current and parasitic current problem in mesa-type MESFET and planar-type MESFET, and reduce noise and high-frequency characteristics by reducing high source resistance and gate capacitance. Improved. In addition, it is possible to control the thickness of the active layer to enable a growth type / deficient MESFET.

It is apparent that the present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (12)

A compound metal-semiconductor field effect transistor comprising: an isolated well formed as an element formation region in a semi-insulating substrate; A first conductivity type barrier layer, a second conductivity type active layer, and a second conductivity type gate buffer layer each of which is sequentially filled with a predetermined thickness in the isolation well by a microcrystalline growth technique; An ion implantation region in which impurities of a second conductivity type are doped at edges of the barrier layer, the active layer and the gate buffer layer to a depth to the barrier layer; A gate electrode formed on the gate buffer layer between the ion implantation regions; And a source electrode and a drain electrode formed on the ion implantation region. The metal-semiconductor field effect transistor according to claim 1, wherein the semi-insulating substrate, the barrier layer, the active layer and the gate buffer layer are made of GaAs. The method of claim 1, wherein the first conductivity type layer contains any one of impurities such as silicon, sulfur, tellurium, and the like, and the second conductivity type layer contains any one of impurities such as beryllium, magnesium, zinc, and the like. A metal-semiconductor field effect transistor, characterized in that. 3. The metal-semiconductor field effect transistor according to claim 2, wherein said barrier layer, active layer and gate buffer layer are made by MBE microcrystal growth technology. 3. The metal-semiconductor field effect transistor according to claim 2, wherein said barrier layer, active layer and gate buffer layer are made by MOCVD microcrystal growth technology. The method of claim 2, wherein the barrier layer and the active layer each contain a high concentration of different impurities to create a large energy barrier between the two layers in order to prevent the current of the active layer from leaking to the semi-insulating substrate. Metal-semiconductor field effect transistor. The metal-semiconductor field effect transistor according to claim 2, wherein the active layer contains an impurity having the same concentration as that of the ion implantation region. 3. The metal-semiconductor field effect transistor according to claim 2, wherein the gate buffer layer contains a low concentration of impurities to reduce the gate capacitance. A method for producing a compound metal-semiconductor field effect transistor, comprising: forming an isolation well on a semi-insulating substrate by a conventional photolithography method; Growing a first conductive barrier layer as a microcrystal growth technique in said isolation well; Growing a second conductive type active layer on the barrier layer by the growth technique; Growing a second conductivity type gate buffer layer on the active layer by the growth technique; After the gate buffer layer growth process, doping a high concentration of impurities to the barrier layer at the edge of the barrier layer, the active layer and the gate buffer layer, and then annealing to form an ion implantation region; Forming a source electrode and a drain electrode on the ion implantation region after the annealing process; And forming a gate electrode on the gate buffer layer between the ion implantation regions. 10. The method of claim 9, wherein the barrier layer, the active layer, and the gate buffer layer are grown by MBE microcrystal growth technology. 10. The method of claim 9, wherein the barrier layer, the active layer, and the gate buffer layer are grown by MOCVD microcrystal growth technology. The method of claim 9, wherein the first conductivity type contains any one of impurities such as silicon, sulfur, tellurium, and the like, and the second conductivity type layer is formed by containing one of impurities such as beryllium, magnesium, zinc, and the like. Method for manufacturing a metal-semiconductor field effect transistor, characterized in that.

Images