JPH0121570Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a lateral junction field effect transistor suitable for obtaining an unsaturated drain voltage versus drain current characteristic (hereinafter simply referred to as an unsaturated characteristic). In particular, it relates to improvements in channel structure.

[Summary of the idea]

The present invention provides a lateral junction field effect transistor in which a source auxiliary region and a drain auxiliary region are each formed of a buried layer, and a gate region is formed on the surface of a high-resistance semiconductor layer facing a substrate semiconductor portion between these auxiliary regions. By defining a conductive channel consisting of a portion of the high-resistance semiconductor layer, the channel can be shortened.

[Conventional technology]

Figure 1 is a cross-sectional view of a conventional multi-channel vertical junction field effect transistor with a reticulated gate embedded therein. In this transistor, a high resistance layer is used in the drain region including the channel to improve conversion conductance. By reducing the ratio of the width a to the length of the channel/a, the series resistance between the source and drain can be kept low and unsaturated characteristics can be obtained.

However, although such vertical junction field effect transistors have the characteristics of low internal resistance and high breakdown voltage, they are not suitable for signal applications due to their vertical form, such as large junction capacitance, large gate series resistance, and gate (high impurity concentration layer). ) There are problems such as manufacturing difficulties in embedding.

In order to deal with these problems, a lateral junction field effect transistor with unsaturated characteristics was also developed
It has been proposed in Japanese Patent No. 18475, etc., and has attracted attention due to its advantages such as the ability to reduce gate series resistance, the ease of reducing junction capacitance, and the simple manufacturing process, but there are still many unresolved problems.

FIGS. 2a and 2b show a planar structure and a cross-sectional structure, respectively, of a field effect transistor similar to that in the above-mentioned publication, and this transistor is manufactured as follows. That is, p-type semiconductor substrate 1
Donut-shaped n ⁺ type buried layer 16 on the main surface of 1
After forming an n ^- type high-resistance semiconductor layer 12 by epitaxial growth treatment, a depletion layer 17 extending from the ring-shaped p ⁺ type gate region 13 is surrounded by a buried layer 16 on the surface of the semiconductor layer 12 . Furthermore, an n ⁺ type source region 14 is formed on the surface of the semiconductor layer 12 facing the substrate semiconductor portion 11A, and a ring of the buried layer 16 is formed so as to be close to the depletion layer 18 extending from the substrate semiconductor portion 11A. A ring-shaped n ⁺ -type drain region 15 is formed opposite to the shaped portion.

[The problem that the idea attempts to solve]

FIG. 2c shows a part of the structure shown in FIG. 2b on an enlarged scale, with reference to which the problems of the prior art will be explained.

According to the structure in Figure 2c, the conductive channel is
The channel is defined to extend obliquely upward with respect to the plane of the substrate semiconductor portion 11A on the side of the source side of the gate region 13, and the channel thickness corresponds to the distance between the gate region 13 and the substrate semiconductor portion 11A. The channel length is determined corresponding to the distance between the buried layer 16 and the source region 14.

Here, the gate region 13 and the semiconductor portion 11A
The distance between them depends not only on the depth of the gate region 13, but also on the
Since it also depends on the position of the gate region 13 in the direction parallel to the plane of the semiconductor portion 11A, there are large variations due to misalignment during gate diffusion. Furthermore, the distance between the buried layer 16 and the source region 14 also depends on the position of the source region 14 in the direction parallel to the plane of the buried layer 16, and therefore varies widely due to misalignment during source/drain diffusion. Therefore, there is a problem in that the reproducibility of channel dimensions and, furthermore, the reproducibility of unsaturated characteristics is not good, and the manufacturing yield is low.

Moreover, in the operating state, the gate region 13
Since the depletion layer 17 that expands from the source side expands more toward the drain side than the source side, the depletion layer 17 does not reach the depletion layer 18 even with a slight gate voltage, and the broken line 17'
A considerably large gate voltage is required to reach the pinch-off state shown in . That is, it is difficult to cause a large change in drain current with a small change in gate voltage, and there are problems in that the conversion conductance is low.

In order to deal with such problems, it is conceivable to form the gate region 13 closer to the semiconductor portion 11A, but in this case,
Since the gate region 13 is close to the source region 14, there is a disadvantage that the breakdown voltage between the gate and the source is lowered. Therefore, it is necessary to form the source region 14 away from the gate region 13, and in this case, the effective channel length increases, the series resistance between the source and the drain increases, and the frequency characteristics deteriorate. There are disadvantages that good unsaturation properties may not be obtained. In other words, when trying to shorten the channel length, the gate region 13
must be formed away from the semiconductor portion 11A toward the drain, and if this is done, there is an unavoidable inconvenience that the conversion conductance decreases.

In short, in the case of Fig. 2c, it is difficult to increase the conversion conductance without reducing the gate-source breakdown voltage, and it is also difficult to shorten the channel without reducing the conversion conductance. There is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a lateral junction field effect transistor with improved electrical characteristics and ease of manufacture.

[Means to solve the problem]

FIG. 3 shows a transverse junction field effect transistor according to an embodiment of the present invention, and the structure of the present invention will be explained with reference to this. The field effect transistor of the present invention includes a semiconductor substrate 1, source and drain auxiliary regions 61 and 62, and a high resistance semiconductor layer 2.
, a gate region 3 , and source and drain regions 4 and 5 .

The semiconductor substrate 1 has a first conductivity type (for example, p-type).

The source and drain auxiliary regions 61 and 62 each have a second conductivity type (eg, n-type) opposite to the first conductivity type, and are formed on the main surface of the semiconductor substrate 1 at a distance from each other.

High-resistance semiconductor layer 2 has a second conductivity type with a lower impurity concentration than source and drain auxiliary regions 61 and 62, and is epitaxially formed on the main surface of semiconductor substrate 1 so as to cover source and drain auxiliary regions 61 and 62. Formed by a barrel growth process.

The gate region 3 has a first conductivity type,
A high resistance semiconductor layer 2 is provided between the substrate semiconductor portion 1A sandwiched between the source and drain auxiliary regions 61 and 62.
is formed on the surface of the high-resistance semiconductor layer 2 facing the substrate semiconductor portion 1A to define a conductive channel consisting of a portion of the substrate semiconductor portion 1A.

The source and drain regions 4 and 5 each have a second conductivity type with higher impurity concentration than the high resistance semiconductor layer 2, and the source and drain auxiliary regions 6
1 and 62, respectively, are formed on the surface of the high-resistance semiconductor layer 2, respectively.

The source auxiliary region is made to work as an effective source based on the source potential applied to the source region, and the drain auxiliary region is made to work as an effective drain based on the drain potential given to the drain region.

[Effect]

According to the above configuration of the present invention, the conductive channel extends between the substrate semiconductor portion 1A sandwiched between the source and drain auxiliary regions 61 and 62 and the gate region 3, substantially parallel to the plane of the semiconductor portion 1A. The channel thickness is determined according to the distance between the gate region 3 and the semiconductor portion 1A, and the channel length is determined according to the distance between the source and drain auxiliary regions 61 and 62. Ru.

Here, the distance between the substrate semiconductor portion 1A and the gate region 3 depends on the depth of the gate region 3, but does not depend on the position of the gate region 3 in the direction parallel to the plane of the substrate semiconductor portion 1A. There is no variation due to misalignment during gate formation, and the depth of the gate region 3 can be determined with high precision by a normal impurity introduction process such as selective diffusion. Further, source and drain auxiliary regions 61,
The distance between the source and drain auxiliary regions 61, 62 is determined by a conventional impurity introduction process such as a selective diffusion method.
62 at the same time eliminates the need for positioning as in the prior art, allowing for highly accurate determination. Therefore, the reproducibility of channel dimensions and, by extension, the reproducibility of unsaturated properties are improved, and the manufacturing yield is significantly improved.

Moreover, in the operating state, the depletion layer 7 extending from the gate region 3 as shown in FIG. Even with gate voltage, it becomes easy to reach a pinch-off state,
High conversion conductance can be obtained. In this case, even if the position of the gate region 3 in the direction parallel to the plane of the substrate semiconductor portion 1A is slightly shifted, unlike the conventional case, this does not affect the pinch-off operation. This means that the channel is in the substrate semiconductor portion 1A.
This is because it is set approximately parallel to the plane of Further, unlike the conventional case, the gate region 3 does not need to be formed particularly close to the source in order to obtain high conversion conductance.

Furthermore, the pinch-off point (intrinsic gate point)
Since the carrier injection into is performed from the source auxiliary region 61, this source auxiliary region 61 acts as an effective source. Therefore, source region 4
The gate-source series resistance, which is determined by the effective source position, can be kept small even if the source region 4 is formed at a certain distance from the gate region 3.Moreover, by keeping the source region 4 away from the gate region 3, surface leakage current can be reduced and the gate - Source-to-source breakdown voltage can be improved. In other words, the channel length is determined according to the distance between the source and drain auxiliary regions 61 and 62 and is not directly related to the position of the source region 4, so it can be shortened without sacrificing the gate-source breakdown voltage. Channelization can be achieved, and good unsaturated characteristics and high frequency characteristics can be obtained.

〔Example〕

Next, an embodiment will be described in which the lateral junction field effect transistor of the present invention is manufactured so as to obtain unsaturated characteristics.

For example, on the main surface of a semiconductor substrate made of p-type silicon, n-type source and drain auxiliary regions 61 and 62 are formed simultaneously at a predetermined distance (channel length) from each other by a well-known selective diffusion process. Ru. After that, an n ^- type high resistance semiconductor (silicon) layer 2 with a thickness of about 10 μm, for example, is placed on the top surface of the substrate.
is formed by an epitaxial growth process. In this case, the impurity concentration of the semiconductor layer 2 is preferably set to 5×10 ¹⁴ atoms/cm ³ or less (for example, 1×10 ¹³ atoms/cm ³ ) to facilitate expansion of the depletion layer. Source and drain auxiliary regions 61, 62
is covered with the semiconductor layer 2 and becomes a so-called buried layer.

Next, a p ⁺ -type gate region 3 is formed on the surface of the semiconductor layer 2 by selective diffusion processing, facing the substrate semiconductor portion 1A sandwiched between the source and drain auxiliary regions 61 and 62. As a result, semiconductor portion 1
Between A and gate region 3 a conductive channel is defined which is substantially parallel to the plane of semiconductor portion 1A. In this case, the distance (channel thickness) t between the semiconductor portion 1A and the gate region 3 is preferably 10 μm or less, and the ratio of the distance t to the distance/t is as small as possible, for example within the range of 0.1 to 10. It is preferable to set it to .

Next, on the surface of the semiconductor layer 2, an n ⁺ type source region 4 facing a part of the source auxiliary region 61 and an n ⁺ type drain region 5 facing a part of the drain auxiliary region 62 are simultaneously formed by selective diffusion treatment. is formed. In this case, the formation positions of the source and drain regions 4 and 5 with respect to the gate region 3 are appropriately set so as to obtain the desired gate-source breakdown voltage and gate-drain breakdown voltage, but the depletion layer 7 from the gate region is Considering the spread, gate area 3
It is desirable that the distance between the drain region 5 and the drain region 5 is larger than that of the source region 4. As an example, the distance between the gate region 3 and the drain region 5 is
It can be made more than 10μm.

After this, the gate region 3,
Electrode layers are provided in the source region 4, drain region 5, and substrate 1, respectively. The substrate 1 acts as a second gate, and may be applied with a voltage or grounded as desired.

FIG. 4 shows an example of the characteristics of a lateral junction field effect transistor manufactured according to the above embodiment, and shows a drain voltage V _D with a gate voltage V _G as a parameter.
This shows the characteristic curve of the drain current I _D , and it can be seen that good unsaturated characteristics are obtained.

In the above embodiment, an n-channel transistor was explained, but a p-channel lateral junction field effect transistor can be easily realized by reversing the conduction type of each semiconductor element from that shown in the figure. Channel lateral transistors have the advantage of being easier to manufacture than those with vertical structures.

[Effect of idea]

As described above, according to this invention, source and drain auxiliary regions each consisting of a buried layer are provided, and a gate region is formed on the surface of the high-resistance semiconductor layer facing the semiconductor portion of the substrate between these auxiliary regions. A conductive channel made of a part of the high-resistance semiconductor layer is defined, and the source and drain auxiliary regions are made to work as an effective source and drain, respectively, so that a short channel can be formed with improved conversion conductance and gate-source breakdown voltage. By shortening the channel, electrical characteristics such as unsaturated characteristics and frequency characteristics can be improved.

Furthermore, since channel dimensions can be determined with good reproducibility, an additional effect of improving manufacturing yield can be obtained.

[Brief explanation of the drawing]

Figure 1 is a sectional view showing a conventional vertical junction field effect transistor, Figure 2 a, b and c are a plan view, sectional view and partially enlarged sectional view of a conventional lateral junction field effect transistor, respectively. FIG. 4 is a cross-sectional view showing a field effect transistor according to an embodiment of the present invention, and a characteristic diagram showing the relationship between drain voltage V _D and drain current _ID in the transistor of the present invention. 1... Semiconductor substrate, 2... High resistance semiconductor layer, 3
...gate region, 4...source region, 5...drain region, 61...source auxiliary region, 62...drain auxiliary region.

Claims (1)

[Claims for Utility Model Registration] (a) A semiconductor substrate having a first conductivity type; (b) A second conductivity type formed on the main surface of the semiconductor substrate at a distance from each other and having a second conductivity type opposite to the first conductivity type. (c) a source auxiliary region and a drain auxiliary region formed on the main surface of the semiconductor substrate to cover the source auxiliary region and the drain auxiliary region, each having a mold; (d) a part of the high-resistance semiconductor layer between a high-resistance semiconductor layer having a second conductivity type with a lower impurity concentration and (d) a substrate semiconductor portion sandwiched between the source auxiliary region and the drain auxiliary region; (e) a gate region of a first conductivity type formed on the surface of the high resistance semiconductor layer opposite the substrate semiconductor portion to define a conductive channel; (f) a source region formed on the surface of the high resistance semiconductor layer and having a second conductivity type with a higher impurity concentration than the high resistance semiconductor layer; formed on the surface,
a drain region having a second conductivity type with a higher impurity concentration than the high-resistance semiconductor layer; the source auxiliary region acts as an effective source based on a source potential applied to the source region; A field effect transistor characterized in that the drain auxiliary region is made to function as an effective drain based on a given drain potential.