JPS6331945B2 - - Google Patents

Info

Publication number
JPS6331945B2
JPS6331945B2 JP55084884A JP8488480A JPS6331945B2 JP S6331945 B2 JPS6331945 B2 JP S6331945B2 JP 55084884 A JP55084884 A JP 55084884A JP 8488480 A JP8488480 A JP 8488480A JP S6331945 B2 JPS6331945 B2 JP S6331945B2
Authority
JP
Japan
Prior art keywords
forming
region
conductivity type
semiconductor layer
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55084884A
Other languages
Japanese (ja)
Other versions
JPS5710266A (en
Inventor
Junji Sakurai
Takashi Matsumoto
Haruhisa Mori
Kunihiko Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8488480A priority Critical patent/JPS5710266A/en
Publication of JPS5710266A publication Critical patent/JPS5710266A/en
Publication of JPS6331945B2 publication Critical patent/JPS6331945B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Description

【発明の詳細な説明】 本発明は、高密化されたMIS(Metal Insulator
Semiconductor)電界効果半導体装置を製造する
方法の改良に関する。
[Detailed Description of the Invention] The present invention provides a high-density MIS (Metal Insulator)
Semiconductor) relates to improvements in methods for manufacturing field effect semiconductor devices.

従来、MIS電界効果半導体装置を高密化する技
術の一つとして短チヤネル化が実施されている。
その場合、所謂短チヤネル効果の発生防止、ゲー
ト・オーバラツプ容量の低減などの目的をもつ
て、ソース接合、ドレイン接合を浅く形成するこ
とが行なわれる。例えば、第1図に見られるよう
に、サフアイア、二酸化シリコンなどの絶縁物基
板1上にp型シリコン半導体島2を形成し、そこ
に、ゲート酸化膜3、シリコン・ゲート電極4、
n+型ソース領域5、n+型ドレイン領域6などを
形成して装置を作つた場合、ソース領域5、ドレ
イン領域6は出来る限り浅く形成される。
Conventionally, channel shortening has been implemented as one of the techniques for increasing the density of MIS field effect semiconductor devices.
In this case, the source and drain junctions are formed shallowly for the purpose of preventing the so-called short channel effect and reducing gate overlap capacitance. For example, as shown in FIG. 1, a p-type silicon semiconductor island 2 is formed on an insulating substrate 1 such as sapphire or silicon dioxide, and a gate oxide film 3, a silicon gate electrode 4,
When a device is manufactured by forming an n + type source region 5, an n + type drain region 6, etc., the source region 5 and drain region 6 are formed as shallowly as possible.

ところで、図示のように、半導体島2が厚く形
成されていて、ソース領域5、ドレイン領域6が
浅く形成されたことに依り、それ等領域5,6の
底面が半導体島2内に露出された状態になると、
この種半導体装置の特徴の一つである接合面積が
小さい旨の利点が失なわれてしまう。従つて、接
合からのリークや接合容量が大になる。尚、第1
図の破線は空乏層を表わしている。
By the way, as shown in the figure, since the semiconductor island 2 is formed thickly and the source region 5 and drain region 6 are formed shallowly, the bottom surfaces of these regions 5 and 6 are exposed inside the semiconductor island 2. When the condition is reached,
The advantage of a small junction area, which is one of the characteristics of this type of semiconductor device, is lost. Therefore, leakage from the junction and junction capacitance increase. Furthermore, the first
The broken line in the figure represents the depletion layer.

そこで、前記欠点を解消すべく、第2図に見ら
れる装置が開発された。尚、第2図では第1図に
関して説明した部分と同部分を同記号で指示して
ある。
Therefore, in order to eliminate the above-mentioned drawbacks, the device shown in FIG. 2 was developed. In FIG. 2, the same parts as those explained with reference to FIG. 1 are indicated by the same symbols.

第2図従来例が第1図従来例と相違する点は、
半導体島2を薄く形成して、ソース領域5及びド
レイン領域6の底面が絶縁物基板1に達している
ことである。これに依り、第1図従来例に関して
記述した欠点は解消される。しかしながら、その
ような構成を採ることに依り新たな問題が発生す
る。即ち、半導体島2を薄くしたことに依り、ソ
ース領域5及びドレイン領域6の抵抗値が高くな
つてしまい、高速動作を妨げられることである。
The differences between the conventional example in Figure 2 and the conventional example in Figure 1 are as follows:
The semiconductor island 2 is formed so thin that the bottom surfaces of the source region 5 and drain region 6 reach the insulating substrate 1. This eliminates the drawbacks described with respect to the conventional example in FIG. However, adopting such a configuration creates new problems. That is, by making the semiconductor island 2 thinner, the resistance values of the source region 5 and drain region 6 become higher, which impedes high-speed operation.

本発明は、チヤネル領域に対し、ソース領域及
びドレイン領域に於ける微少面積の側面のみが対
向するようにしながらも、ソース領域及びドレイ
ン領域の抵抗値増を招来しない構造のMIS電界効
果半導体装置を製造できるようにするものであ
り、以下これを詳細に説明する。
The present invention provides a MIS field effect semiconductor device having a structure in which only small side surfaces of the source and drain regions face the channel region, but do not cause an increase in the resistance values of the source and drain regions. This will be explained in detail below.

第3図は本発明を実施して得られたMIS電界効
果半導体装置の一例を表す要部側断面説明図であ
る。
FIG. 3 is an explanatory side sectional view of a main part of an example of a MIS field effect semiconductor device obtained by implementing the present invention.

図に於いて、11は絶縁物基板、12はp型シ
リコン半導体層、13はゲート絶縁膜、14はシ
リコン・ゲート電極、15はn+型ソース領域、
16はn+型ドレイン領域、12Aはリセス部を
それぞれ示している。
In the figure, 11 is an insulator substrate, 12 is a p-type silicon semiconductor layer, 13 is a gate insulating film, 14 is a silicon gate electrode, 15 is an n + type source region,
Reference numeral 16 indicates an n + type drain region, and reference numeral 12A indicates a recess portion.

本発明では、前記MIS電界効果半導体装置の構
造から判るように島状の厚いp型シリコン半導体
層12のチヤネル領域及びその近傍を含む部分に
リセス部12Aを形成して薄くなし、その薄い部
分の表面にゲート絶縁膜13及びシリコン・ゲー
ト電極14を形成してから例えば燐イオンの注入
を行なつてソース領域15及びドレイン領域16
を形成してあるので、それ等がチヤネル領域と対
向して接合を形成する部分は前記薄い部分に掛つ
ている。従つて、接合面積は必要最小限に抑えら
れ、そして、ソース領域15及びドレイン領域1
6の大部分は厚い部分からなつているので抵抗値
も低く保たれている。
In the present invention, as can be seen from the structure of the MIS field effect semiconductor device, a recessed portion 12A is formed in a portion of the island-shaped thick p-type silicon semiconductor layer 12 including the channel region and its vicinity to make it thinner. After forming a gate insulating film 13 and a silicon gate electrode 14 on the surface, for example, phosphorus ions are implanted to form a source region 15 and a drain region 16.
are formed so that the portions where they face the channel region and form a junction span the thin portions. Therefore, the junction area is suppressed to the necessary minimum, and the source region 15 and drain region 1
Since most of 6 is made up of thick parts, the resistance value is also kept low.

第4図は本発明を実施して得られたMIS電界効
果半導体装置の他の例を表わす要部側断面説明図
であり、第3図に関して説明した部分と同部分を
同記号で指示してある。
FIG. 4 is an explanatory side cross-sectional view of a main part showing another example of a MIS field-effect semiconductor device obtained by implementing the present invention, and the same parts as those explained in connection with FIG. 3 are indicated by the same symbols. be.

本実施例が第3図実施例と相違する点は、n型
不純物イオン、例えば燐イオンを注入する際に、
イオン濃度のピークが半導体層12の薄い部分か
ら外れるように、従つて、その部分ではイオン濃
度のピークは絶縁物基板11内に形成され図では
そのピーク領域を1点鎖線で表わし記号17で指
示してある。また、半導体層12の厚い部分では
ピーク領域が記号15A,16Aで指示してある
ように、ソース領域15、ドレイン領域16内に
存在するようになり、それ等の抵抗値を低減する
のに極めて有効に作用する。また、チヤネル領域
と対向して接合を形成する部分は比較的低不純物
濃度になされるから耐圧を向上させることができ
る。
The difference between this embodiment and the embodiment shown in FIG. 3 is that when implanting n-type impurity ions, for example, phosphorus ions,
In such a way that the peak of ion concentration deviates from the thin portion of the semiconductor layer 12, the peak of ion concentration is formed in the insulating substrate 11 in that portion. It has been done. In addition, in the thick portion of the semiconductor layer 12, the peak regions exist in the source region 15 and drain region 16 as indicated by symbols 15A and 16A, and it is extremely difficult to reduce the resistance value of these regions. It works effectively. Further, since the portion facing the channel region and forming the junction is made to have a relatively low impurity concentration, the breakdown voltage can be improved.

以上の説明で判るように、本発明に依れば、ソ
ース領域及びドレイン領域の大部分は厚い半導体
層部分に在り、チヤネル領域と対向して接合を形
成する部分は薄い半導体層部分に在つて、前記ソ
ース領域及びドレイン領域は微少面積の側壁のみ
で、しかも、浅い接合が形成されたMIS電界効果
半導体装置を容量に製造することができ、そし
て、そのようにして得られたMIS電界効果半導体
装置は短チヤネル効果の防止、ゲート・オーバラ
ツプ容量の低減に有効であり、また、抵抗値は低
く維持されるので高速性が妨げられることもな
い。
As can be seen from the above description, according to the present invention, most of the source region and drain region are located in the thick semiconductor layer portion, and the portion facing the channel region and forming a junction is located in the thin semiconductor layer portion. , it is possible to manufacture a capacitive MIS field effect semiconductor device in which the source region and the drain region have only sidewalls with a small area and shallow junctions, and the MIS field effect semiconductor device thus obtained The device is effective in preventing short channel effects and reducing gate overlap capacitance, and the resistance is kept low so high speed is not hindered.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は従来例を説明する為のMIS
電界効果半導体装置の要部側断面図、第3図及び
第4図は本発明を実施して得られたMIS電界効果
半導体装置のそれぞれ異なつた例を表す要部側断
面図である。 図に於いて、11は基板、12は半導体層、1
3はゲート酸化膜、14はゲート電極、15はソ
ース領域、16はドレイン領域である。
Figures 1 and 2 are MIS to explain the conventional example.
FIGS. 3 and 4 are side sectional views of main parts of field effect semiconductor devices, respectively, showing different examples of MIS field effect semiconductor devices obtained by implementing the present invention. In the figure, 11 is a substrate, 12 is a semiconductor layer, 1
3 is a gate oxide film, 14 is a gate electrode, 15 is a source region, and 16 is a drain region.

Claims (1)

【特許請求の範囲】 1 絶縁物基板上に島状の一導電型半導体層を形
成する工程と、 次いで、該島状の一導電型半導体層に於けるチ
ヤネル領域及びその近傍にリセス部を形成して薄
くする工程と、 次いで、該薄くされたチヤネル領域の表面にゲ
ート酸化膜及びゲート電極を形成する工程と、 次いで、該ゲート電極をマスクとして反対導電
型不純物を導入し前記チヤネル領域を介して対向
する反対導電型ソース領域及びドレイン領域を形
成する工程と が含まれてあることを特徴とするMIS電界効果半
導体装置の製造方法。
[Claims] 1. A step of forming an island-shaped semiconductor layer of one conductivity type on an insulating substrate, and then forming a recessed portion in the channel region and its vicinity in the island-shaped semiconductor layer of one conductivity type. Next, a step of forming a gate oxide film and a gate electrode on the surface of the thinned channel region; Next, using the gate electrode as a mask, an opposite conductivity type impurity is introduced through the channel region. A method for manufacturing an MIS field effect semiconductor device, comprising the step of forming a source region and a drain region of opposite conductivity type facing each other.
JP8488480A 1980-06-23 1980-06-23 Mis field effect semiconductor device Granted JPS5710266A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8488480A JPS5710266A (en) 1980-06-23 1980-06-23 Mis field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8488480A JPS5710266A (en) 1980-06-23 1980-06-23 Mis field effect semiconductor device

Publications (2)

Publication Number Publication Date
JPS5710266A JPS5710266A (en) 1982-01-19
JPS6331945B2 true JPS6331945B2 (en) 1988-06-27

Family

ID=13843183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8488480A Granted JPS5710266A (en) 1980-06-23 1980-06-23 Mis field effect semiconductor device

Country Status (1)

Country Link
JP (1) JPS5710266A (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0828507B2 (en) * 1982-03-16 1996-03-21 セイコーエプソン株式会社 Semiconductor device
US5736751A (en) * 1982-04-13 1998-04-07 Seiko Epson Corporation Field effect transistor having thick source and drain regions
US6294796B1 (en) 1982-04-13 2001-09-25 Seiko Epson Corporation Thin film transistors and active matrices including same
JPS58178564A (en) * 1982-04-13 1983-10-19 Seiko Epson Corp Thin film transistor
FR2527385B1 (en) * 1982-04-13 1987-05-22 Suwa Seikosha Kk THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY PANEL USING THIS TYPE OF TRANSISTOR
JP2622661B2 (en) * 1982-04-13 1997-06-18 セイコーエプソン株式会社 LCD panel
JPS58182272A (en) * 1982-04-19 1983-10-25 Seiko Epson Corp Thin film transistor
US5698864A (en) * 1982-04-13 1997-12-16 Seiko Epson Corporation Method of manufacturing a liquid crystal device having field effect transistors
JPS62281473A (en) * 1986-05-30 1987-12-07 Sony Corp Manufacture of field-effect type transistor
US5485028A (en) * 1988-10-03 1996-01-16 Kabushiki Kaisha Toshiba Semiconductor device having a single crystal semiconductor layer formed on an insulating film
US5116771A (en) * 1989-03-20 1992-05-26 Massachusetts Institute Of Technology Thick contacts for ultra-thin silicon on insulator films
US5362979A (en) * 1991-02-01 1994-11-08 Philips Electronics North America Corporation SOI transistor with improved source-high performance
CA2061796C (en) * 1991-03-28 2002-12-24 Kalluri R. Sarma High mobility integrated drivers for active matrix displays
JP2018148123A (en) 2017-03-08 2018-09-20 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and semiconductor device manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5656675A (en) * 1979-10-16 1981-05-18 Toshiba Corp Semiconductor device on insulated substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5656675A (en) * 1979-10-16 1981-05-18 Toshiba Corp Semiconductor device on insulated substrate

Also Published As

Publication number Publication date
JPS5710266A (en) 1982-01-19

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