JPS6131630B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit semiconductor device of the type in which a buried insulating layer is formed below an impurity doped region.

Conventionally, structures such as those shown in FIGS. 1 to 3 have been proposed in order to improve the high frequency characteristics and power consumption characteristics of semiconductor devices.

Figure 1 is a side view of the main parts of an n-channel MOS field effect transistor, in which 1 is a p ⁺ type silicon semiconductor substrate, 2 is a p ^- type epitaxially grown silicon semiconductor layer, 3 is a buried insulating layer, and 4 is a gate insulator. 5 is a polycrystalline silicon gate, 6 is an n ⁺ type source region, 7 is an n ⁺ type drain region, 8 is a phosphosilicate glass film, S is a source electrode terminal, G is a gate electrode terminal, D is a drain electrode Each terminal is shown.

FIG. 2 is a sectional side view of the main parts of a p-n-p type bipolar transistor, in which 11 is an n ⁺ type silicon semiconductor substrate, 12 is an n ^- type epitaxially grown silicon semiconductor layer, 13 is a buried insulating layer, and 14 15 is an insulating film, 15 is a p ⁺ type emitter region, 16 is an n ⁺ type base region, 17 is a p ⁺ type collector region, E is an emitter electrode terminal, B is a base electrode terminal, and C is a collector electrode terminal.

FIG. 3 is a side sectional view of the main parts of a junction field effect transistor, in which 21 is an n ⁺ type silicon semiconductor substrate, 22 is a p ^- type epitaxially grown silicon semiconductor layer, 23 is a buried insulating layer, 24 is an insulating film, 25 26 is a p ⁺ type source region, 26 is a p ⁺ type drain region, 27 is an n ⁺ type gate region, S is a source electrode terminal, D is a drain electrode terminal, and G is a gate electrode terminal, respectively.

What these conventional examples have in common is that a buried insulating layer is provided below an impurity-introduced region, such as a source region. In this way, it is possible to reduce the parasitic capacitance of the junction formed between the impurity doped region and the substrate (semiconductor layer), which is effective in improving high frequency characteristics and reducing power consumption.

However, it is not necessarily a good idea to form the above-mentioned buried insulating layer in all element regions;
In fact, its existence may sometimes cause inconvenience.

The present invention provides a semiconductor having an element region in which a buried insulating layer for reducing junction capacitance is formed on one semiconductor substrate, and an element region in which a buried insulating layer is not formed and parasitic junction capacitance is actively utilized. An apparatus is provided, which will now be described in detail.

FIG. 4 is a sectional view of essential parts of an embodiment of the present invention.

This embodiment consists of a main circuit consisting of an n-channel MIS inverter and its input protection circuit.
This is an example.

In the figure, 31 is a p ⁺ type silicon semiconductor substrate, 32 is a p ^- type epitaxially grown silicon semiconductor layer, 33 is a buried insulating layer, 34 is a gate insulating film, 35 is a polycrystalline silicon gate, and 36 is an n ⁺
type source region, 37 is n ⁺ type drain region, 38
39 is an insulating film, 39 is a p ⁺ type impurity introduced region, and 40 is an insulating film.
n ⁺ type impurity introduced region, S is the source electrode terminal, D
is the drain electrode terminal, G is the gate electrode terminal, IN
indicate input terminals, respectively.

FIG. 5 shows an equivalent circuit diagram of the embodiment shown in FIG. 4, and the same symbols as those used in FIG. 4 represent the same parts or have the same meanings.

In the figure, R is the resistance formed by the n ⁺ type impurity introduced region 40, and Di is the p ⁺ type impurity introduced region 39.
and a diode formed of the n ⁺ type impurity-introduced region 40 and set to a relatively low reverse breakdown voltage;
C ₁ is a junction capacitance, C ₂ is a gate capacitance, C ₃ is a drain junction capacitance, M is a main circuit, and P is an input protection circuit.

In this embodiment, the n ⁺ type drain region 37
Since the bottom and part of the side surfaces are insulated by the insulating layer 33 and the insulating film 38 made of silicon dioxide, the junction capacitance _C3 is significantly reduced and the high frequency characteristics are improved. On the other hand, since the junction capacitance _C1 has a relatively large value, a large voltage noise (spike) occurs between the input terminal IN and the power supply.
When is applied, the spike voltage slows down according to the time constant of C ₁ ×R, so that the gate capacitance C ₂ will not be destroyed. In order to effectively maintain such a function, the p ⁺ type impurity introduced region 3
9. It is preferable that the bottom and side surfaces of the n ⁺ -type impurity-introduced region 40 are not insulated. The reason for this is that not only is there no benefit in forming a buried insulating layer, but also
This is because the degree of freedom in design for appropriately selecting the values of C ₁ and R becomes narrower.

Forming the buried insulating layer 33 described above is extremely easy. That is, a thermal oxide film of, for example, about 1 [μm] is formed on the p ⁺ type substrate 31, and then the thermal oxide film is patterned using ordinary photolithography technology, and then p ^- type epitaxy is formed on the thermal oxide film. A buried insulating layer 33 is formed by forming a dielectrically grown silicon semiconductor layer 32 . The pattern is such that the thermal oxide film is removed from the portion of the main circuit M that will become the gate region, and from the entire portion of the input protection circuit P. The technique for forming the buried insulating layer 33 described above is well known, and if necessary, refer to Japanese Patent Application Laid-Open No. 112574/1984. Next, silicon is deposited at 0.5 to 1.0 using the usual vapor phase growth method.
Grow to about [μm]. Then, a polycrystalline silicon film is grown on the insulating layer 33, and a single crystal silicon film is grown on the portion where the surface of the semiconductor layer 32 is exposed by removing the thermosetting film. As a result, the buried insulating layer is completely buried. After this, required elements may be formed through normal steps.
In the step of forming the thermal oxide film, a selective oxidation technique using a nitride film (eg, planox, isoplanar, etc.) may be applied. Further, in the embodiments described above, the MIS field effect transistor has been described, but the present invention can also be applied to bipolar transistors and junction field effect transistors.

As can be seen from the above explanation, according to the present invention, a buried insulating layer is formed in the region where elements that require high speed are to be formed to reduce the junction capacitance. A buried insulating layer is not formed in the area where the elements that make up the circuit are to be formed, so that different types of elements installed on the same substrate can perform their full functions. It is extremely easy to do this.

[Brief explanation of the drawing]

1 to 3 are side sectional views of main parts of a conventional example, FIG. 4 is a side sectional view of main parts of an embodiment of the present invention, and FIG. 5 is an equivalent circuit diagram of the embodiment shown in FIG. In the figure, 31 is a semiconductor substrate, 32 is a semiconductor layer, 33 is a buried insulating layer, 34 is a gate insulating film,
35 is a polycrystalline silicon gate, 36 is a source region, 37 is a drain region, 38 is an insulating film, 39,
40 is an impurity introduced region, IN is an input terminal, S is a source electrode terminal, D is a drain electrode terminal, and G is a gate electrode terminal. 〓〓〓〓

Claims (1)

[Claims] 1. A device region where a buried insulating layer is provided on a semiconductor substrate and the junction capacitance of the device formed thereon is reduced; 1. A semiconductor device comprising an element region having a large junction capacitance.