JP2002217410A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed, low-power semiconductor device. SOLUTION: A MOS transistor is provided with a titanium oxide gate insulation electrode 104a that is interposed between a semiconductor substrate 101 and a gate electrode 105a. The main crystal structure of titanium oxide is of anatase type. The channel region of the semiconductor substrate is in a tensile stressed condition due to a film 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a gate insulating film suitable for high speed and low power.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for higher speed and lower power of semiconductor devices. In order to realize a high-speed semiconductor device, miniaturization of an element structure has been promoted, and it has been proposed to utilize a strain effect in a field-effect transistor. In the strain effect, when a semiconductor is subjected to stress, an energy band is distorted, and the effective mass of carriers changes. If the effective mass can be reduced, the speed of the semiconductor device will be increased.

In order to reduce the power consumption of a semiconductor device, it is conceivable to reduce a leak current flowing through a gate insulating film. A silicon oxide film having a large band gap of 8.0 eV and having excellent insulating properties is considered to be a gate insulating film. It has been frequently used for membranes.

However, in recent years, with the miniaturization of semiconductor devices, thinning of the gate insulating film has been required, and the thickness of the gate insulating film has been reduced to 3.0 nm.
The following oxide films have been used: When the thickness of the insulating film is reduced to 3.0 nm or less, there is a problem that a tunnel current becomes so large that it cannot be ignored, a leak current increases, and power consumption increases. Therefore, it has been considered that by using titanium oxide having a higher dielectric constant than silicon oxide for the gate insulating film, the thickness of the gate insulating film is increased and the increase in tunnel current is suppressed while maintaining the dielectric characteristics. For example, when the relative dielectric constants of titanium oxide and silicon oxide are 60 and 4.0, respectively, a 30-nm-thick titanium oxide thin film has dielectric properties equivalent to 2 nm of silicon oxide. The above-described titanium oxide thin film having a thickness of 30 nm is called 2 nm in terms of silicon oxide. On the other hand, the actual film thickness of 30 nm is called a physical film thickness.

It is known that titanium oxide has two types of crystal structures, rutile type and anatase type, depending on the production method. For example, IBM Journal of Research and De
Table 1 of velopment VOL.43, NO.3, page 385 shows that the chemical vapor deposition (Chemical Vapordeposition: CVD) method
When the film formation temperature is 465 ° C. or lower, the anatase type becomes 550
It is described that a structure in which anatase type and rutile type are mixed at 620 ° C. and 620 ° C., and a rutile type at 660 ° C. or higher. It is also described that anatase type titanium oxide changes to rutile type by annealing. That is,
Since rutile-type titanium oxide is more thermally stable than anatase-type titanium oxide, it has been proposed to use rutile-type titanium oxide as a conventional gate insulating film.

[0006]

However, in a conventional semiconductor device, when trying to achieve both high speed and low power, a tensile strain is applied to the channel layer, and further, rutile type titanium oxide is used as a gate insulating film. Although it is necessary to have a structure, such a structure has a problem in that a tensile current is applied to the channel layer, so that a leak current flowing through the gate insulating film increases, and as a result, power consumption increases.

The present inventors have conducted intensive studies on this problem, and have found a mechanism that the leakage current density flowing through the rutile-type titanium oxide gate insulating film is increased by applying a tensile strain to the channel layer. The mechanism is that by applying tensile strain to the channel layer, tensile strain also occurs in the rutile-type titanium oxide gate insulating film, the band gap of the rutile-type titanium oxide film decreases, tunneling probability increases, and leakage current increases. Has increased.

An object of the present invention is to provide a high-speed and low-power semiconductor device.

[0009]

(1) To achieve the above object, the present invention provides a semiconductor device having a MOS transistor having a titanium oxide gate insulating film interposed between a semiconductor substrate and a gate electrode. Wherein the titanium oxide has a main crystal structure of an anatase type and a strain state of a channel region of the semiconductor substrate is a tensile strain state.

With the above structure, the band gap of the gate insulating film can be made larger than that of the case of using the rutile type by making the main crystal structure of the titanium oxide gate insulating film anatase type, and the tensile strain can be reduced. Even if it is added to the film, the band gap of anatase type is larger than that of rutile type. Therefore, it is possible to suppress an increase in tunnel current due to tensile strain, to reduce a leak current and to operate a semiconductor device at high speed and with low power. What can be done.

(2) In the above (1), preferably,
A silicon oxide film or a titanium silicate film is provided between the semiconductor substrate and the titanium oxide gate insulating film.

(3) In any one of the above (1) and (2), preferably, the gate electrode has a polycrystalline silicon film to which phosphorus or boron is added, and the gate electrode and the titanium oxide gate insulating film Between them, a silicon oxide film or a titanium silicate film is provided.

(4) In any one of the above (1) and (2), preferably, the gate electrode is any one of a tungsten film, a molybdenum film, a tungsten nitride film, a tungsten boride film, a tungsten silicide film or It has such a laminated structure.

(5) In any one of (1) and (2), preferably, the gate electrode has a ruthenium oxide film, and the ruthenium oxide film and the titanium oxide insulating film are in contact with each other. It was done.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and a method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS. First, the configuration of the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 1 is a cross-sectional view showing a cross-sectional configuration of a main part of the semiconductor device according to the first embodiment of the present invention.
It is A 'sectional drawing. FIG. 2 is a plan layout diagram of a main part of the semiconductor device according to the first embodiment of the present invention.

As shown in FIG. 1, in the semiconductor device according to the present embodiment, an element isolation film 102 made of, for example, a silicon oxide film is provided on the surface of a P-type silicon substrate 101, and an element formation region 103 is formed. . Element formation region 10
3 is provided with an N-channel MOS transistor.

The MOS transistor has a gate insulating film 10
4a and a gate electrode 105a. On the side surface of the gate electrode 105a, a sidewall 106a made of, for example, silicon nitride is formed. The main constituent material of the gate insulating film 104a is titanium oxide having an anatase crystal structure. The gate electrode 105a is, for example, a polycrystalline silicon film, a metal thin film, a metal silicide film, or a laminated structure of these. The MOS transistor has an N ⁻ formed on the gate electrode 105a in a self-aligned manner.
It has a source / drain diffusion layer 107a and an N ⁺ -type source / drain diffusion layer 108 formed in self-alignment with the element isolation layer 102 and the gate electrode 105a.

A film 20 having a tensile stress is formed on the surface of the MOS transistor. The film 20 having the tensile stress is, for example, silicon nitride. The film 20 puts the channel region 10 of the silicon substrate into a tensile strain state, reduces the effective mass of carriers, and speeds up the device. Further, the gate insulating film is also in a tensile strain state by the film 20 of the tensile stress.

An interlayer insulating film 1 is formed on the surface of the semiconductor device.
09 is formed. In the interlayer insulating film 109, a contact hole 110 reaching the N ⁺ type source / drain diffusion layer 108 is provided.

Anatase type titanium oxide gate insulating film 10
The film thickness of 4a is, for example, 30 nm. The relative dielectric constants of anatase type titanium oxide and silicon oxide are 60, respectively.
In the case of 4.0, the thickness of the gate insulating film 104a is 2n in terms of the thickness of silicon oxide having equivalent dielectric properties.
m. That is, the physical film thickness is 30 nm, and the reduced film thickness is 2 nm.

As described above, in the semiconductor device according to the present embodiment, since the gate insulating film 104a is made of an anatase type titanium oxide which is a high dielectric material, the gate insulating film 1
04a is a gate insulating film a
Can be made thicker and the DT current can be prevented from flowing.

Further, the main crystal structure of the titanium oxide gate insulating film uses an anatase type, and the band gap of the gate insulating film can be made larger than that using a rutile type. Even when tensile strain is applied to the gate insulating film, the band gap of the anatase type is larger than that of the rutile type. Thereby, an increase in tunnel current due to tensile strain can be suppressed.

Here, the tensile strain dependency of the anatase type titanium oxide used in the semiconductor device according to the present embodiment will be explained in comparison with the characteristics of the rutile type titanium oxide with reference to FIGS. First, the tensile strain dependence of the band gap of titanium oxide will be described with reference to FIG. FIG. 3 is an explanatory diagram of the tensile strain dependence of the band gap of titanium oxide. In the figure, the horizontal axis indicates tensile strain ε (%), and the vertical axis indicates band gap Eg (e).
V). In the figure, the solid line A indicates the anatase type, and the solid line R indicates the rutile type.

[0024] As understood from FIG. 3, the band gap Eg ^R of rutile titanium oxide R (epsilon), the band gap Eg ^A of anatase type titanium oxide A (epsilon) is decreased both in accordance with the strain increases However, the band gap Eg ^A (ε) of the anatase type titanium oxide A does not become smaller than the band gap Eg ^R (ε) of the rutile type titanium oxide R.

The strain dependence of the band gap shown in FIG. 3 is obtained by the first principle band calculation. First-principles band calculation is, for example, "solid-structure and physical properties"
Iwanami Lecture Modern Physics 7 (Iwanami Shoten, 1994)
As described in, a method of solving the Schrodinger equation for electrons in a solid and calculating the energy band of the electrons.

The band gap is the energy difference between the upper end of the energy level (valence band) occupied by electrons and the lower end of the energy level (conduction band) not occupied by electrons. It can be said that the larger the band gap is, the higher the insulating property is and the more difficult it is for a current to flow. According to the density functional theory, the calculated value of the band gap is usually underestimated as compared with the experimental value.
Therefore, in this calculation, the band gap value is corrected based on the experimental results.

Next, the dependency of the work function of titanium oxide on tensile strain will be described with reference to FIG. FIG. 4 is an explanatory diagram of the tensile strain dependence of the work function of titanium oxide. In the figure, the horizontal axis represents tensile strain ε (%),
The vertical axis indicates the band gap Eg (eV). Note that positive strain indicates tensile strain, and negative strain indicates compressive strain. In the figure, the solid line A indicates the anatase type, and the solid line R indicates the rutile type.

Here, it is assumed that the work function ΦB (ε) is proportional to the band gap Eg shown in FIG. 3, and the following equation (1) is used for the rutile work function ΦB ^R (ε).
The work function ΦB ^A (ε) of the anatase type was calculated using the following equation (2).

ΦB ^R (ε) = ΦB ^R (ε = 0) × Eg ^R (ε) / Eg ^R (ε = 0) (1) ΦB ^A (ε) = ΦB ^R (ε = 0) × Eg ^{A (ε) / Eg R (ε} = 0) ... (2) here,, ΦB ^R (ε = 0) is strain-free (epsilon = 0)
Is the work function of the rutile type in the case of ΦB ^R (ε = 0)
= 1.0 eV. This value is the work function of bulk rutile-type titanium oxide obtained in the experiment.

As shown in FIG. 4, the work function ΦB ^R (ε) of the rutile type titanium oxide and the work function ΦB ^A (ε) of the anatase type titanium oxide decrease as the strain increases. Work function ΦB ^R (ε) of titanium oxide
Is not smaller than the work function ΦB ^A (ε) of anatase type titanium oxide.

Next, the dependency of the leakage current density of titanium oxide on the tensile strain will be described with reference to FIG. FIG.
FIG. 4 is an explanatory diagram of the dependency of the work function of titanium oxide on the tensile strain of the leak current density. In the figure, the horizontal axis represents tensile strain ε (%), and the vertical axis represents leakage current density (A / c).
m ² ). Note that positive strain indicates tensile strain, and negative strain indicates compressive strain. Also,
In the figure, the solid line A indicates the anatase type, and the solid line R indicates the rutile type.

The strain dependency of the leak current density shown in FIG. 5 is obtained from the strain dependency of the work function obtained in FIG. 4, for example, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.
6, NO.2, WKB (Wentz
el-Kramers-Brillouin) approximation, derived from the relationship between the probability that electrons tunnel through the insulating film and the strain.

FIG. 5 shows the result when the applied voltage is 1 V and the film thickness is 2.0 nm in terms of silicon oxide. The silicon oxide-equivalent film thickness on the horizontal axis in FIG. 5 indicates a film thickness capable of obtaining the same dielectric properties as silicon oxide, and the dielectric constants of silicon oxide and rutile type titanium oxide are 4.0 and 60, respectively. For example, the film thickness of titanium oxide having a silicon oxide equivalent film thickness of 2.0 nm is 2.0 nm × 60 / 4.0 = 30.0 nm.

FIG. 5 shows that the leakage current densities of the rutile-type titanium oxide and the anatase-type titanium oxide both increase monotonically with an increase in the strain, but the leak current density of the anatase type is higher than that of the rutile type even when strain is applied. Is small. That is, even if tensile strain is applied to the gate insulating film due to the tensile strain applied to the channel layer, the leakage current is increased by using an anatase type titanium oxide film for the gate insulating film as compared with the case of using the rutile type. Can be suppressed. Therefore, power consumption can be reduced.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG.
FIG. 11 is a process chart illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

As shown in FIG. 6, the P-type silicon substrate 10
On one surface, a groove having a depth of 200 nm to 300 nm is formed, a silicon oxide film is buried, and a shallow trench type element isolation layer 1 is formed.
02 is formed.

Next, as shown in FIG.
01 surface, for example, Chemical Vapor d
An anatase-type titanium oxide film 104 having a thickness of about 30 nm is formed by eposition (CVD). At this time, the film forming temperature is preferably 460 ° C. or less, and more preferably 330 ° C. or less. When the film formation temperature is 460 ° C. or higher, the titanium oxide film 10
This is because rutile-type titanium oxide may be mixed during film formation. Further, when the film formation temperature is 330 ° C. or more, even if the film is anatase type at the time of film formation, the anatase type titanium oxide may undergo a phase transition to the rutile type by a subsequent heat treatment at about 850 ° C. An N ⁺ -type polycrystalline silicon film 105 having a thickness of about 200 nm is formed on the surface of the anatase-type titanium oxide film 104 by a CVD method or the like.

Next, as shown in FIG. 8, the polycrystalline silicon film 105 and the anatase type titanium oxide film 104 are etched using the photoresist film as a mask. Thus, a gate insulating film 104a and a gate electrode 105a of the MOS transistor are formed. Next, the thermal oxidation method or C
A silicon oxide film 96 having a thickness of about 2 nm is formed by the VD method. The N of the MOS transistor is implanted by phosphorus ion implantation.
^- -type source and drain regions 107. The N ⁻ type source / drain region 107 is self-aligned with the gate electrode and the gate insulating film. The purpose of forming the silicon oxide film 96 is to reduce damage to the silicon substrate due to the phosphorus ion implantation.

Next, as shown in FIG. 9, a silicon nitride film 106 having a thickness of 200 nm is deposited on the surface of the semiconductor substrate by sputtering or CVD.

Further, as shown in FIG. 10, by etching the silicon nitride film 106 and the silicon oxide film 96, side walls 106a are formed on the side walls of the gate electrode and the gate insulating film.

Finally, as shown in FIG. 11, the element isolation film 102, the gate electrode 105a, the side fall 106a
Is used as a mask to form an N ⁺ type source / drain diffusion layer 108 by arsenic ion implantation. Further, a silicon nitride film 20 having a thickness of 200 nm is
It is deposited by the D method. The silicon nitride film formed by the CVD method has a tensile stress. Due to this tensile stress, the channel portion 10 of the silicon substrate and the gate insulating film 104
a is also pulled to be in a tensile strain state. And C
The main part of the semiconductor device according to the present embodiment shown in FIG. 1 is formed by forming the interlayer insulating film 109 and forming the contact hole 110 reaching the surface of the diffusion layer by the VD method.

It should be noted that the above-described manufacturing method uses the N-channel M
In the case of an OS transistor, this manufacturing method can be applied to a P-channel MOS transistor. Further CM
It can also be applied to OS transistors and BiCMOS transistors.

As the gate electrode 105a, other than a polycrystalline silicon film, a metal thin film such as tungsten or molybdenum, a metal compound such as tungsten nitride or tungsten boride, a metal silicide film such as tungsten silicide, or ruthenium oxide It may be a film or a laminated structure thereof. By using these materials, the resistance of the gate electrode can be reduced. In a structure in which a ruthenium oxide film and a titanium oxide gate insulating film are in contact with each other, improvement in thermal stability of the titanium oxide gate insulating film can be expected.

As described above, anatase-type titanium oxide is more thermally unstable than rutile-type titanium oxide.
In some cases, a phase transition from an anatase type to a rutile type occurs due to annealing treatment after film formation. However, the present embodiment is characterized in that the main crystal structure of the oxide gate insulating film is an anatase type. For example, even if the oxide gate insulating film contains a rutile type of about several to ten percent, The effects are not significantly impaired, and are within the scope of the present embodiment.

As described above, in the semiconductor device according to the present embodiment, since the channel region of the silicon substrate is in a tensile strain state, the effective mass of electrons as carriers is reduced, and the speed of the semiconductor device is increased. .

In the present embodiment, the main crystal structure of the titanium oxide gate insulating film uses an anatase type, and the band gap of the gate insulating film can be made larger than that of the rutile type. Further, even when tensile strain is applied to the gate insulating film, the band gap of the anatase type can be larger than that of the rutile type.
Therefore, an increase in tunnel current due to tensile strain can be suppressed, and power consumption can be reduced.

Therefore, the reliability of the semiconductor device can be improved. As a result, the yield can be improved.

Next, the configuration of the semiconductor device according to the second embodiment of the present invention will be explained with reference to FIG. Figure 1
FIG. 2 is a sectional view showing a configuration of a main part of the semiconductor device according to the second embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same parts.

In this embodiment, as shown in FIG.
Silicon substrate 101 and titanium oxide gate insulating film 104a
Between them, an insulating film such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or a titanium silicate film 111 is formed in one or more layers. However, the thickness of the insulating film 111 is preferably 0.5 nm or less in order to obtain high dielectric properties of the gate insulating film. By interposing the above-described film between the silicon substrate 101 and the titanium oxide gate insulating film, the thermal stability of the titanium oxide insulating film can be improved.

Also in this embodiment, the speed of the semiconductor device can be increased, and the power consumption can be reduced. Therefore, the reliability of the semiconductor device can be improved. As a result, the yield can be improved.

Next, the configuration of the semiconductor device according to the third embodiment of the present invention will be explained with reference to FIG. Figure 1
FIG. 3 is a sectional view showing a configuration of a main part of the semiconductor device according to the third embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same parts.

In this embodiment, as shown in FIG.
Forming a gate electrode like the film 105a and the film 112;
It has two or more layers. As the film 112, silicide, the same film as the film 105a, aluminum (Al), or tungsten (W) can be used.

Also in this embodiment, the speed of the semiconductor device can be increased and the power consumption can be reduced. Therefore, the reliability of the semiconductor device can be improved. As a result, the yield can be improved.

[0054]

According to the present invention, a high-speed and low-power semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a sectional configuration of a main part of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan layout view of a main part of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is an explanatory diagram of the tensile strain dependence of the band gap of titanium oxide.

FIG. 4 is an explanatory diagram of the dependence of the work function of titanium oxide on tensile strain.

FIG. 5 is an explanatory diagram of the dependency of the work function of titanium oxide on the tensile strain of the leak current density.

FIG. 6 is a process chart illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a process chart illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a process chart illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a process chart illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a process chart illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a process chart illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a cross-sectional configuration of a main part of a semiconductor device according to a second embodiment of the present invention.

FIG. 13 is a sectional view showing a sectional configuration of a main part of a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 ... Silicon substrate 102 ... Element isolation film 103 ... Element formation region 104 ... Anatase type titanium oxide film in a tensile strain state 104a ... Anatase type titanium oxide gate insulating film in a tensile strain state 105 ... Polycrystalline silicon film 105a, 112 ... The gate electrode 106 ... silicon nitride film 106a ... sidewall 107 and 107a ... N ^- type source and drain diffusion layers 108, 108a ... N ⁺ type source and drain diffusion layers 109 ... interlayer insulating film 110 ... contact hole 111: insulating film 96 ... Silicon oxide film

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hideo Miura 502, Kandachicho, Tsuchiura-shi, Ibaraki Pref. Machinery Research Laboratory, Hitachi, Ltd. F-term within the Hitachi, Ltd. Semiconductor Group (Reference) 4M104 BB01 BB16 BB18 BB28 BB33 BB35 BB36 BB40 CC05 DD17 EE03 EE15 EE16 EE17 FF13 GG09 5F040 DA02 DB03 DC01 EC01 EC04 EC07 EC08 EC09 ED01 ED03 EK05 EL06 EM05 EL06

Claims (5)

[Claims] 1. A semiconductor device in which a MOS transistor having a titanium oxide gate insulating film interposed between a semiconductor substrate and a gate electrode is formed, wherein a main crystal structure of the titanium oxide is an anatase type, and Wherein the strain state of the channel region is a tensile strain state. 2. The semiconductor device according to claim 1, further comprising a silicon oxide film or a titanium silicate film between said semiconductor substrate and said titanium oxide gate insulating film. 3. The semiconductor device according to claim 1, wherein said gate electrode has a polycrystalline silicon film doped with phosphorus or boron, and said gate electrode and said titanium oxide gate insulating film. A silicon oxide film or a titanium silicate film between them. 4. The semiconductor device according to claim 1, wherein the gate electrode is any one of a tungsten film, a molybdenum film, a tungsten nitride film, a tungsten boride film, and a tungsten silicide film. A semiconductor device having a stacked structure thereof. 5. The semiconductor device according to claim 1, wherein said gate electrode has a ruthenium oxide film, and said ruthenium oxide film and said titanium oxide insulating film are in contact with each other. A semiconductor device, comprising: