JPH01119065A - Iii-v compound semiconductor field-effect transistor - Google Patents

Abstract

PURPOSE:To enable a channel to be positioned which is away from a MIS interface and to stabilize characteristics by allowing the first semiconductor layer which is adjacent to a gate insulation later to keep an energy gap which is larger than the second semiconductor layer which is positioned at a lower position and by forming the second semiconductor layer and a conformity grid or distortion grid. CONSTITUTION:A MIS-type field-effect transistor consists of a grid conformity In1-xGaxAs semiconductor layer 2 (x=0.47), InP semiconductor layer 1, a gate insulation layer 4, a gate electrode 5, and source/drain electrodes 6 and 7 on a semi-insulation InP substrate 3. When a positive voltage is applied to a gate electrode 5, energy gap (1.35eV) of InP is larger than that (0.8eV) of InGaAs and a channel is formed at the InGaAs layer side of interface between the InGaAs layer 2 and the InP layer 1.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a metal insulating layer having an active layer of an m-v compound semiconductor that can handle large voltage amplitudes at high speed and is suitable for integration, etc. Semiconductor field effect transistor (hereinafter referred to as
MISFET).

<Conventional technology> +11-V group compound semiconductors have high speed, low power consumption,
In order to surpass silicon in terms of low noise, etc., its development is currently being actively carried out. The element is formed using silicon. M equivalent to Mo5FET
ISFETs are desirable because they are suitable for high performance and high integration, but they are difficult to form using GaAs, which is currently being put into practical use, and MESs using Schottky gates are difficult to form.
FET is commonly used. However, MESF
ET has a small voltage amplitude during circuit operation and a small drive capacity, so it is hard to say that it has an advantageous element structure from the viewpoint of increasing the speed and integration of the element.

<Problems to be solved by the invention> If a MISFET is realized, it will be possible to realize a highly integrated electronic device that has a large logic amplitude (input voltage amplitude) and is highly resistant to noise and power supply voltage fluctuations. It is expected that the material will be InP, InGaA.
Indium-based ■-V group compounds such as s are suitable. However, these MISFETs have problems such as insufficient interface characteristics for practical use and the occurrence of characteristic trirad during operation.

The present invention was created in view of the above points, and aims to solve the above technical problems and provide a MISFET that is stable in operation and has high performance.

<Means for Solving the Problems> In order to achieve the above-mentioned object, the present invention provides a substrate and a substrate having different energy gaps Eg formed on the substrate.
It has a plurality of semiconductor layers formed by stacking group compounds, and a gate insulating layer formed on the semiconductor stack, and at least one of the substrate or the semiconductor layer is a m-v group compound containing In and P. In a field effect transistor made of a compound, the first semiconductor layer in contact with the gate insulating layer has a larger energy gap than the second semiconductor layer below it. and forms a matched lattice or strained lattice with the second semiconductor layer.

<Function> By configuring as above, a channel is formed at a position away from the MIS interface, which causes carrier capture and characteristic drift, so characteristics can be stabilized and the energy gap can be reduced. Multiple m- with different Eg
By combining V-group compounds, it is possible to form high-performance transistors that utilize two-dimensional electron gas and the like and are suitable for ultra-high-speed operation.

Furthermore, the characteristics of MISFET, such as high driving ability and large ring fracture amplitude, are maintained.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a cross-sectional view showing the structure of a MIS field effect transistor according to an embodiment of the present invention, in which a lattice-matched I nl-X GaX As semiconductor layer 2 ( x=0.47), an InP semiconductor layer 1, a gate insulating layer 4, a gate electrode ff15, and source/drain electrodes 6.7.

FIG. 2 shows an energy band diagram when a positive voltage is applied to the gate electrode 5, and the energy gap (1.35 eV) of InP is similar to that of In Ga As (0
, 8eV), and the InGaAs layer 2 and InP
A channel is formed on the InGaAs layer side of the interface of layer 1.

In this example, InP is undoped, for example,
It functions as a buffer layer that separates the channel and MIS interface.

E2 and gate voltage v6, V6=V, +
v2+ v3 2E+d1+Ezd+ (However, v3 is about 0.IV and should be ignored) εI El = '2 E2, vG ''('' dt + d 2 ) E2ε1, and the first semiconductor layer (InP) 1 An electric field of approximately ε2 d 1 + d 2 Sl is applied.

Here, ■2〉ΔE0(ΔEc: InGaAs and In
Conduction band disco between P
ntinuity), the channel 7 is formed not only at the interface between the first semiconductor layer 1 and the second semiconductor layer 2 but also at the MIS interface.
5; formed, making it impossible to obtain high-speed performance. In order to prevent a new channel from being formed at the MIS interface due to a single fc force, it is desirable that the conditions of E2d2 and ΔEo be satisfied.

So, (here vG)ΔEo, most of the voltage is absolute! & applied to layer 4).

As is clear from the above equation (1), the thickness of the first semiconductor layer 1 is desirably about 1000 Å at most or less, although it depends on the combination of materials and the operating voltage of the device.

For example, as the gate insulating layer 4, the film thickness d 1 = 1000λ
When InP is used as the first semiconductor layer 1 and l n Ga As is used as the second semiconductor layer 2, 't(S i 02) =3.9+ ', +(I
n P ) = 12° ΔEC (InP-InGaAs,
)=0.3V, so if VG is about 1V,
If d241000^tonari and VG are set to about 4.5V, then d2 will be 200A.

Next, a method for manufacturing an M I 5FET according to an embodiment of the present invention will be described with reference to FIG.

First, MOCVD is performed on a semi-insulating InP substrate 3.

Using a method capable of high-purity crystal growth such as halide VPE, an InGaAs layer 2 with a thickness of 0.2 to 1 μm is formed by lattice matching. In order to increase the device operation speed, this crystal layer 2 is preferably as high in purity as n <10" c+++-2 + more preferably n < 1015 cm-2. Next, the InP layer 1 with a film thickness of 100 to 1000 cm is used.
Continue to form. The steps after forming the gate insulating film 4 are carried out according to normal MISFET steps.

Here, when the gate insulating film 4 is made of wood, the MIS interface is far from the channel, so the influence on drift etc. is smaller compared to a normal MISFET. It is desirable to adopt it. Preferably, photo-CVD method, ECR plasma CV
Si
O□, SiN.

A film of P ON , P AsO, etc. or a composite film thereof is formed and used. Next, a gate electrode fM5 is formed using AI by EB evaporation or W by sputtering,
Furthermore, it is processed into a shape having a predetermined L/W using photolithography. Source of this element.

The drain portion is preferably as shown by the dotted line in FIG.
After doping with impurities by a method such as Sl ion implantation to form impurity-doped regions 8, 8, the gate insulating film 4 is
The entire portion is removed by etching, and an electrode 6.7 made of AuGe or the like is formed by a combination of a vacuum evaporation method and a lift-off method to complete the device.

In the embodiments of the present invention, the InP semiconductor layer 1 is undoped, but a doped crystal layer may be used if necessary, or it may have a two-layer structure of an undoped layer and a doped layer. good.

In this case, the threshold voltage of the transistor changes by about kNnd%/2ε depending on the doping amount ND, which can be used for ft threshold voltage control.

In the transistor realized by the embodiment of the present invention, electrons induced in the channel region form a two-dimensional electron gas, and depending on the film thickness and doping state of the InP semiconductor layer, enhancement type and depletion type operation are possible. Furthermore, although an amorphous layer is used as the gate insulating layer in this example, it is also possible to use a wide gap ■-v group compound semiconductor such as InAIIP or GaAlAs. .

Embodiment 2 In the present invention, the first semiconductor layer 1 in contact with the gate insulating film 4 in FIG. 1 and the second semiconductor layer 2 underlying it may be lattice mismatched. In this case, it is considered that the order of
It is rather smaller than the number of levels at the nPl interface. From this, the allowable range of mismatch is approximately 1 to 2 Φ. Therefore, in Example 1, InP and In□ which is lattice matched to this
-8GaxAs (X=0.47) was shown as an example, but
Considering mismatch of about 1-2%, x=0.3-0.
7In1-XGaXAS can be adopted. A particularly desirable structure is a composition with a mismatch of about 1%, 0.3<x<0.47; in this case, x
= 0.47, it is possible to obtain a larger electron mobility than the lattice-matched system, and in addition, the first semiconductor layer (InP) 1 with a thickness of about 1000 Å or less is elastically deformed in the form of a strained lattice. can be formed on the second semiconductor layer (InGaAs) 2 without generating many lattice defects. In addition, also in this Example 2, the subsequent MIS
The FET manufacturing process can be performed in two steps as in the first embodiment.

Example 3 In this example, the second semiconductor layer 2 shown in FIG. 1 is made of InP, and the first semiconductor layer 1 is made of InAIAkGaP or the like having a larger energy gap than that of InP.

Similar to Examples 1 and 2, these semiconductor laminated structures can be formed by methods such as MBE, VPE, MOCVD, etc., which are superior in laterality in thin layer growth and can yield highly pure films. If the first semiconductor layer 1 is In)<AA'1-xAs, then x=
This composition can be used because it has a lattice match with InP at around 0.52. However, the first
The first semiconductor layer 1 shown in the figure is as thin as about 1000 Å. Therefore, InGaAsk with x = 0.3 to 0.4 having a lattice misalignment of about 1f can also be used. Next, the first
Since the semiconductor layer 1 is in contact with the amorphous insulating layer 4 on the surface side, it is more desirable to use a ■-■ group compound containing In and P which has excellent interfacial characteristics with the amorphous insulating layer 4. In this case, InP
There will be a lattice mismatch with the lower layer, but if we allow a lattice mismatch of around 1 to 2 types like the above strained superlattice, then I nxkl, -X
In P, values up to x = 0.3 can be used.

At this time, the energy gap of InAIP is approximately 0.4 eV larger than that of InP, and it can be a suitable material for the first semiconductor layer.

Based on a similar idea, InG was used as the second semiconductor layer in this example.
It is also clear that strained lattice systems such as aAs, InAsP etc. can be used.

In this embodiment as well, the MISFET manufacturing process after the formation of semiconductor stacks is carried out in accordance with the first embodiment.

In the above embodiments, as the substrate on which the semiconductor layer is formed, an InP bulk substrate, an insulating substrate such as sapphire, a substrate in which InP is hetero-epitched on Si, etc. can be used.

FIG. 3 shows an example using an InP/Si substrate. Note that GaAs, Gap, and InGaAs are used to improve crystallinity between these substrates and the semiconductor stack.

Of course, those having various buffer layers such as I n AJ As can also be used. In addition, in FIG. 3, 9 is a buffer layer for epitaxial growth, and 10 is an epitaxial layer.

<Effects of the Invention> As described above, the present invention provides an MI having a structure including a semiconductor active layer formed by stacking a plurality of 111-V compounds having different energy gaps, and a gate insulating film formed on the semiconductor active layer.
In the SFET, the first m-v compound layer in contact with the gate insulating layer has a larger band gap than the second layer below it, and both layers form a matched lattice or strained lattice with excellent interface characteristics. It is characterized by the fact that conventional MISFE
It has become possible to improve the stability of element operation, which was a problem with T, while maintaining the characteristics of MISFET that can handle even larger voltage amplitudes, while maintaining the characteristics of MISFET, such as two-dimensional electron gas? This makes it possible to form high-speed electronic devices using

In particular, the M I 5F containing InGaAs of Examples 1 and 2
ET is effective for the construction of high-speed logic ICs due to its high mobility characteristics, and is also effective for the construction of high-speed logic ICs, etc.
ISFETs can be effectively utilized in the construction of high-output, high-speed devices due to the InPO material properties (high peak velocity, high electric field resistance, etc.).

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of an MIS field effect transistor according to an embodiment of the present invention, and FIG. 2 shows whether a positive voltage is applied to the element shown in FIG. FIG. 3 is a diagram illustrating the structure of a MIS type field effect transistor according to another embodiment of the present invention. 1... A first semiconductor layer in contact with the gate insulating layer, 2...
- Second semiconductor layer, 3... Substrate, 4... Gate insulating layer, 5... Gate electrode, 6, 7... Source and drain electrode, 8... Impurity doped region, 9...
... Buffer layer for epitaxial growth, 10... Epitaxial layer.

Claims (1)

[Claims] 1. A substrate, a plurality of semiconductor layers formed on the substrate and formed by stacking III-V group compounds with different energy gaps Eg, and a gate insulating layer formed on the semiconductor stack. a field effect transistor having a first semiconductor layer in contact with the gate insulating layer, in which at least one of the substrate or the semiconductor layer is made of a III-V compound containing In and P; A III-V compound semiconductor field effect transistor having a larger energy gap than a second semiconductor layer and forming a matched lattice or strained lattice with the second semiconductor layer. 2. The III-V compound according to claim 1, wherein the lattice mismatch between the first semiconductor layer in contact with the gate insulating layer and the second semiconductor layer below it is within 2%. Semiconductor field effect transistor. 3. The thickness of the first semiconductor layer in contact with the gate insulating layer is 1
A III-V compound semiconductor field effect transistor according to claim 1, characterized in that the field effect transistor has a thickness of 000 Å or less. 4. The first semiconductor layer in contact with the gate insulating layer is made of InP, and the second semiconductor layer is made of InGaAs.
III-V compound semiconductor field effect transistor. 5. The first semiconductor layer in contact with the gate insulating layer is In_1
____XAl_XP, In_1_-_XGa_XP, I
n_1_-_XAl_XAs, and the second semiconductor layer is InP, In_1_-_XGa_XAs,
I according to claim 1 or 2, characterized in that it is any one of InAs_1_-_XP_X
II-V compound semiconductor field effect transistor.