JPS55117282A - 3[5 group compound semiconductor mosfet - Google Patents

3[5 group compound semiconductor mosfet

Info

Publication number
JPS55117282A
JPS55117282A JP2457379A JP2457379A JPS55117282A JP S55117282 A JPS55117282 A JP S55117282A JP 2457379 A JP2457379 A JP 2457379A JP 2457379 A JP2457379 A JP 2457379A JP S55117282 A JPS55117282 A JP S55117282A
Authority
JP
Japan
Prior art keywords
composition
forbidden band
inp
mosfet
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2457379A
Other languages
Japanese (ja)
Other versions
JPS6321354B2 (en
Inventor
Takeshi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2457379A priority Critical patent/JPS55117282A/en
Publication of JPS55117282A publication Critical patent/JPS55117282A/en
Publication of JPS6321354B2 publication Critical patent/JPS6321354B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To provide an FET having low threshold value employing III-V compound semiconductor by separating a semiconductor layer making contact with a gate oxide film from a semiconductor layer formed with channel in hetero structure. CONSTITUTION:An InGaAsP capable of matching lattice completely with a p-type InP substrate and varying widely the forbidden band width of the srbstrate is grown in gas phase on the substrate by continuously altering the composition of the gas in the range less than 0.5mum of thickness and finally returning it to the composition of InP. With this method the difference of the forbidden band width of the surface and internal crystal layers is set to become Eg1-Eg2>0.2eV and the difference of the lattice constant of both the crystals is set to become ¦a1-a2¦< 0.02a1. Then, ion is implanted to the depth becoming no change in composition to form n-type source 7 and drain 8 thereon so as to form ohmic electrodes 11, 12. The gate film 13 of Al2O3 and aluminum electrode 14 are formed on the InP crystal surface to complete the MOSFET. With this configuration an inversion layer can be readily formed to form a channel in narrow width of forbidden band to lower the threshold voltage and accelerate the operation of the MOSFET.
JP2457379A 1979-03-05 1979-03-05 3[5 group compound semiconductor mosfet Granted JPS55117282A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2457379A JPS55117282A (en) 1979-03-05 1979-03-05 3[5 group compound semiconductor mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2457379A JPS55117282A (en) 1979-03-05 1979-03-05 3[5 group compound semiconductor mosfet

Publications (2)

Publication Number Publication Date
JPS55117282A true JPS55117282A (en) 1980-09-09
JPS6321354B2 JPS6321354B2 (en) 1988-05-06

Family

ID=12141902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2457379A Granted JPS55117282A (en) 1979-03-05 1979-03-05 3[5 group compound semiconductor mosfet

Country Status (1)

Country Link
JP (1) JPS55117282A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01119065A (en) * 1987-10-30 1989-05-11 Sharp Corp Iii-v compound semiconductor field-effect transistor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2505502Y2 (en) * 1991-02-08 1996-07-31 株式会社ノダ Decorative wall

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01119065A (en) * 1987-10-30 1989-05-11 Sharp Corp Iii-v compound semiconductor field-effect transistor

Also Published As

Publication number Publication date
JPS6321354B2 (en) 1988-05-06

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