JPS61199666A - Field-effect transistor - Google Patents
Field-effect transistorInfo
- Publication number
- JPS61199666A JPS61199666A JP60041695A JP4169585A JPS61199666A JP S61199666 A JPS61199666 A JP S61199666A JP 60041695 A JP60041695 A JP 60041695A JP 4169585 A JP4169585 A JP 4169585A JP S61199666 A JPS61199666 A JP S61199666A
- Authority
- JP
- Japan
- Prior art keywords
- plane
- epitaxial layer
- type epitaxial
- etching
- grow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 150000001875 compounds Chemical class 0.000 claims abstract description 10
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 3
- 238000003776 cleavage reaction Methods 0.000 claims description 3
- 230000007017 scission Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000007788 liquid Substances 0.000 abstract 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- MODGUXHMLLXODK-UHFFFAOYSA-N [Br].CO Chemical compound [Br].CO MODGUXHMLLXODK-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
Abstract
Description
【発明の詳細な説明】
し発明の背景と目的］
本発明は、電界効果トランジスタに係り、特に化合物半
導体によ、る絶縁ゲート電界効果トランジスタに関する
ものである。BACKGROUND AND OBJECTS OF THE INVENTION The present invention relates to field effect transistors, and more particularly to insulated gate field effect transistors made of compound semiconductors.
電界効果トランジスタは、多数キャリア素子であるため
、バイポーラトランジスタに比べて高速性であるなどの
優れた特徴を有している。特に化合物半導体による電界
効果トランジスタは、シリコンにするものより高速であ
るなどのメリットがある。電界効果トランジスタは、オ
ン抵抗を小さくするため、−・般に、特開昭５９−８３
７５号公報に示しであるように、第３図に示ずような縦
形構造のものが用いられてきた。第３図に示したＶ字形
ゲート部の作製は、結晶の異方性を利用し、エツチング
払により行われていた。したがって、チャネル領域は、
（１１１）面にできるので、電子移動度が小さく、チャ
ネル抵抗が増大し、その結果、オン抵抗が大きくなる。Since field effect transistors are majority carrier devices, they have superior features such as higher speed than bipolar transistors. In particular, field effect transistors made of compound semiconductors have the advantage of being faster than those made of silicon. In order to reduce the on-resistance of field effect transistors, generally
As shown in Japanese Patent No. 75, a vertical structure as shown in FIG. 3 has been used. The V-shaped gate portion shown in FIG. 3 was fabricated by etching using the anisotropy of the crystal. Therefore, the channel area is
Since it is formed in the (111) plane, the electron mobility is low and the channel resistance increases, resulting in a large on-resistance.
本発明は上記に鑑みてなされたもので、その目的とする
ところは、電子移動度が大きく、Ａ２時のチャネル抵抗
を低減でき、オン抵抗が小さい電界効果トランジスタを
提供することにある。The present invention has been made in view of the above, and an object of the present invention is to provide a field effect transistor that has high electron mobility, can reduce channel resistance at A2, and has low on-resistance.
１発明の概要」
本発明の特徴は、（００１）面を有する化合物半導体結
晶基板の表面に＜１１０＞へき開方向と４５°の角度を
なす矩形状の凹部を形成し、上記矩形状の凹部の側面を
なす（０１０）または（００１）面をチ１１ネルとして
用いる構成とした点にある。1 Overview of the Invention" The present invention is characterized by forming a rectangular recess forming an angle of 45 degrees with the <110> cleavage direction on the surface of a compound semiconductor crystal substrate having a (001) plane, and The point is that the (010) or (001) plane forming the side surface is used as a channel.
［実施例１
以下、本発明を第１図、第２図に示した実施例を用いて
詳細に説明Ｊる。[Example 1] Hereinafter, the present invention will be explained in detail using the example shown in FIGS. 1 and 2.
結晶学的に（１００）面をチャネルとするために、化合
物半導体結晶基板ＧａＡＳの（００１）面上の＜１００
＞方向に、第１図（ａ）に示すように、＜１１０＞へき
開方向と４５°の角度をなす矩形状の凹部Ｐを形成する
ようにエツチングを行う。ただし、エツチングはエッチ
ャントを選択して、第１図（ｂ）に示すように、（００
１）表面に対して垂直にエツチングを行う。このとき、
直方体にエツチングされた凹部Ｐの側面は、それぞれ（
０１０）、（００１）面となり、（１００）面と等価な
面となる。ＧａＡＳ系基板に垂直にエツチングするには
、通常の１ａｌＩＩ！−過酸化水素系あるいは臭素−メ
タノール系のエッチャントを用いる反応性イオン・エツ
チング法や反応性イオン・ビームエツチング法を用いる
。In order to make the crystallographic (100) plane a channel, <100 on the (001) plane of the compound semiconductor crystal substrate GaAS is
> direction, as shown in FIG. 1(a), etching is performed to form a rectangular recess P making an angle of 45° with the <110> cleavage direction. However, for etching, select the etchant and as shown in Figure 1(b), (00
1) Perform etching perpendicular to the surface. At this time,
The sides of the recess P etched into a rectangular parallelepiped are (
010) and (001) planes, which are equivalent to the (100) plane. To perform vertical etching on a GaAS-based substrate, use the usual 1alII! - Use a reactive ion etching method or a reactive ion beam etching method using a hydrogen peroxide-based or bromine-methanol-based etchant.
次に、実際に電界効果トランジスタを作成する方法につ
いて説明する。第２図は本発明の電界効果トランジスタ
の一実施例を示す縦断面図である。Next, a method for actually manufacturing a field effect transistor will be explained. FIG. 2 is a longitudinal sectional view showing an embodiment of the field effect transistor of the present invention.
まず、（００１）面を有する半絶縁性ＧａＡｓ基板１上
にＰ＋型エピタキシャル１２．ｎ型エピタキシャル膚３
およびＰ型エピタキシャルＨ４を順次成長させる。Ｐ
型エピタキシャルＷ４２のキャリア濃度は２ Ｘ １０
１８ｃｍ−３、ｎ型エピタキシャルＷＪ３のキャリア濃
度は１ ｘ １０１６ｃｍ’ 、 Ｐ型エピタキシャル
層４のキャリア濃度は５×１０１７Ｃ［３である。次に
、フォトレジスト液を厚さ１μｍ塗布し、通常のフォト
・リングラフイー法を用いて基板１上にパターンを作成
する。そして、未硬化のフォトレジスト液を除去後、基
板１に垂直にｎ型エピタキシャル１ｌＩ３の中間までエ
ツチングする。このときのエツチング部の底面は（００
１）面で側面は（１００）面と（０１０）面である。First, a P+ type epitaxial layer 12 is formed on a semi-insulating GaAs substrate 1 having a (001) plane. n-type epitaxial skin 3
and P-type epitaxial H4 are sequentially grown. P
The carrier concentration of type epitaxial W42 is 2×10
18 cm-3, the carrier concentration of the n-type epitaxial layer WJ3 is 1 x 1016 cm', and the carrier concentration of the P-type epitaxial layer 4 is 5 x 1017 C[3. Next, a photoresist solution is applied to a thickness of 1 .mu.m, and a pattern is created on the substrate 1 using an ordinary photolithography method. After removing the uncured photoresist solution, etching is performed perpendicularly to the substrate 1 to the middle of the n-type epitaxial layer 1lI3. At this time, the bottom surface of the etched part is (00
1) and the side surfaces are the (100) plane and the (010) plane.
次に、ゲート酸化膜５を成長させ、電極をつけるだめの
コンタクト窓６を開孔し、そこにも酸化膜５を成長させ
る。最後に、金、アルミ等の金属電極７を蒸着して、ソ
ース電極およびゲート電極を形成する。Next, a gate oxide film 5 is grown, a contact window 6 for attaching an electrode is opened, and the oxide film 5 is also grown there. Finally, a metal electrode 7 such as gold or aluminum is deposited to form a source electrode and a gate electrode.
８は電池、９は抵抗、１０は可変抵抗を示す。8 is a battery, 9 is a resistor, and 10 is a variable resistor.
なお、化合物半導体基板としてＧａＡＳを用いたが、Ｉ
ｎＰを用いてもよい。Although GaAS was used as the compound semiconductor substrate, I
nP may also be used.
［発明の効果」
上記した本発明によれば、チャネル部分が（１００）面
と等価な面を用いであるため、電子移動度が大きく、オ
ン時のチャネル抵抗を低減でき、オン抵抗を小さくでき
るという効果がある。[Effects of the Invention] According to the present invention described above, since the channel portion uses a plane equivalent to the (100) plane, the electron mobility is large, and the channel resistance when turned on can be reduced, and the on-resistance can be reduced. There is an effect.
第１図は、本発明の電界効果トランジスタを製造する場
合の電界矩形状の凹部を形成する工程を示す図、第２図
は本発明の電界効果ｌ・ランジスタの一実施例を示す縦
断面図、第３図は従来の電界効果トランジスタの縦断面
図である。
１・・・半絶縁性化合物半導体基板。
２・・・Ｐ）エピタキシャル層。
３・・・「１型工ピタキシヤル層。
４・・・Ｐ型エピタキシャル層。
５・・・酸 化 膜。
６・・・コンタクト窓。
７・・・金属電極。FIG. 1 is a diagram illustrating the process of forming an electric field rectangular recess when manufacturing the field effect transistor of the present invention, and FIG. 2 is a longitudinal cross-sectional view showing an embodiment of the field effect transistor of the present invention. , FIG. 3 is a longitudinal sectional view of a conventional field effect transistor. 1...Semi-insulating compound semiconductor substrate. 2...P) Epitaxial layer. 3... Type 1 epitaxial layer. 4... P type epitaxial layer. 5... Oxide film. 6... Contact window. 7... Metal electrode.
Claims (3)
面に、〈１１０〉へき開方向と４５°の角度をなす矩形
状の凹部を形成し、前記矩形状の凹部の側面をなす（０
１０）または（００１）面をチャネルとして用いる構成
としたことを特徴とする電解効果トランジスタ。(1) A rectangular recess forming an angle of 45° with the <110> cleavage direction is formed on the surface of a compound semiconductor crystal substrate having a (001) plane, and a (0
10) or (001) plane as a channel.
求の範囲第１項記載の電界効果トランジスタ。(2) The field effect transistor according to claim 1, wherein the compound semiconductor crystal substrate is InP.
請求の範囲第１項記載の電界効果トランジスタ。(3) The field effect transistor according to claim 1, wherein the compound semiconductor crystal substrate is GaAs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60041695A JPS61199666A (en) | 1985-03-01 | 1985-03-01 | Field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60041695A JPS61199666A (en) | 1985-03-01 | 1985-03-01 | Field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61199666A true JPS61199666A (en) | 1986-09-04 |
Family
ID=12615560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60041695A Pending JPS61199666A (en) | 1985-03-01 | 1985-03-01 | Field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61199666A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714781A (en) * | 1995-04-27 | 1998-02-03 | Nippondenso Co., Ltd. | Semiconductor device having a gate electrode in a grove and a diffused region under the grove |
| US5776812A (en) * | 1994-03-30 | 1998-07-07 | Nippondenso Co., Ltd. | Manufacturing method of semiconductor device |
| US5780324A (en) * | 1994-03-30 | 1998-07-14 | Denso Corporation | Method of manufacturing a vertical semiconductor device |
| US5925911A (en) * | 1995-04-26 | 1999-07-20 | Nippondenso Co., Ltd. | Semiconductor device in which defects due to LOCOS or heat treatment are suppressed |
| US6015737A (en) * | 1991-07-26 | 2000-01-18 | Denso Corporation | Production method of a vertical type MOSFET |
| US6603173B1 (en) | 1991-07-26 | 2003-08-05 | Denso Corporation | Vertical type MOSFET |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS598375A (en) * | 1982-07-05 | 1984-01-17 | Matsushita Electronics Corp | Insulated gate field-effect transistor |
-
1985
- 1985-03-01 JP JP60041695A patent/JPS61199666A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS598375A (en) * | 1982-07-05 | 1984-01-17 | Matsushita Electronics Corp | Insulated gate field-effect transistor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6015737A (en) * | 1991-07-26 | 2000-01-18 | Denso Corporation | Production method of a vertical type MOSFET |
| US6603173B1 (en) | 1991-07-26 | 2003-08-05 | Denso Corporation | Vertical type MOSFET |
| US5776812A (en) * | 1994-03-30 | 1998-07-07 | Nippondenso Co., Ltd. | Manufacturing method of semiconductor device |
| US5780324A (en) * | 1994-03-30 | 1998-07-14 | Denso Corporation | Method of manufacturing a vertical semiconductor device |
| US5925911A (en) * | 1995-04-26 | 1999-07-20 | Nippondenso Co., Ltd. | Semiconductor device in which defects due to LOCOS or heat treatment are suppressed |
| US5714781A (en) * | 1995-04-27 | 1998-02-03 | Nippondenso Co., Ltd. | Semiconductor device having a gate electrode in a grove and a diffused region under the grove |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1214575A (en) | Method of manufacturing gaas semiconductor device | |
| CA1148272A (en) | Vertical field effect transistor with improved gate and channel structure | |
| EP0551110B1 (en) | Compound semiconductor devices | |
| JPS598375A (en) | Insulated gate field-effect transistor | |
| JP3377022B2 (en) | Method of manufacturing heterojunction field effect transistor | |
| JPS61199666A (en) | Field-effect transistor | |
| JPS60251671A (en) | Field-effect type transistor and manufacture thereof | |
| JPS62190772A (en) | Field-effect transistor and manufacture thereof | |
| JPS6115375A (en) | Hetero junction fet | |
| JPH02192172A (en) | Superconducting transistor | |
| JP2745624B2 (en) | Method for manufacturing field effect transistor | |
| JP3082401B2 (en) | Selective etchant and method for manufacturing semiconductor device | |
| JPS6323667B2 (en) | ||
| JP2526492B2 (en) | Method for manufacturing semiconductor device | |
| GB2217108A (en) | Semiconductor device etching using indium containing etch stop | |
| JPH05198554A (en) | Manufacture of semiconductor device | |
| JPS62115782A (en) | Manufacture of semiconductor device | |
| JPH0123955B2 (en) | ||
| JPH0323641A (en) | Manufacture of field-effect transistor | |
| JPH0797634B2 (en) | Field effect transistor and manufacturing method thereof | |
| JPS63281474A (en) | Semiconductor device | |
| JPS6222488A (en) | Manufacture of gallium arsenide schottky barrier junction gate type field effect transistor | |
| JPS6367342B2 (en) | ||
| JPH0323642A (en) | Manufacture of field-effect transistor | |
| JPH01166571A (en) | Semiconductor device |