JPS61199666A - Field-effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

BACKGROUND AND OBJECTS OF THE INVENTION The present invention relates to field effect transistors, and more particularly to insulated gate field effect transistors made of compound semiconductors.

Since field effect transistors are majority carrier devices, they have superior features such as higher speed than bipolar transistors. In particular, field effect transistors made of compound semiconductors have the advantage of being faster than those made of silicon. In order to reduce the on-resistance of field effect transistors, generally
As shown in Japanese Patent No. 75, a vertical structure as shown in FIG. 3 has been used. The V-shaped gate portion shown in FIG. 3 was fabricated by etching using the anisotropy of the crystal. Therefore, the channel area is
Since it is formed in the (111) plane, the electron mobility is low and the channel resistance increases, resulting in a large on-resistance.

The present invention has been made in view of the above, and an object of the present invention is to provide a field effect transistor that has high electron mobility, can reduce channel resistance at A2, and has low on-resistance.

1 Overview of the Invention" The present invention is characterized by forming a rectangular recess forming an angle of 45 degrees with the <110> cleavage direction on the surface of a compound semiconductor crystal substrate having a (001) plane, and The point is that the (010) or (001) plane forming the side surface is used as a channel.

[Example 1] Hereinafter, the present invention will be explained in detail using the example shown in FIGS. 1 and 2.

In order to make the crystallographic (100) plane a channel, <100 on the (001) plane of the compound semiconductor crystal substrate GaAS is
> direction, as shown in FIG. 1(a), etching is performed to form a rectangular recess P making an angle of 45° with the <110> cleavage direction. However, for etching, select the etchant and as shown in Figure 1(b), (00
1) Perform etching perpendicular to the surface. At this time,
The sides of the recess P etched into a rectangular parallelepiped are (
010) and (001) planes, which are equivalent to the (100) plane. To perform vertical etching on a GaAS-based substrate, use the usual 1alII! - Use a reactive ion etching method or a reactive ion beam etching method using a hydrogen peroxide-based or bromine-methanol-based etchant.

Next, a method for actually manufacturing a field effect transistor will be explained. FIG. 2 is a longitudinal sectional view showing an embodiment of the field effect transistor of the present invention.

First, a P+ type epitaxial layer 12 is formed on a semi-insulating GaAs substrate 1 having a (001) plane. n-type epitaxial skin 3
and P-type epitaxial H4 are sequentially grown. P
The carrier concentration of type epitaxial W42 is 2×10
18 cm-3, the carrier concentration of the n-type epitaxial layer WJ3 is 1 x 1016 cm', and the carrier concentration of the P-type epitaxial layer 4 is 5 x 1017 C[3. Next, a photoresist solution is applied to a thickness of 1 .mu.m, and a pattern is created on the substrate 1 using an ordinary photolithography method. After removing the uncured photoresist solution, etching is performed perpendicularly to the substrate 1 to the middle of the n-type epitaxial layer 1lI3. At this time, the bottom surface of the etched part is (00
1) and the side surfaces are the (100) plane and the (010) plane.

Next, a gate oxide film 5 is grown, a contact window 6 for attaching an electrode is opened, and the oxide film 5 is also grown there. Finally, a metal electrode 7 such as gold or aluminum is deposited to form a source electrode and a gate electrode.

8 is a battery, 9 is a resistor, and 10 is a variable resistor.

Although GaAS was used as the compound semiconductor substrate, I
nP may also be used.

[Effects of the Invention] According to the present invention described above, since the channel portion uses a plane equivalent to the (100) plane, the electron mobility is large, and the channel resistance when turned on can be reduced, and the on-resistance can be reduced. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the process of forming an electric field rectangular recess when manufacturing the field effect transistor of the present invention, and FIG. 2 is a longitudinal cross-sectional view showing an embodiment of the field effect transistor of the present invention. , FIG. 3 is a longitudinal sectional view of a conventional field effect transistor. 1...Semi-insulating compound semiconductor substrate. 2...P) Epitaxial layer. 3... Type 1 epitaxial layer. 4... P type epitaxial layer. 5... Oxide film. 6... Contact window. 7... Metal electrode.

Claims (3)

[Claims] (1) A rectangular recess forming an angle of 45° with the <110> cleavage direction is formed on the surface of a compound semiconductor crystal substrate having a (001) plane, and a (0
10) or (001) plane as a channel. (2) The field effect transistor according to claim 1, wherein the compound semiconductor crystal substrate is InP. (3) The field effect transistor according to claim 1, wherein the compound semiconductor crystal substrate is GaAs.