JPS6178174A - Junction gate type field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a junction gate type field-effect transistor having self- alignment type gate structure, which has small parasitic resistance and noises therefrom are low, by forming a semiconductor buffer layer having a mixed- crystal composition different from a semiconductor gate layer between the semiconductor gate layer and a gate electrode metallic layer and shaping the gate electrode metallic layer to an eave form to the semiconductor buffer layer. CONSTITUTION:A first metal 5 and a second metal 6 for a gate electrode are patterned to a striped shape in the inverted mesa direction, and only a p type In0.74Ga0.26As0.56P0.44 layer 4 is etched selectively by an etching liquid consisting of sulfuric acid, hydrogen peroxide and water while using the metals 5 and 6 as masks. Only a p type InP layer 3 is etched selectively by an etching liquid composed of phosphoric acid and hydrochloric acid while employing the p type In0.74Ga0.26As0.56P0.44 layer 4 as a mask. The p type InP layer 3 is etched selectively without side etching and takes a form close to approximately verticality at that time. When a third metal 7 is evaporated onto the whole surface, the eave of the gate electrode shaped by selectively etching the p type In0.74Ga0.26 As0.56P0.44 layer 4 forms a shadow, thus isolating both a gate and a source and both the gate and a drain in a self-alignment manner.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to improvements in junction gate field effect transistors, particularly field effect transistors suitable for low noise, high speed electronic circuits.

(Prior Art) Field effect transistors, which are important as electronic circuit elements, need to have large source-drain mutual conductance and reduced parasitic resistance in order to operate at low noise and high speed. To achieve this, the gate length, gate-drain distance, and gate-source distance need to be shortened, and self-aligned structures are usually widely used. By the way, the gate length of a junction gate type field effect transistor corresponds to the length of the pn junction, and a structure in which the pn junction, that is, the gate part is separated from the source and drain in a self-aligned manner, has been known. That is, a pn junction is formed by a heterojunction, and a striped reverse mesa is used as a gate gold pAt mask? This structure is created by selective etching, and at this time, side etching produces an overhang of silicate gold, which becomes a shadow during the deposition of ohmic electrodes for the source and drain, and the gate is separated from the source and drain in a self-aligned manner. Deoru (US magazine 'Proceedin')
gsof the 7th Conference o
n 3o1id Device', 157 (197
5)).

In this case, the amount of side etching corresponds to the gate acoustic source and gate-drain distances, and is preferably as small as possible from the perspective of reducing parasitic resistance. However, in this conventional structure, the height of the gate mesa is adjusted to Since it is necessary to make the side etching sufficiently higher than the thickness, it is extremely difficult to control the side etching, which is formed at the same time as the mesa etching of the gate, to a total thickness of 2 μm or less. Therefore, it has been disadvantageous that it is not possible to obtain a low-noise field effect transistor with small parasitic resistance between the gate and source and between the gate and drain, large mutual conductance, and low noise.

(Object of the Invention) The object of the present invention is to eliminate these drawbacks and provide a self-aligned gate with a gate-source distance and a gate-drain distance of 0.2μ or less, low parasitic resistance, and low noise. An object of the present invention is to provide a junction gate field effect transistor structure of gold.

(Structure of the Invention) The structure of the present invention is such that a semiconductor layer of a first conductivity type is formed on a semiconductor substrate, a semiconductor gate layer of a second conductivity type is formed on a part of this semiconductor layer, and this semiconductor gate layer and this semiconductor layer are formed on a part of this semiconductor layer. In a junction gate field effect transistor, electrode metal layers are provided on the semiconductor layers on both sides of a semiconductor gate layer to serve as a gate, a drain, and a source, respectively, and the semiconductor gate layer is provided between the semiconductor gate layer and the gate electrode metal layer. A semiconductor layer with a mixed crystal composition different from the layer is provided,
The gate electrode metal layer is characterized in that it has an eave shape with respect to the semiconductor buffer layer.

(Example) Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view of a junction gate field effect transistor according to an embodiment of the present invention. As shown in the figure, this junction gate field effect transistor has a layer thickness of 0.2 μm on a substrate 1 made of semi-insulating InP.

Career Il! 1 degree is l X I Q 17cns-”
n-type In0.74GaOJg8S 0.56 P 0
．． Active shoulder consisting of 44 layers 2 and layer thickness 0.5μ groove P-type InP layer 3 with carrier concentration 5X1017α-3 and layer thickness 01
P-type InO, 74Gao, zs A30.5, which becomes a buffer layer with a μ carrier concentration of 5×1018a11-8
11 Po, 44 layers 4, and the gate has an inverted mesa stripe-like gate layer of gold, and its electrodes include a first gold layer made of TI and a second gold layer made of 1I45°Pt.
6 and a third gold ff17 made of AuGe, the source/drain ? JC Metals is the third metal 7
It becomes.

The method for forming the gate of this structure is to first mask the first gold N5 and the second metal 6 of the gate electrode in a stripe pattern with a length of 250 μm and a width of 1.5 μm in the reverse mesa direction. n O, 74aao, 26
As o, ss P O, 44 Only layer 4 is selectively etched with an etching solution consisting of sulfuric acid, hydrogen peroxide, and water.

Next, p M In O, 74 Gao, zs Aso,
aa PO, 44 layers 4t+v2, and only the p-type InP layer 3 is selectively etched with an etching solution consisting of phosphoric acid and hydrochloric acid. At this time, p-type In0.74GaOJ6
In the selective etching of the AS0.56F0.44 layer 4, side etching is dominant, but in the selective etching of the p-type InP layer 3, there is no side etching and the shape is almost vertical. Next, when the third metal 7t is deposited on the entire surface, p-type In0.74Ga0.26Aso, sa PG, 4
Since the eaves of the gate electrode created by selective etching of the 4th layer 4 create a shadow, the gate and source and the gate and drain are separated by self-alignment.

In this example, side etch 1-rip type In0.74Ga (1,26 SG,
56 P 0.44N4 (DSotDMiash, p type I
n O, 74 Ga O, 26 As o, ssP O,
Since the layer thickness of the 44l layer 4 is 0.1 μm, the amount of side etching on the mesa can be controlled to about 0.2 μm, and the sieveness of the mesa can be controlled by side etching. p-type I independently of
The thickness of nPM13 can be set arbitrarily.

Therefore, the parasitic resistance between the gate and the source and between the gate and the drain is about 20 when the gate is 250 μm, which is significantly reduced to less than 1/10 compared to the conventional method, resulting in a low-noise junction with high transconductance. A gated field effect transistor is obtained.

The material and mixed crystal composition of each layer constituting the element are not limited to those of this embodiment, but may be any material or mixed crystal composition that can be selectively etched. Also. The doping amount and layer thickness of each layer may be any value, and the electrode metal may be any metal as long as it is resistant to the etchant that performs mesa etching and can establish ohmic contact.

(Effects of the Invention) As detailed above, according to the present invention, by sandwiching the semiconductor buffer layer 1 between the semiconductor gate layer and the gate electrode metal, the gate-source and gate-drain distances can be completely shortened. Thus, a junction gate field effect transistor with reduced parasitic resistance and high transconductance can be obtained.

[Brief explanation of drawings]

Figure $1 is a schematic cross-sectional view of one embodiment of the present invention. In the figure, l is the substrate, 2 is n-type In0.74Ga0,2
@A$0. MPo, 44 layers, 3 is p-type InP/l, 4 is p-type In0.76Ga O,24As o, sa Po
, 44 layers, 5 is the first metal, 6 is the second metal, and 7Vi is the third metal.

Claims (1)

[Claims] A semiconductor layer of a first conductivity type is formed on a semiconductor substrate, a semiconductor gate layer of a second conductivity type is formed on a part of this semiconductor layer, and a semiconductor gate layer of a second conductivity type is formed on this semiconductor gate layer and the semiconductor layers on both sides of this semiconductor gate layer, respectively. In a junction gate field effect transistor provided with an electrode metal layer and used as a gate, a drain, and a source, respectively, a semiconductor buffer layer having a mixed crystal composition different from that of the semiconductor gate layer between the semiconductor gate layer and the gate electrode metal layer. A junction gate field effect transistor characterized in that the gate electrode metal layer has an eave shape with respect to the semiconductor buffer layer.