JPH01154565A - Manufacture of junction fet - Google Patents

Abstract

PURPOSE:To eliminate the exfoliation of a gate electrode becoming a gate in case of forming a gate, to form the gate in a self-alignment manner, and to manufacture a junction FET having a high frequency and a large current in a high yield by providing a sidewall having a predetermined thickness on the side face of the gate electrode, providing in advance an overhang extending in a predetermined length on the periphery of a gate region on the gate electrode, and depositing source/drain electrode as a gate electrode mask. CONSTITUTION:A gate electrode 4 having an overhang 41 is formed on a gate region, and a sidewall 13 made of Si3N4 or the like is formed on the side face of the electrode 4. Here, with the electrode 4 as a mask an InGaAsP layer 14' is removed in a predetermined depth from the surface by etching, for example, by a reactive ion beam etching method. Further, an InGaAsP layer 14' remaining under the sidewall 13 and on its periphery is isotropically etched. Then, with the electrode 4 and the sidewall 13 as masks an InP layer 7'' is etched. Thereafter, the sidewall 13 is removed, Au or the like is deposited perpendicularly to the surface of the substrate 1, and a source electrode and a drain electrode are then formed.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method for forming a gate, gate electrode, and source/drain electrode in a high frequency/high current junction FET for optical communication.

The purpose is to prevent peeling of the gate electrode, which serves as a mask when forming the gate.

An eaves extending over a semiconductor layer of opposite conductivity type for forming a gate formed on the surface of a K-type semiconductor, facing the semiconductor layer and extending by a predetermined length (X) around the gate formation region. a sidewall layer of a predetermined thickness made of a material that is not removed during etching of the semiconductor layer is formed on the side surface of the gate electrode, and the semiconductor layer is selected using the gate electrode and the sidewall layer as a mask. A gate made of the semiconductor layer is formed in the gate formation region by etching, and after removing the sidewall layer, a metal layer is deposited from a direction perpendicular to the semiconductor surface using the gate electrode as a mask. The method includes the step of forming a source/drain electrode made of the metal layer at a position separated by the distance X from the formation region.

[Industrial application field]

The present invention relates to a method for manufacturing a junction FET.

More specifically, the present invention relates to a method for forming gates, gate electrodes, and source/drain electrodes in high-frequency, high-current junction FETs used as semiconductor laser drivers for optical communications.

[Conventional technology]

Figure 2 shows p formed by diffusion or ion implantation.
Junction FET with n-junction (J-FET)
The structure of For example, a channel layer 2 made of n-type 1nP is formed on a semi-insulating substrate 1 made of InP (indium phosphorous), and an impurity is implanted into a predetermined region of the channel layer 2 by diffusion or ion implantation to make it p-type. Game D
N region 3 is formed. Then, a gate electrode 4 is formed on the gate region 3, and a source electrode 5 and a drain electrode 6 are formed on the channel layer 2 on both sides of the gate region 3, respectively.

Junction FETs made of compound semiconductors such as those described above are used as cylindrical-frequency, high-current drivers necessary to drive semiconductor lasers for optical communications. 3 and the source electrode 5 and drain electrode 6 are required to be as short as possible.

However, in the gate region 3 formed by diffusion etc. in the junction FET described above, it is difficult to control the gate length and the gate-source/drain distance to desired minute dimensions, so it is necessary to reduce these. has manufacturing technology limitations. On the other hand, as shown in FIG.

A junction PET having a structure in which a gate 7 made of a semiconductor layer of an opposite conductivity type is provided on a channel layer 2 is known. The gate electrode 4 provided on the gate 7 and the source electrode 5 and drain electrode 6 provided on both sides thereof are the same as those shown in FIG.

In the structure shown in FIG. 3, the gate length and the gate-source/drain distance are determined by the pattern accuracy and positional accuracy of the gate 7 and each electrode, so that desired minute dimensions can be achieved relatively easily.

[Problem that the invention seeks to solve]

However, when the gate 7 is formed by etching, the following problem occurs when the gate length becomes short.

That is, referring to FIG. 4(a), a channel layer 2 made of, for example, InP and a layer 7' of, for example, InGaAsP for forming a gate are formed on a substrate 1. On top of this, a gate electrode is formed.

For example, an Au layer is formed, and the gate electrode 4 is formed by first etching this Au layer using a mask 10 made of SiO□ (silicon dioxide) or 5i3N4 (silicon nitride). Next, as shown in FIG. 4(b), the semiconductor layer 7' is etched using the gate electrode 4 as a mask. The semiconductor layer 7' is etched in the thickness direction, and at the same time, the lower part of the gate electrode 4 is side etched. When the etching in the thickness direction is completed, as shown in Fig. 4 (
As shown in c), only a small portion remains in contact with the gate electrode 4. As a result, the gate electrode 4 is likely to peel off. Further, the gate 7 has a trapezoidal shape with a widened base.

That is, only the lower part of the upper surface of the nine trapezoids effectively functions as a gate.

Therefore, it is necessary to design the original dimensions of the mask 10 in consideration of the amount of side etching as described above, and it is inevitable that this amount of side etching will be added between the gate and the source/drain. As described above, in the conventional gate forming method described above, there is a practical limit to the reduction of the gate length and the gate-source/drain distance.

An object of the present invention is to solve the above-mentioned problems in a method of etching a semiconductor layer constituting a gate using a gate electrode 1 as a mask.

Means for Solving Problem C] The above object includes a step of depositing a semiconductor layer of an opposite conductivity type on the surface of a semiconductor of one conductivity type, and a step of depositing a semiconductor layer of a predetermined value with respect to the semiconductor layer in a gate formation region on the semiconductor layer. a step of forming gate electrodes having eaves extending from the gate formation region to the periphery by a predetermined length (x) facing each other with an interval of Forming a gate made of the semiconductor layer by forming a layer on the side surface of the gate electrode, and selectively removing the semiconductor layer around the gate formation region using the gate electrode and the sidewall layer as a mask. selectively removing the semiconductor layer, then removing the sidewall layer, and depositing a metal layer from a direction perpendicular to the semiconductor surface using the gate electrode as a mask. 2, comprising the step of forming source/drain electrodes on the semiconductor surface on both sides of the gate region, the source/drain electrodes being arranged at a distance of the predetermined length (X) from the gate region. This is achieved by a manufacturing method.

[For production]

By providing a side wall of a predetermined thickness on the side surface of the gate electrode, side etching that occurs when etching the semiconductor layer constituting the gate is stopped at the lower part of the side wall. Further, a bottom portion extending by a predetermined length around the gate 6N region is provided in advance on the gate electrode.

By depositing the source/drain electrode as a gate electrode mask, a distance equal to the length of the bottom is maintained between the gate and source/drain electrodes.

In this way, the gate region and the source/drain region are formed in a self-aligned manner, and a junction FET having a desired minute gate length and gate-source/drain distance can be manufactured.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In the following drawings, the same parts as in the previously shown drawings are designated by the same reference numerals.

FIGS. 1(a) to 1) are sectional views of essential parts in steps of an embodiment of the present invention.

Referring to FIG. 1(a), 1. For example, on a semi-insulating substrate l made of high-resistance InP single crystal, using a known eviaxial growth technique, A channel layer 2 made of rnP type and a p-type InGaAsP layer 7' having a thickness of about 0.4 μm for forming a gate are sequentially deposited. Further, on the InGaAsP layer 7', a film with a thickness of approximately 70 mm is deposited using a known thin film technique such as electron beam evaporation.
A titanium (Ti) layer 8 having a thickness of 0 and a platinum (P) layer 9 having a thickness of about 1000 are sequentially deposited.

Next, using known lamination lithography techniques, the image shown in FIG.
), a resist layer 12 with a thickness of approximately 7,000 layers and an opening 11 corresponding to the gate region is formed on the PT layer 9, and then the resist layer 12 is formed in the opening 11 using the 11 layer 8 and the N layer 9 as electrodes. Au plating is applied to the exposed surface.

A gate electrode 4 made of this Au plating layer is formed.

In this case, the thickness of the Au plating layer is controlled so that the height of the gate electrode 4 from the surface of the PtJi 9 is approximately 1.0 μm. As a result, in the portion of the gate electrode 4 that protrudes from the upper surface of the resist layer 12, a plating layer also grows in the lateral direction, and an eaves portion 41 extends by a length (X) around the gate region determined by the opening 11. is formed. The length (x) of the eaves portion 41 is approximately equal to the difference between the height of the gate electrode 4 and the thickness of the resist layer 12.

Further, the thickness of the resist N12 is set so as to ensure a distance between the lower surface of the eaves portion 41 and the surface of the channel layer 2 that is sufficiently larger than the thickness of the source/drain electrodes to be formed later. Note that the 11th layer 8 is the InGaAsP layer 7.
For the purpose of increasing the adhesive force of the gate electrode 4 to the
Furthermore, the PT layer 9 is provided for the purpose of increasing the adhesive force between the gate electrode 4 and the 11 layer 8 made of Au.

Next, after removing the 1 resist N12, the 11 layer 8 and the PT layer 9 are etched away using the gate electrode 4 as a mask to obtain the structure shown in FIG. 1(C). This removal is 1
For example, the 11 layer 8 can be etched by reactive ion etching using CF (carbon tetrafluoride), and the Pt layer 9 can be etched by sputter etching using argon gas.

After the above step 5, for example, by using a known plasma CVD (chemical vapor deposition method), the first
As shown in FIG.
1, for example, by performing anisotropic etching from a direction perpendicular to the surface of the substrate 1 using a known reactive ion etching method using CF4 gas, so that Si is etched only on the side surfaces of the gate electrode 4.
3N4 layer 13' is left. In this way, Fig. 1(e)
As shown in , a 5iJ4 layer 13' is formed on the side surface of the gate electrode 4
A side wall 13 is formed. The thickness of the side wall 13 is 5iJ
The thickness is approximately the same as that of the fourth layer 13'. Further, the sidewall 13 is made of InGaAsP for forming a gate 7 which will be described later.
Any material that is not removed by the etching of layer 7' may also be used (an SiO□ layer may also be used).

Next, using the gate electrode 4 and sidewall 13 as a mask, 1
For example, the InGaAsP layer 7' is anisotropically etched from a direction perpendicular to the surface of the substrate 1 by a known reactive ion beam etching method using chlorine (C1□) gas.

In this case, (1) the rlGaAsP layer 7' is not entirely etched in its thickness direction, leaving about 0.5 μm. This is to prevent the channel layer 2 from being damaged by the ion beam etching. In this way, Figure 1 (fl
After obtaining the structure shown in , the remaining InGaA
The sP layer 7' is subjected to isotropic etching using a 90=5:5 mixed solution of, for example, sulfuric acid (HzSO, ):hydrogen peroxide (H20□):water (120).

The above mixed solution does not etch the channel layer 2 made of InP. As a result, as shown in FIG. Channel layer 2 is exposed.

Next, the side wall 13 is removed by a known reactive ion etching method using, for example, CF4 gas.

In this case, in order to eliminate anisotropy, the CF4 gas pressure is made higher than when forming the side wall 13.

In reactive ion etching using CF4 gas.

Channel N2, which is made of InP, is not etched.

By this etching, the structure shown in FIG. Using a known thin film technique, Au is deposited from a direction perpendicular to the surface of the channel layer 2.
A thin film is deposited to form a source electrode 5 and a drain electrode 6 on both sides of the gate electrode 4, as shown in FIG. 1(1).

In this case, an Au layer is additionally formed on the gate electrode 4.

As shown in FIG. 1(1), the Au layer is not formed between the gate electrode 4 and the source electrode 5 and drain electrode 6 due to the shadow of the eaves 41 of the gate electrode 4.

In other words, the distance between the gate and source/drain is
It is determined in a self-consistent manner by the length (X) of 1.

In the above embodiment, after forming the opening 11 corresponding to the gate region in the resist layer 12 in FIG. 1(b), the thickness of the Au plating layer formed in the opening 11 is changed.

By simply controlling the layer thickness of the Si, N4 layer 13' formed on the side surface of the gate electrode 4, the gate length and the gate-source/drain distance are determined in a self-aligned manner. Moreover,
The InGaAs around the gate H region is used as a mask using the sidewall 13, which has good coupling properties with the compound semiconductor layer such as InGaAsP.
Since the P layer 7' is etched, no peeling of the mask layer occurs, and as a result, the gate 7 of a predetermined size can be formed.

FIGS. 5 fal to e) are sectional views of essential parts showing steps of another embodiment of the present invention.

Referring to FIG. 5(a), for example, on a substrate 1 made of semi-insulating InP single crystal, a film made of n-type InGaAsP with a thickness of about 300 nm is grown using a known epitaxial growth technique.
a channel layer 2 of about 3000 nm thick, and a p-type InP q 7'' of about 3000 nm thick for forming the gate.

For example, an InGaAsP layer 14' having a thickness of about 2000 layers is deposited to form a contact layer 14 to be described later.
Next, TiN8 and PT layer 9 are formed in the same manner as in the previous embodiment.
are deposited sequentially. Then, in the same manner as in the embodiment described above, a gate electrode 4 having an eaves portion 41 is formed on the gate region as shown in FIG. form 13.

Here, by a reactive ion beam etching method using, for example, argon gas, using the gate electrode 4 as a mask,
As shown in FIG. 5(C), an InGaAsP layer 14'
4' outside the surface layer by etching to a certain depth.

Furthermore, the remaining I
2 for the nGaAsP layer 14', for example, sulfuric acid (lhsOt) as described above: hydrogen peroxide (H20□): water () 1
Isotropic etching is performed using a 90=5:5 mixed solution of 20).

As a result, a contact layer 14 made of InGaAsP is formed under the gate electrode 4, as shown in FIG. 5(d). The contact layer 14 has a large contact resistance when the gate electrode 4 is formed directly on the +InP layer 7''.
This is provided for the purpose of reducing contact resistance by interposing an InGaAsP layer.

Next, using the gate electrode 4 and sidewall 13 as a mask,
The InP layer 7'' is etched. For this etching, a 3=2 mixed solution of hydrochloric acid (HCI) and water (11,0) is used to selectively remove the contact layer 14 and channel layer 2 made of InGaAsP. In this way, the structure shown in FIG. 5(e) is obtained.

After the above, in the same manner as in the previous embodiment.

After removing the sidewall 13, Au or the like is deposited vertically on the surface of the substrate 1 to form a source electrode and a drain electrode (not shown).

In this embodiment, a thick layer is generally required as a semiconductor layer constituting a gate, and whereas forming a quaternary compound such as InGaAs1' in a thick layer with a desired composition is relatively spaced, a thick layer is required. This has the advantage that the gate can be formed from an InP layer that is relatively easy to form.

〔Effect of the invention〕

According to the present invention, in manufacturing a junction FET having a gate made of a semiconductor layer, the gate electrode, which serves as a mask, does not peel off when forming the gate, the gate can be formed in a self-aligned manner, and high frequency and large current This has the effect of making it possible to manufacture junction FETs with high yield.

[Brief explanation of the drawing]

FIG. 1(a) or 1) is a sectional view of a main part in a process of an embodiment of the present invention. FIG. 2 is a sectional view of a main part of a conventional junction FET having a pn junction made of an impurity implanted layer. FIG. 3 is a sectional view of a main part of a conventional junction FET having a gate made of a deposited layer of conductivity type opposite to that of the channel layer. FIGS. 4(a) to 4(c) are sectional views of main parts for explaining problems in the conventional junction FET having the structure shown in FIG. 3. FIGS. 5(a) to 5(e) are sectional views of main parts in steps of another embodiment of the present invention. In fig. 1 is the board. 2 is the channel layer. 3 is the gate area. 4 is the gate electrode. 5 is the source electrode. 6 is the drain electrode. 7 is the gate. 7' and 14' are InGaAsP Ji. 7" is an InP layer. 8 is a Ti layer. 9 is a ptI3° 11 is an opening. 12 is a resist layer. 13 is a side wall. 13' is a 5iJ4 layer. 14 is a contact layer.

Claims (3)

[Claims] (1) A step of depositing a semiconductor layer of an opposite conductivity type on the surface of a semiconductor of one conductivity type; forming a sidewall layer of a predetermined thickness on a side surface of the gate electrode made of a material that is not removed during etching of the semiconductor layer; forming a gate made of the semiconductor layer by selectively removing the semiconductor layer around the gate formation region using the semiconductor layer as a mask; and after selectively removing the semiconductor layer, removing the sidewall layer. and depositing a metal layer from a direction perpendicular to the semiconductor surface using the gate electrode as a mask, so that the metal layer is deposited on the semiconductor surface on both sides of the gate region by the predetermined length from the gate region. 1. A method of manufacturing a junction FET, comprising the step of forming source/drain electrodes that are spaced apart. (2) The step of forming a gate made of the semiconductor layer includes etching the semiconductor layer to a predetermined depth by performing anisotropic etching from a direction perpendicular to the semiconductor surface using the gate electrode and the sidewall layer as a mask. and a step of removing the semiconductor layer around the gate formation region by removing the semiconductor layer by isotropic etching using the gate electrode and the sidewall layer as a mask. A method for manufacturing a junction FET according to claim 1, characterized in that: (3) The method for manufacturing a junction FET according to claim 1, wherein the semiconductor layer is made of InP, and a contact layer made of InGaAsP is formed between the semiconductor layer and the gate electrode.