JPH05283438A - Manufacture of two-step recess type fet - Google Patents

Abstract

PURPOSE:To obtain a forming method of a two-step recess type FET wherein each two-step recess is formed independently with excellent controllability, and the yield of an FET is increased. CONSTITUTION:A dummy gate 3 is formed on an N-GaAs active layer 2 on a semiinsulative GaAs substrate 1. A first recess trench 6 is formed on both sides of the dummy gate 3 by first etching. A region except the dummy gate 3 is covered with resist 55. After the dummy gate 3 is eliminated, a second recess trench 7 is formed by second etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an FET having a two-step recess type gate structure.

[0002]

2. Description of the Related Art FIGS.
It is a figure which shows the process of the manufacturing method of a step recess type | mold FET using sectional drawing. In this figure, 1 is semi-insulating GaA
s substrate, 2 is an n-GaAs active layer, 12 is, for example, Si
An insulating film such as an O film, 13 is a resist, and 14 is a side etching region in which the insulating film 12 is side-etched to an etching amount W _S. Reference numeral 8 represents a gate electrode, 66 is a recess groove formed in the first time, and 77 is a recess groove formed in the second time.

Next, a manufacturing method will be described. First, n-Ga is formed on the semi-insulating GaAs substrate 1 by ion implantation and annealing or epitaxial growth by the MBE method.
An As active layer 2 is provided. After that, source and drain electrodes are formed. Since FIG. 4 shows only the vicinity of the gate, the source and drain electrodes are not shown.

Next, after forming the insulating film 12 by, for example, the plasma CVD method, an opening is formed in the insulating film 12 by RIE using the resist 13 as a mask in the gate formation portion. The layer 2 is etched to a desired depth to form the recess groove 66 (FIG. 4A). Next, the insulating film 12 is formed with an HF-based solution.
Near the opening of the side etching area 1
4 (FIG. 4B), the n-GaAs active layer 2 is formed again.
Is etched to a desired depth to form a recess groove 77. In this way, a two-step recess structure as shown in FIG. 4C can be formed. Next, the gate electrode 8 is formed by the vapor deposition and lift-off process (FIG. 4D), the process is completed, and the two-stage recess type FET provided with the source electrode 9 and the drain electrode 10 as shown in FIG. Can be manufactured.

[0005]

A conventional two-step recess type F
ET, as described above, since the area of the second recess etching shown in FIG. 4 (b) has been controlled by the side etching amount W _S of the insulating film 12, the recess width W ₁ shown in FIG. 4 (c), The controllability of W ₂ was poor, which was a factor that deteriorated the yield of FETs.

The present invention has been made to solve the above problems, and is a manufacturing method suitable for improving the controllability of the recess width of a two-step recess type FET and improving the manufacturing yield of the FET. The purpose is to provide a method.

[0007]

A method of manufacturing a two-step recess type FET according to the present invention forms a dummy gate at a gate formation position on an active layer region on a semiconductor substrate, and the dummy gate is formed only on both sides of the dummy gate. The active layer region is etched to a desired depth to form a first recess groove, and then the region other than the dummy gate is covered with a resist. After removing the dummy gate, the active layer region in the removed portion is formed to a desired depth. The second recess groove is formed by etching to the depth.

In the formation of the first recess groove, after the dummy gate is formed, sidewalls are formed on both sides of the dummy gate, the dummy gate and the region other than the sidewall are covered with a resist, and then only the sidewall is removed. After that, the first recess groove is formed on the semiconductor active layer by etching.

[0009]

In the present invention, the depth and width of the first recessed groove in the first step can be controlled in different steps, and the depth and width of the second recessed groove in the second step can be controlled in separate steps. The property is improved.

Further, since the first recess groove is formed by utilizing the sidewalls on both sides of the dummy gate, the recess width can be accurately controlled by accurately controlling the thickness of the sidewall.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 (a) to 1 (e) and 2 (a) to 2 (e) are cross-sectional views showing manufacturing steps of the two-stage recess type FET of the present invention. 1 and 2, 1 is a semi-insulating GaAs substrate,
2 is an n-GaAs active layer, 3 is a dummy gate made of SiN, 4 is a SiO film, 44 is a sidewall of the SiO film 4 left on the side surface of the dummy gate 3, and 5 and 55 are resists,
Reference numeral 6 is a first recess groove formed by the first etching, 7 is a second recess groove formed by the second etching, 8 is a gate electrode, 9 is a source electrode, and 10 is a drain electrode.

Next, the manufacturing method will be described with reference to FIGS. However, FIGS. 1B to 2E show only the vicinity of the gate.

First, the n-GaAs active layer 2 is provided on the semi-insulating GaAs substrate 1 by ion implantation and annealing or epitaxial growth by the MBE method. afterwards,
Source and drain electrodes 9 and 10 are formed by ordinary photoengraving using a resist and vapor deposition lift-off (FIG. 1).
(A)). Next, a SiN film is formed by the plasma CVD method, and the dummy gate 3 is formed by photoengraving and plasma etching (FIG. 1B). Then, after the SiO film 4 is formed again on the entire surface by the plasma CVD method (see FIG.
(C)) Using an ECR etcher with strong anisotropy, etching is performed so that the side wall 44 made of the SiO film 4 is left on the side surface of the dummy gate 3 (FIG. 1D). Then, a resist 5 is applied to the entire surface (FIG. 1E), and the dummy gate 3 and its side wall 44 are cued using oxygen plasma (FIG. 2A).

Next, only the side wall 44 of the dummy gate 3 is selectively removed by etching with buffer hydrofluoric acid, and the n-GaAs active layer 2 is further removed with a phosphoric acid-based etchant using the resist 5 and the dummy gate 3 as masks. Etching is performed to a desired depth to form the first recess groove 6 (FIG. 2B). Then, after removing the resist 5, the resist 55 is recoated on the entire surface again, and the dummy gate 3 is cued by oxygen plasma or the like, and then the dummy gate 3 is removed by plasma etching (FIG. 2).
(C)). Next, using the remaining resist 55 as a mask, the n-GaAs active layer 2 is again removed by etching to a desired depth to form a second recess groove 7 (FIG. 2 (d)). Further, a metal structure and a lift-off process complete a gate structure having a two-step recess structure (FIG. 2E).

Although the SiO film 4 is used on the side wall 44 of the dummy gate 3 in the above-described embodiment, it is not shown in FIGS.
After the dummy gate 3 is formed as shown in FIG. 3C, the resist 5 is applied and the dummy gate 3 is cueed (see FIG. 3).
(A)), the resist is removed only on both sides of the dummy gate 3 by photolithography using the mask 11 (FIG. 3 (b)), and the dummy gate 3 and the resist 5 are used as masks for n-
The GaAs active layer 2 is etched to a desired depth (see FIG. 3).
(C)) and subsequent steps can be manufactured in the same manner as the steps of FIGS. 2 (c) to 2 (e).

In the above embodiment, the FET using GaAs as the active layer has been described, but InP and InGaAs are used.
Other semiconductor materials such as InP / InGaAs, I
nAlAs / InGaAs, AlGaAs / InGaA
The same effect can be obtained in an FET having a heterojunction such as s.

[0017]

As described above, according to the present invention,
A step of forming a dummy gate at a gate forming position on the semiconductor active layer, etching the semiconductor active layer on both sides of the dummy gate to form a first recess groove, and covering a region other than the dummy gate with a resist After that, the dummy gate is removed, and thereafter the semiconductor active layer in the removed portion is etched deeper than the first recess groove to form the second recess groove, so that the recesses of the first and second steps are formed. They can be formed independently of each other, which has the effect of realizing a two-step recess type gate structure with good controllability.

Further, since the sidewalls formed on both sides of the dummy gate are used for forming the first recess groove, a highly accurate recess can be obtained.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a two-stage recess type FET according to the present invention.

FIG. 2 is a cross-sectional view showing a step that follows FIG.

FIG. 3 is a process sectional view showing another embodiment of the method for manufacturing a two-step recess type FET according to the present invention.

FIG. 4 is a process cross-sectional view showing a method of manufacturing a conventional two-step recess type FET.

FIG. 5 is a cross-sectional view showing a two-stage recess type FET manufactured by a conventional manufacturing method.

[Explanation of symbols]

 1 semi-insulating GaAs substrate 2 n-GaAs active layer 3 dummy gate 4 SiO film 5 resist 6 first recess groove 7 second recess groove 8 gate electrode 9 source electrode 10 drain electrode 11 mask 44 formed on the side surface of the dummy gate Side wall of the formed SiO film 55 Resist

Claims (2)

[Claims] 1. A method of manufacturing an FET having a two-step recess structure on a semiconductor active layer, wherein a dummy gate is formed at a gate formation position on the semiconductor active layer, and the semiconductor active layer is provided on both sides of the dummy gate. A step of etching to form a first recess groove, and a region other than the dummy gate is covered with a resist, the dummy gate is removed, and then the semiconductor active layer in the removed portion is removed from the first recess. A method of manufacturing a two-step recess type FET, comprising the step of forming a second recess groove by etching deeper than the groove. 2. The step of forming a first recess groove comprises forming a dummy gate, forming sidewalls on both sides of the dummy gate, and then covering the area other than the dummy gate and the sidewall with a resist, and then forming the dummy gate. 2. The method of manufacturing a two-step recess type FET according to claim 1, which is a step of forming a first recess groove on the semiconductor active layer by etching after removing only the side wall.