JPH04274332A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a parasitic capacity between a T-type gate electrode and an activation layer to be reduced by performing side etching of a first spacer layer wider than a gate electrode upper width, forming a T-type gate within a gate recess, and then performing dry etching of the spacer layer. CONSTITUTION:A two-layer spacer where a second spacer layer 7 has a lower etching rate than a first spacer layer 6 is used, a gate recess 11 is formed, and then the first spacer layer 6 is subjected to dry etching so that an opening W4 which is wider than a gate electrode upper width W3 can be achieved. A gate electrode metal 5' is deposited and lifted off, a T-type electrode 5 is formed within the gate recess 11, and further the exposed first and second spacer layers 6 and 7 are eliminated by dry etching, thus enabling a spacing which is equal to a film thickness of the first spacer layer 6 to be secured between the T-type gate electrode 5 and an activation layer 2 after completion of FET.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular, a field effect transistor (Field effect transistor) formed on a semi-insulating gallium arsenide (GaAs) semiconductor substrate.
eld Effect Transistor; F
ET), high electron mobility transistor (High ELE)
ctron Mobility Transistor
The present invention relates to a method of forming a gate electrode of a device such as HEMT in a self-aligned manner.

0002

2. Description of the Related Art Generally, in order to improve the performance of high frequency field effect transistors, it is required to shorten the gate length (Lg) and reduce the gate resistance (Rg). For this reason, a so-called T-shaped gate structure is adopted in which the width of the gate electrode is narrower on the lower side and wider on the upper side. Furthermore, due to the requirement for high breakdown voltage, a structure that also employs a gate recess structure is required, making its manufacture extremely difficult.

A conventional method for forming a T-shaped gate within a gate recess will be described below. Figure 7 (a
) to (f) are Si in the gate recess according to the conventional example.
FIG. 4 is a cross-sectional view of each main process showing a method of forming a T-shaped gate electrode using a spacer layer made of ON, SiN, or the like. In the figure, reference numeral 1 denotes a substrate made of semi-insulating GaAs semiconductor or the like, on which an active layer 2 is formed, and a groove 11 called a gate recess is formed in the center of the substrate. A T-shaped gate electrode 5 is provided. Source electrodes 3 are placed on the active layer 2 on both sides of the gate electrode 5.
, a drain electrode 4 are provided. Also, 6,6',
10 and 10' are spacer layers made of SiN or SiO, and 8 and 9 are resists.

[0004] Next, the manufacturing process according to the conventional method will be explained. First, a substrate 1 made of a semi-insulating GaAs semiconductor substrate
An n-type active layer 2 is formed on the main surface by ion implantation or epitaxial growth, and a source electrode 3 and a drain electrode 4 are formed on this. After that, a spacer layer 6 made of SiN or SiON is formed on the entire surface of the wafer, and a resist pattern 8 for forming a gate recess is provided.
Using this as a mask, the spacer layer 6 is etched away (FIG. 7(a)).

Next, the active layer 2 is etched using the opened spacer layer 6 as a mask to form a gate recess 11 in the active layer 2 (FIG. 7(b)).

Thereafter, after removing the resist pattern 8, a spacer layer 10 of SiN or SiON is formed so as to fill the gate recess 11 (FIG. 7(c)).

When the spacer layer 10 is removed by its thickness by dry etching, the remaining portions 10' of the spacer layer 10 remain at the stepped portions of the source electrode 3 and drain electrode 4 and at both corners of the gate recess 11 (FIG. 7(d)). ) ).

Thereafter, a resist pattern 9 for forming a gate electrode is formed, and a gate electrode metal 5 is deposited over the entire surface by vapor deposition.
' (Figure 7(e)).

Then, unnecessary gate electrode metal 5' and resist 9 are removed by lift-off method, and dry etching is performed to remove unnecessary spacer layer 6 exposed on the surface.
, 10' are removed to obtain the T-shaped gate electrode 5, completing the FET structure (FIG. 7(f)).

0010

[Problem to be solved by the invention] However, conventionally,
Since the T-shaped gate was formed in the gate recess by the method described above, the remaining spacer layers 6' and 10' of the spacer layers 6 and 10 remained in the gate recess 11 even after the T-shaped gate 5 was formed. SiN or SiO remains between the gate electrode 5 and the active layer 2 and fills the space between the gate electrode 5 and the active layer 2.
The parasitic capacitance due to the dielectric films 6' and 10' of N etc. increases,
There is a problem in that the high frequency characteristics of the FET etc. are impaired, thereby reducing the effect of reducing the gate length.

Furthermore, if the alignment of the resist pattern 9 for forming a gate electrode is misaligned with the gate recess 11, the gate electrode 5 and the GaA
s Dielectric film 6' such as SiN or SiON between the active layers 2
, 10' further increases the parasitic capacitance.

The present invention was made in view of the above-mentioned problems, and it is possible to reduce the parasitic capacitance between the T-shaped gate electrode and the active layer in a device having a T-shaped gate electrode in the gate recess, and shorten the gate length. An object of the present invention is to provide a method for manufacturing a semiconductor device that can effectively reduce gate resistance.

[0013]

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a step of forming a source electrode and a drain electrode on a base substrate on which an active layer is formed, and a step of forming a first spacer layer on the entire surface of the wafer. At the same time, a step of forming a second spacer layer with a small etching rate using the first spacer layer thereon, a step of forming a first resist pattern for opening the first and second spacer layers, and a step of forming a first resist pattern for forming holes in the first and second spacer layers. A step of etching the first and second spacer layers at the same etching speed using the resist pattern as a mask, and after removing the first resist pattern, a second resist for forming a gate electrode having an opening width wider than that of the first resist pattern. forming a pattern; etching the active layer using the opened first and second spacer layers as masks to form a gate recess; etching the first spacer layer to adjust the opening width to the second resist pattern; a process of widening the opening beyond the width of the opening, a process of vapor depositing a metal for forming a gate electrode on the entire surface and removing unnecessary metal for forming a gate electrode by lift-off, and a process of removing the first and second spacer layers around the gate electrode by etching. The method is characterized in that it has a step of completing the gate electrode.

The method for manufacturing a semiconductor device according to the present invention includes:
A step of forming a source electrode and a drain electrode on the base substrate on which the active layer is formed, a first spacer layer is formed on the entire surface of the wafer, and a second spacer layer with a small etching rate is formed on top of this by the first spacer layer. forming a first resist pattern for opening the first and second spacer layers; etching the first and second spacer layers at the same etching rate using the first resist pattern as a mask; After removing the first resist pattern,
a step of forming a second resist pattern for forming a gate electrode having an opening width wider than the first resist pattern; a step of partially etching the active layer using the opened first and second spacer layers as a mask; a step of widening the opening width of the first spacer layer by etching; a step of etching the active layer using the opening pattern of the first spacer layer as a mask to form a gate recess; etching the first spacer layer; A process of widening the opening width from that of the second resist pattern, depositing a metal for forming a gate electrode on the entire surface,
The process of removing unnecessary gate electrode forming metal by lift-off, and the process of removing the first and second metals around the gate electrode by etching.
The method is characterized in that it has a step of removing the spacer layer to complete the gate electrode.

[0015]

[Operation] According to the method of manufacturing a semiconductor device of the present invention, two spacer layers consisting of the first and second spacer layers having different etching rates are used, and after forming the gate recess, the first spacer layer is attached to the upper part of the gate electrode. A T-shaped gate is formed in the gate recess by side etching wider than the width, gate electrode metal deposition and lift-off, and the spacer layer is removed by dry etching, so there is always a gap between the T-shaped gate and the active layer in the recessed structure. A space corresponding to the thickness of the first spacer layer is secured, and the gate length and gate resistance can be shortened while suppressing an increase in parasitic capacitance between the T-type gate and the active layer.

Further, according to the method of manufacturing a semiconductor device of the present invention, part of the active layer is etched using the first spacer layer with holes as a mask, and the first spacer layer is widened by etching to form an opening pattern. The active layer is etched using a mask to form a gate recess, and then the first
Since we added a step to widen the spacer layer from the resist pattern for gate electrode formation by etching, a gap equal to the thickness of the first spacer layer is always secured between the T-shaped gate and the active layer in the recessed structure, and the T-shaped gate In addition to suppressing the increase in parasitic capacitance between the active layer and the active layer, shortening the gate length and reducing gate resistance, the recess structure can be controlled in multiple stages using the first spacer layer, and the gate-source resistance (Rs
) and increase the withstand voltage.

[0017]

[Example] Figures 1(a) to (d) and 2(a) to
(c) is a sectional view of each main process showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

In the figure, reference numeral 1 denotes a semiconductor substrate as a base substrate, and in order to fabricate a high frequency semiconductor device, a semi-insulating I film made of, for example, semi-insulating GaAs, semi-insulating InP, etc. is used.
Preferably, a II-V compound semiconductor substrate is used. A semiconductor layer called an active layer 2 is provided on one main surface of the substrate 1 by an epitaxial growth method or an ion implantation method.
An opening 11 called a recess is formed that does not reach the bottom of the hole. Further, a T-shaped gate electrode 5 is formed in this opening 11, thereby forming a 1T-shaped gate recess structure. Further, a source electrode 3 and a drain electrode 4 are provided on the active layer 2 located on both sides of the T-shaped gate electrode 5. 6 and 7 are first and second spacer layers both made of SiN or SiON, and the second spacer layer 7
is formed of SiN, SiON, or the like, which has a lower etching rate than the first spacer layer 6. 8 is a first resist pattern for forming openings in the first and second spacer layers 6 and 7, and 9 is a second resist pattern having openings wider than the first resist pattern. It's a pattern.

Next, a method for manufacturing a semiconductor device according to this embodiment will be explained. First, an active layer 2 is formed on one main surface of a semiconductor substrate 1 such as a semi-insulating GaAs substrate. This active layer 2
As a method for forming the substrate 1, there are two methods: crystal growth of an n-type GaAs layer using an epitaxial growth method such as molecular beam epitaxy, or a method of introducing an n-type impurity into the substrate 1 using an ion implantation method and annealing. The thickness of this active layer 2 is preferably about 0.4 to 0.5 μm for FET.

After forming the active layer 2, an ohmic source electrode 3 and a drain electrode 4 made of, for example, AuGe/Ni/Au are formed on the active layer 2, and a first electrode made of SiN or SiON is formed on the entire surface of the wafer. The etching rate S is smaller than that of the spacer layer 6 and the first spacer layer 6.
A second spacer layer 7 made of iN or SiON is sequentially formed. The first and second spacer layers 6 and 7 are formed using silane gas (SiH4) and ammonia gas (NH4).
) is preferably used. The first and second spacer layers 6 and 7 having different etching rates are C
It can be easily formed by changing the mixing ratio of silane gas and ammonia gas in the VD method. For example, the first spacer layer 6 is formed at a mixing ratio of silane gas and ammonia gas of 1:2, and the second spacer layer 7 is formed at a mixing ratio of silane gas and ammonia gas of 4:1.
By doing so, the SiN film with an etching rate of 3000 angstroms/min is used as the first spacer layer 6, and the SiN film with an etching rate of 3000 angstroms/min is used as the second spacer layer 7.
A SiN film of 0 angstrom/min can be formed. The thickness of the first spacer layer 6 is about 500 angstroms, and the thickness of the second spacer layer is about 500 to 1500 angstroms (FIG. 1(a)).

Thereafter, a resist is applied to the entire surface, and openings are formed in the resist by ordinary photolithography to obtain a first resist pattern 8. The opening width a of this first resist pattern corresponds to the width of the junction surface (so-called gate length) of the gate electrode of the FET with the active layer 2 after manufacturing is completed, and is important for the electrical characteristics of the FET, especially the high frequency characteristics. extremely important.

Then, using this first resist pattern 8 as a mask, the first and second spacer layers 6 and 7 exposed in the openings are etched away using an etching method capable of etching at the same etching rate, Openings having an opening width a are formed in both the first and second spacer layers 6 and 7. This etching includes dry etching, such as RI.
It is preferable to use the E method (Figure 1(b)).

Thereafter, the first resist pattern 8 is removed, a resist is applied again to the entire surface of the wafer, and openings are formed in the resist by ordinary photolithography to form a second resist pattern for forming gate electrodes. Get 9. The opening width W3 of this second resist pattern 9 corresponds to the width of the upper part of the gate electrode of the FET after manufacturing is completed (FIG. 1(c)).

Next, a gate recess 11 having a depth of about 0.35 μm and a width W1, which does not reach the substrate 1, is formed in the active layer by etching using the opening pattern of the first spacer layer 6 as a mask. For etching this active layer, wet etching using a tartaric acid-based or phosphoric acid-based etchant is preferable. For example, if the plane orientation of the active layer 2 is (1
00), by using this etching method, a forward mesa-shaped recess with the (0/1/1) plane exposed is formed on the sidewall as shown in the figure.

Thereafter, only the first spacer 6 is selectively etched by wet etching using a hydrofluoric acid-based etchant, so that the opening width W4 thereof is larger than the opening width W3 of the resist pattern 9 for forming the gate electrode. Side etching is performed so that (W4 > W3 > W1) (FIG. 1(d)).

After that, a metal material is used to form a Schottky barrier gate electrode on the entire surface, for example, the substrate is made of GaA.
s, a multilayer metal material 5' containing aluminum, such as Ti/Mo/Al, is deposited (Fig. 2
(a) ). After that, unnecessary gate electrode metal 5' is removed by lift-off method.
and remove the second resist pattern 9 (FIG. 2(b)
).

Thereafter, the first and second spacer layers 6 and 7 exposed on the surface are removed by dry etching, such as plasma etching, to obtain the T-shaped gate electrode 5 having a recessed structure. Complete the FET (Figure 2(c)
) ). At this time, the remainder 7' of the second spacer layer may remain in the portion of the T-shaped gate electrode facing the active layer 2.

According to this embodiment, two spacer layers are used, the second spacer layer 7 having a lower etching rate than the first spacer layer 6, and the gate recess 11
After formation, the first spacer layer 6 has a gate electrode upper width W3.
Side etching is performed to have a wider opening W4, gate electrode metal 5' is deposited and lifted off, a T-shaped gate electrode 5 is formed in the gate recess 11, and the exposed first and second Since the spacer layers 6 and 7 are removed by dry etching, the T
A gap equal to the thickness of the first spacer layer 6 can always be maintained between the T-type gate electrode 5 and the active layer 2, thereby reducing the parasitic capacitance between the T-type gate electrode 5 and the active layer 2. It is possible to effectively shorten the gate length, reduce gate resistance, and increase the withstand voltage, and it is possible to obtain a product with excellent high frequency characteristics.

[0029] Also, FIGS. 3(a) to (d) and FIG. 4(
a) to (c) are cross-sectional views of each main process showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. In the figures, the same reference numerals as those in FIGS. 1 and 2 according to the above embodiment indicate the same or corresponding parts, and the explanation thereof will be omitted.

Next, the manufacturing process according to the second embodiment will be explained by referring to FIGS. 1(a) to (c), FIGS. 3(a) to (d), and FIG. 4(a) used in the above embodiment. ~(c) Perform using.

1A to 1C, a source electrode 3 and a drain electrode are formed on an active layer 2 of a substrate 1 made of semi-insulating GaAs or the like in the same process as described in the first embodiment. A first spacer layer 6 made of SiN or SiON or the like is formed on the entire surface of the wafer, and a second spacer 7 having an etching rate smaller than the etching rate of the first spacer layer 6 is formed above the first spacer layer 6 (FIG. 1). (a) ),
Thereafter, using the first resist pattern having the opening width a as a mask, the first and second spacer layers 6 and 7 are etched away using an etching means capable of etching at the same etching speed (FIG. 1(b)). Thereafter, after removing the first resist pattern 8, a resist is applied to the entire surface of the wafer, and a second resist pattern for forming a gate electrode having an opening width W3 wider than the opening width a of the first resist pattern is formed. 9 (FIG. 1(c)).

Thereafter, in the second embodiment, a gate recess 1 having a depth not reaching the substrate 1 is formed in the active layer 2 by etching using the opening pattern of the first spacer layer 6 as a mask.
1 (Fig. 3(a)). It is preferable to use a wet etching method using a tartaric acid-based or phosphoric acid-based etchant for this etching. For example, when the plane orientation of the active layer 2 is (100), by using this etching method, the on its side wall as shown in (
0 /1 /1) Mesa-shaped recess 11a with exposed surface
is formed.

Further, by wet etching using a hydrofluoric acid etchant, the opening width of the first spacer layer 6 is widened by side etching using the second spacer layer 7 as a mask (FIG. 3(b)).

[0034] Then, the first spacer layer 6 with the openings
Using this as a mask, wet etching is performed again using a tartaric acid-based or phosphoric acid-based etchant until the remaining thickness of the active layer 2 reaches a predetermined thickness (preferably 1500 angstroms to 2000 angstroms). The step gate recess 11 is completed (FIG. 3(c)).

Further, only the first spacer layer 6 is selectively etched by wet etching using a hydrofluoric acid-based etching solution, and the opening width W4 is the same as that of the second resist pattern 9 for forming the gate electrode. Side etching is performed so that the hole width is larger than W3 (FIG. 3(d)).

After that, a metal material is used to form a Schottky barrier gate electrode on the entire surface, for example, the substrate is made of GaA.
s, a gate electrode metal 5' made of a multilayer metal containing aluminum such as Ti/Mo/Al is vapor-deposited (FIG. 4(a)), and unnecessary gate electrode metal 5' is removed by a lift-off method. and second resist pattern 9
(Figure 4(b)).

Thereafter, the first and second spacer layers 6 and 7 exposed on the surface are removed by dry etching to form T.
FE with a two-stage recessed T-type gate structure was obtained.
Complete T (Figure 4(c)).

According to the second embodiment, as in the first embodiment, the first and second embodiments have different etching rates.
Using the second spacer layers 6 and 7, only the first spacer layer 6 is selectively side-etched to make the opening width W4 larger than the opening width W3 of the second resist pattern for forming the gate electrode. After forming the T-shaped gate electrode 5, a T-shaped gate electrode is formed by a vapor deposition/lift-off method, so that a constant distance equal to the thickness of the first spacer layer 6 is always maintained between the T-shaped gate electrode 5 and the active layer 2. Therefore, it is possible to prevent the generation of parasitic capacitance between the gate electrode 5 and the active layer 2 due to the dielectric film.

Furthermore, the manufacturing method of the second embodiment is the same as the manufacturing method of the first embodiment, except that the active layer 2 is etched using the opened first and second spacer layers 6 and 7 as masks. After that, the first spacer layer is expanded by wet etching, and the active layer 2 is etched using the opening pattern 6 of this first spacer layer as a mask to complete the gate recess 11. Since we added a step to wet-etch the layer 6 to make it wider than the opening width of the second resist pattern 9 for forming the gate electrode, its inner wall has a two-stage recess structure, and the T-shaped gate electrode is in the bottom row. It is possible to obtain one formed on a recess. As a result, the manufacturing method of this embodiment can effectively increase the withstand voltage of the element compared to the FET structure having the one-stage recessed T-type gate of the first embodiment, by adding an extremely simple manufacturing process, and This has the effect of making it possible to obtain a high-performance field-effect transistor structure in this area.

In the above embodiments, the above manufacturing method was used to obtain a structure in which a T-shaped gate electrode was formed in one or two stages of recesses, but the present invention applies to these two embodiments. The process is not limited to, but includes, but is not limited to, a step of partially etching the active layer using the first spacer layer 6 as a mask before forming the T-shaped gate electrode 5 (FIG. 3(a)), a step of etching the first spacer layer 6 a step of widening the opening width by side etching (FIG. 3(b)), and a step of further etching the active layer using the first spacer layer 6 with the widened opening width as a mask (
It also includes a manufacturing method for obtaining a high breakdown voltage, high output FET structure in which a T-shaped gate electrode is formed within a recessed structure whose inner wall has multiple stages by repeating the steps in FIG. 3(d)) several times.

Furthermore, in the above embodiments, the method for manufacturing a GaAs field effect transistor was explained as an example, but the present invention
It is not limited to the production of aAs field effect transistors, for example, high electron mobility transistors (HE
The present invention can also be applied to manufacturing electrodes for MT) or microwave monolithic ICs (MMIC).

FIG. 5 shows a HEMT structure having a T-shaped gate electrode in a one-stage recess manufactured using the manufacturing method according to the first embodiment, and FIG. 6 shows a HEMT structure manufactured using the manufacturing method according to the second embodiment. In these figures, the same reference numerals as in FIGS. 1 to 4 indicate the same or equivalent parts, and 17 indicates a half. an insulating substrate; 16 is a GaAs buffer layer formed on the substrate 17; 14 is a GaAs buffer layer;
An InGaAs layer formed on the s buffer layer 16, on which an n + -AlGaAs layer 13 is formed,
A two-dimensional electron gas layer 15 is provided within the InGaAs layer 14 at the interface between the InGaAs layer 14 and the n+ -AlGaAs layer 13.
is formed. In addition, 12 is n+ -AlGaAs
An n+ -GaAs layer formed on the layer 13, the n+
A one-stage or two-stage recess 11 is formed in the + -AlGaAs layer 13, and a T-shaped gate electrode 5 is formed in the recess. GaA is sequentially deposited on the semi-insulating substrate 17.
s buffer layer 16, InGaAs layer 14, n+ -Al
After forming the GaAs layer 13 and the n+ -GaAs layer 12, a source electrode 3 and a drain electrode 4 are formed on the n+ -GaAs layer 12, and then the manufacturing according to the first embodiment and the second embodiment, respectively, is performed. By using the method (the explanation thereof is omitted here), the HE of the structure shown in FIGS. 5 and 6 can be obtained.
MT is obtained.

[0043] Also in such HEMT, the above first
Similarly to the effect of the second embodiment, a distance equal to the thickness of the first spacer layer can be secured between the T-type gate electrode 5 and the n + -GaAs layer 12 which is the active layer.
Parasitic capacitance can be prevented between the gate electrode 5 and the active layer 13, and high breakdown voltage and high output of the device can be realized.

Further, in the above embodiment, SiON or SiN is used for both the first spacer layer 6 and the second spacer layer 7, but the materials of the first and second spacer layers may be different from these. The material is not limited, and other materials may be used.

Furthermore, the film thicknesses, manufacturing methods, materials, etc. of the other layers are, of course, not limited to those of the above embodiments, and may be changed as appropriate depending on the application.

Furthermore, in the above embodiment, the GaAs active layer 2
Using a surface with a (100) orientation as a surface, recess etching was performed using a tartaric acid-based or phosphoric acid-based etchant to form a mesa-shaped recess with the (0 /1 /1) surface exposed on the side wall. However, the shape of this recess changes depending on the surface orientation of the active layer and the etchant used, and is not limited to the shape shown in the above embodiment.

[0047]

As described above, according to the present invention, two spacer layers are used, the upper spacer layer having a lower etching rate than the lower spacer layer, and after the gate recess is formed, the lower spacer layer is attached to the top of the gate electrode. The T-shaped gate was formed in the gate recess by side etching wider than the width, depositing and lifting off the gate electrode metal, and then removing the spacer layer by dry etching, so that after the device was completed, the T-shaped gate electrode and active A predetermined distance can always be maintained between the T-type gate electrode and the active layer, thereby preventing parasitic capacitance between the T-type gate electrode and the active layer, effectively shortening the gate length and reducing gate resistance, and improving high frequency characteristics. This has the effect that good results can be obtained with good controllability and reproducibility.

[0048] According to the present invention, the perforated upper layer,
Part of the active layer is etched using the lower spacer layer as a mask, then the lower spacer layer is expanded by wet etching, the active layer is etched using the opening pattern of the lower spacer layer as a mask to form a gate recess, and then the lower spacer layer is etched. We added a step to widen the side spacer layer from the resist pattern for gate electrode formation by wet etching, and controlled the recess structure using the lower spacer film to obtain a multi-stage recess structure. - It is possible to obtain a structure that can achieve high breakdown voltage by suppressing the increase in source-to-source resistance (Rs), and has the effect of providing high performance in a high frequency region with good controllability and reproducibility.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a process cross-sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 4 is a process cross-sectional view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view of a HEMT manufactured by a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view of a HEMT manufactured by a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1　　　　Substrate 2 Active layer 3 Source electrode 4 Drain electrode 5 Gate electrode 6 First spacer layer 7 Second spacer layer 8 First resist pattern 9 Second resist pattern 11 Gate recess 7’ Remaining second spacer layer 12 n+ GaAs layer 13 n+ AlGaAs layer 14 InGaAs layer 15 Two-dimensional electronic layer 16 GaAs buffer layer 17 Semi-insulating substrate

Claims (2)

[Claims] 1. A step of forming a source electrode and a drain electrode on a base substrate on which an active layer is formed, forming a first spacer layer on the entire surface of the wafer, and forming a first spacer layer on the first spacer layer. forming a second spacer layer with a smaller etching rate; forming a first resist pattern for forming holes in the first and second spacer layers; 1,
etching a second spacer layer at the same etching rate; after removing the first resist pattern, forming a second resist pattern for forming a gate electrode having an opening width wider than that of the first resist pattern; forming a gate recess by etching the active layer using the opened first and second spacer layers as a mask;
etching the spacer layer and making the opening width wider than the opening width of the second resist pattern; depositing a gate electrode forming metal on the entire surface; and removing unnecessary gate electrode forming metal by lift-off; A method of manufacturing a semiconductor device, comprising the step of removing the first and second spacer layers around the gate electrode by etching to complete the gate electrode. 2. A step of forming a source electrode and a drain electrode on the base substrate on which the active layer is formed, forming a first spacer layer on the entire surface of the wafer, and forming a first spacer layer on the first spacer layer. forming a second spacer layer with a smaller etching rate; forming a first resist pattern for forming holes in the first and second spacer layers; 1,
etching a second spacer layer at the same etching rate; after removing the first resist pattern, forming a second resist pattern for forming a gate electrode having an opening width wider than that of the first resist pattern; a step of partially etching the active layer using the opened first and second spacer layers as a mask, a step of widening the opening width of the first spacer layer by etching, and opening of the first spacer layer. a step of etching the active layer using the pattern as a mask to form a gate recess; a step of etching the first spacer layer to make the opening wider than the opening width of the second resist pattern; and forming a gate electrode over the entire surface. The method includes the steps of depositing a forming metal, removing unnecessary gate electrode forming metal by lift-off, and removing the first and second spacer layers around the gate electrode by etching to complete the gate electrode. A method for manufacturing a featured semiconductor device.