JP3470023B2 - Method for manufacturing field effect transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a method for manufacturing a field effect transistor for a high speed compound semiconductor IC used in communication equipment, computers and the like.

[0002]

2. Description of the Related Art Conventionally, in a field effect transistor (hereinafter referred to as FET) using a compound semiconductor such as GaAs, the parasitic source / drain resistance between the gate and the source and between the gate and the drain is reduced, and the gate and the source are reduced. In order to increase the breakdown voltage between the gate electrode and the gate and the drain, a two-step recess structure is used in which the active layer in the gate electrode formation portion above the channel layer (n layer) is etched in two steps.

The manufacturing method will be described below with reference to FIG.

First, in the step shown in FIG. 7A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and Si of 5 × are formed on a semi-insulating GaAs substrate 11.
After sequentially epitaxially growing an active layer 13 made of an n-type GaAs layer having a thickness of about 500 nm doped to about 10 ¹⁷ cm ^−3, a source electrode made of AuGe / Ni / Au is formed on the active layer 13 at positions separated from each other. 15 and the drain electrode 16 are formed respectively.

Next, in the step shown in FIG. 7B, after a resist film 41 is formed on the substrate, the resist film 41 is used as a mask to form an H ₃ PO ₄ / H ₂ O ₂ / H ₂ O system. Isotropic etching of the active layer 13 with an etching solution,
An upper recess portion 18 wider than the opening 41a of the first resist film 41 is formed in the active layer 13.

Next, after removing the resist film 41, a part of the bottom surface of the upper recess portion 18 is opened, that is, a second resist film 42 having an opening 42a narrower than the bottom surface of the upper recess portion 18 is formed. Form.

[0007] Next, in the step shown in FIG. 7 (c), using the second resist film 42 as a _{mask, H 3 PO 4 / H 2} O 2
The active layer 13 is isotropically etched with a / H ₂ O-based etching solution to form the lower recess portion 19 in the upper recess portion 18.

Next, in a step shown in FIG. 7D, a gate electrode 20 made of Al is formed on the recess portion 19 in the lower stage.

According to this manufacturing method, the active layer 13 has the thickest film thickness at the contact portions immediately below the source electrode 15 and the drain electrode 16, and the second thickest film at the bottom portion of the upper recess 18 and the gate electrode 20. Immediately below, that is, the lower recess 1
Since the thinnest film is formed at the bottom of 9, the parasitic source-drain resistance between the gate and the source and between the gate and the drain is reduced, and the gate-source and the gate
The breakdown voltage between the drains can be increased.

However, in this manufacturing method, two photolithography steps are required to form the two-step recess structure, and the number of steps is large, resulting in high manufacturing cost. Further, since the position of the lower recess portion 19 in the upper recess portion 18 is determined by the alignment of the photolithography, the distance between the gate and the source and the distance between the gate and the drain are varied and formed. There is a problem that the gate breakdown voltage and transconductance of the FET are low in the in-plane uniformity and reproducibility of the wafer.

Therefore, the following manufacturing method is used as a method of forming a two-step recess structure without alignment by photolithography with a small number of steps. (Reference Jpn. J. Appl. Phys., Vol. 31 (1
992) pp. 2374-2381) Hereinafter, a manufacturing method thereof will be described with reference to FIGS.

First, in a step shown in FIG. 8A, a buffer layer 12 made of an undoped GaAs layer and an S of about 1.2 × 10 ¹⁷ cm ⁻³ are formed on a semi-insulating GaAs substrate 11.
i-doped n-type GaAs layer having a thickness of 600 nm
After sequentially epitaxially growing the active layer 13 of
An insulating film 21 made of an iN film is deposited, and then the active layer 1 is formed.
3, the source electrode 15 and the drain electrode 16 are formed at positions separated from each other.

Next, in the step shown in FIG. 8B, the opening 51a is formed in the region where the gate electrode is to be formed on the substrate.
Forming a resist film 51 having
After the insulating film 21 is dry-etched using the mask as a mask to form the opening 21a of the insulating film 21, the resist film 5 is formed.
Using the insulating film 1 and the insulating film 21 as a mask, the active layer 13 is isotropically etched to form a recess 19 in the lower stage.

Next, in the step shown in FIG. 8C, the insulating film 21 is wet-etched (side-etched) by using the resist film 51 as a mask to open the opening 2 of the insulating film 21.
1a is expanded laterally.

Next, in the step shown in FIG. 8D, the active layer 13 is isotropically etched using the resist film 51 and the insulating film 21 as a mask. At this time, the lower recess portion 19 is enlarged and spreads laterally and downward, and the region immediately below the insulating film 21 is largely enlarged laterally and the lower recess portion 1 is expanded.
The upper recess portion 18 having the upper surface of 9 as the bottom surface is formed.

Next, in the step shown in FIG. 8E, the gate electrode 2 made of Ti / Mo is formed on the bottom surface of the recess 19 in the lower stage.
Form 0.

According to this manufacturing method, since only one photolithography step is used in the recess step, a two-step recess structure can be formed with a small number of steps without alignment of photolithography.

[0018]

However, in the manufacturing method described in the above document, when the second isotropic etching of the active layer 13 is performed, not only the lower recess portion 19 formed first is formed not only in the lower portion. Since it is expanded to the side,
Only the lower recess portion 19 having a width larger than the width of the opening 51a of the resist film 51 can be formed.
That is, the width of the recess 19 in the lower stage is defined by the resolution of photolithography, and the opening 51 of the resist film 51 is defined.
It becomes considerably larger than the minimum size of a. Also,
Since the size and shape of each recess are determined by the total of two isotropic etchings of the active layer 13, there is a problem that the controllability of the size and shape is poor.

The present invention has been made in view of the above problems, and an object thereof is to provide a means for forming a two-step recess structure with good uniformity and controllability in the recess process by using as few photolithography processes as possible. Accordingly, it is an object of the present invention to provide an FET manufacturing method capable of forming an FET having a low parasitic source / drain resistance and a high gate breakdown voltage at low cost.

[0020]

The manufacturing method of the first field effect transistor SUMMARY OF THE INVENTION The present invention includes a first step of forming an insulating film on a semiconductor region on a base plate, on said insulating film, A second step of forming a first resist film having an opening in a gate electrode formation region, and a step of forming an opening of the insulating film by etching the insulating film using the first resist film as a mask 3, the fourth step of forming a second resist film having an opening overlapping with the opening of the insulating film on the substrate after removing the first resist film, and the insulating step. Isotropic etching of the semiconductor region is performed using the film and the second resist film as a mask, and the semiconductor region has an upper region wider than the overlapping region of the opening of the second resist film and the opening of the insulating film. Forming the recess part of A fifth step, a sixth step of removing the second resist film, and anisotropic etching of the semiconductor region using the insulating film as a mask to form a lower layer below the opening of the insulating film. And a seventh step of forming a recess portion.

By this method, by performing recess etching twice in one photolithography process,
Since the two-step recess structure including the upper recess section and the lower recess section is formed, the same effect as that of the first aspect can be obtained. In addition, since the upper recess portion offset to the source side or the drain side is formed, the recess portion having a large recess width and depth is formed on the source side or the drain side. That is, since the source side and the drain side have a structure in which the gate withstand voltage can be controlled independently, when the source side and the drain side have different gate withstand voltages, the source side gate withstand voltage and the drain side according to the request are required. It is possible to adjust the gate breakdown voltage.

[0022] Between the upper Symbol sixth step and the seventh step, expanding the insulating film by performing the isotropic etching of the semiconductor region as a mask, the recess portion of the upper downward and laterally from particular keep, since the recessed portion is larger recess width and depth at the source side or the drain side et is formed, the action of the above can be obtained more remarkably. .

The method for producing the second field effect transistor of the present invention includes a first step of forming an insulating film on a semiconductor region on a base plate, on said insulating film, an opening in the gate electrode formation region A second step of forming a first resist film having a portion, a third step of etching the insulating film using the first resist film as a mask to form an opening of the insulating film, and at least the above. Isotropic etching of the semiconductor region is performed using the insulating film as a mask to form a fourth recess in the semiconductor region, which is wider than the opening of the insulating film, and the first resist film is formed. After removing
A fifth step of forming on the substrate a second resist film having an opening overlapping the opening of the insulating film, and isotropic formation of the semiconductor region using the insulating film and the second resist film as a mask. Performing a positive etching to expand a part of the upper recess so as to be wider than the overlapping region of the opening of the second resist film and the opening of the insulating film, and A seventh step of removing the second resist film and anisotropic etching of the semiconductor region using the insulating film as a mask to form a lower layer in a region below the opening of the insulating film in the semiconductor region. An eighth step of forming a recess portion.

By this method, by performing recess etching twice in one photolithography step,
Since the two-step recess structure including the upper recess section and the lower recess section is formed, the same operation as that of the first semiconductor device can be obtained. In addition, since the upper recess portion is enlarged by side etching so as to be offset to the source side or the drain side, the recess portion having a large recess width and depth is formed on the source side or the drain side. That is,
Since the source and drain side gate breakdown voltages can be controlled independently, if the source and drain sides require different gate breakdown voltages, the source and drain side gate breakdown voltages will meet the requirements. It becomes possible to adjust with.

The upper SL as the drain-side edge of the opening of the insulating film is included in the opening of the second resist film, opening and overlap of the second resist film opening and the insulating film from particular and are then, recesses recess width and depth larger in the drain side is formed. Therefore, an FET having a structure in which the gate breakdown voltage on the source side and the drain side can be controlled independently and, in general, a gate breakdown voltage on the drain side which is often required to be higher than that on the source side is formed.

Manufacture of the third field effect transistor of the present invention
The manufacturing method is such that on the semiconductor region including the GaAs layer on the substrate.
A resist film having an opening in the gate electrode formation region.
First step of forming and using the resist film as a mask
Isotropic etching of the GaAs layer was performed to
In the body region, the upper resist that is wider than the opening of the resist film
Second step of forming a mask portion and the resist film as a mask
As an anisotropic etching of the GaAs layer,
The region below the opening of the resist film in the semiconductor region
And a third step of forming a lower recess portion in the region,
The anisotropic etching of the GaAs layer is performed with SiCl4 and N
Dry etching performed using a mixed gas of 2
Ri, perform the above anisotropic etching and isotropic etching using a common plasma dry etching device, while performing the plasma etching by applying a high frequency power when performing the isotropic etching, the anisotropic When performing etching, plasma etching is performed by applying high frequency power to the electrode on which the substrate is installed, while stopping high frequency power when performing the above isotropic etching, and is anisotropic from the above isotropic etching. A gas containing a common gas is used for the reactive etching.

According to this method, it is possible to continuously perform isotropic etching and anisotropic etching by changing the etching conditions using the same etching apparatus.
Moreover, since the etching conditions can be changed only by changing a part of the etching gas and controlling ON / OFF of the high frequency power, complicated operation is not required and can be executed by simple control.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) Hereinafter, a first embodiment of the present invention will be described. Figure 1
(A)-(d) is sectional drawing which shows the structure in the manufacturing process of FET by 1st Embodiment.

First, in the step shown in FIG. 1A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and 5 × 10 5 are formed on a semi-insulating GaAs substrate 11.
¹⁷ cm ⁻³ Si-doped thickness of 100 n
A first active layer 13a composed of an n-type GaAs layer of about m
And an etching stop layer 14 made of an AlGaAs layer having a thickness of about 10 to ²⁰ nm, and an n-type Ga having a thickness of about 400 nm doped with Si of about 5 × 10 ¹⁷ cm ^−3.
After the second active layer 13b made of As layer is sequentially epitaxially grown, the source electrode 15 and the drain electrode 16 made of AuGe / Ni / Au film are formed on the second active layer 13b at positions separated from each other. To do.

Next, in the step shown in FIG. 1B, the opening 17a is formed on the substrate in the region where the gate electrode is to be formed.
After forming the resist film 17 having
Using the as a mask, the second active layer 13b is isotropically etched to form the upper recess portion 18 wider than the opening 17a of the resist film 17. At this time, although illustration of a plasma device used for etching is omitted, an inductively coupled dry etching device (hereinafter referred to as ICP) is used to introduce a SiCl ₄ / SF ₆ mixed gas into the reaction chamber and apply high frequency power to the substrate electrode. Isotropic etching is performed under the condition not to do so.

Next, in the step shown in FIG. 1C, the second active layer 13b is anisotropically etched by using the resist film 17 as a mask to open the resist film 17 in the upper recess portion 18. A lower recess portion 19 having a width substantially equal to the width of the portion 17a is formed. At this time, the same ICP was used as the plasma device, and SiCl ₄ / SF ₆ /
Anisotropic etching is performed under the condition that a N ₂ mixed gas is introduced and high frequency power is applied to the substrate electrode.

Next, in the step shown in FIG. 1D, a gate electrode 20 made of Al is formed on the bottom surface of the recess 19 in the lower stage.

According to the method of manufacturing the FET of this embodiment,
The resist film 17 used in the first etching (isotropic etching) for forming the upper recess portion 18 is used as it is, and the second etching (anisotropic etching) is performed.
Since the lower recess portion 19 is formed by performing the above process, the position of the lower recess portion 19 in the upper recess portion 18 is determined in a self-aligned manner. Moreover, since anisotropic etching is performed in the second etching step, the dimensions of the upper recess portion 18 formed first hardly change, and the controllability of the overall shape and width of the recess portion is good. Further, since the width of the recess portion 19 in the lower stage is almost equal to the width of the resist film 17, a fine structure can be realized. Therefore, an FET having a low parasitic source / drain resistance and a high gate breakdown voltage can be manufactured with good uniformity and reproducibility while reducing the number of photolithography steps.

Further, in the manufacturing process of the present embodiment, the first etching and the second etching are anisotropic from isotropic etching only by changing the etching conditions while using the same etching apparatus (plasma apparatus). It becomes easy to switch to the positive etching. That is,
In the step shown in FIG. 1B, SiCl ₄ / S is placed in the reaction chamber.
When the GaAs layer is etched under the condition that the F ₆ mixed gas is introduced and the high frequency power is not applied to the substrate electrode, strong isotropic etching occurs. Therefore, the opening 17a of the resist film 17 is formed in the second active layer 13b. The upper recessed portion 18 having a width wider than the width is formed. Further, in the step shown in FIG. 1C, when the SiCl ₄ / SF ₆ / N ₂ mixed gas is introduced into the reaction chamber and the GaAs layer is etched under the condition that high frequency power is applied to the substrate electrode, it is very different. It is possible to form the lower recessed portion 19 having a strong directionality and a width substantially equal to the width of the opening 17a of the resist film 17.
Moreover, during that time, the shape of the upper recess portion 18 hardly changes.

In addition, by providing an AlGaAs layer (etching stop layer 14) in the semiconductor region and utilizing the fact that the AlGaAs layer is etched little by this etching gas, the depth at the position of the etching stop layer 14 is increased. It is possible to form the lower recess portion 19 having a prescribed dimensional accuracy. Since the depth of the lower recess portion 19 is accurately controlled, the thickness of the first active layer 13a serving as the channel region below the lower recess portion 19 becomes substantially constant, and the characteristics such as the threshold value. Thus, an FET with a small variation of is formed.

(Second Embodiment) Next, a second embodiment of the present invention will be described. Figure 2
(A)-(e) is sectional drawing which shows the structure in the manufacturing process of FET by 2nd Embodiment.

First, in the step shown in FIG. 2A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and 5 × 10 5 are formed on a semi-insulating GaAs substrate 11.
¹⁷ cm ⁻³ Si-doped thickness of 100 n
A first active layer 13a composed of an n-type GaAs layer of about m
And an etching stop layer 14 made of an AlGaAs layer having a thickness of about 10 to ²⁰ nm, and an n-type Ga having a thickness of about 400 nm doped with Si of about 5 × 10 ¹⁷ cm ^−3.
A second active layer 13b made of an As layer is sequentially epitaxially grown. Then, on the substrate, the thickness is 100n.
An insulating film 21 made of a SiO ₂ film having a thickness of about m is formed, and AuGe / Ni / Au is formed in a connection hole penetrating the insulating film 21.
The source electrode 15 and the drain electrode 16 made of a film are formed.

Next, in the step shown in FIG. 2B, the opening 23a is formed in the region where the gate electrode is to be formed on the substrate.
After forming the resist film 23 having
Is used as a mask to perform wet etching (side etching) of the insulating film 21 using hydrofluoric acid,
The opening 21 that is wider than the opening 23a of the resist film 23
a is formed.

Next, in the step shown in FIG. 2C, the second active layer 13 is formed using the resist film 23 and the insulating film 21 as a mask.
b isotropic etching is performed to open the opening 2 of the insulating film 21.
An upper recess portion 18 wider than 1a is formed. At this time, although illustration of a plasma device used for etching is omitted, isotropic etching is performed under the condition that ICP is used, SiCl ₄ / SF ₆ mixed gas is introduced into the reaction chamber, and high frequency power is not applied to the substrate electrode. .

Next, in the step shown in FIG. 2D, the second active layer 13b is anisotropically etched by using the resist film 23 as a mask to open the opening of the resist film 23 in the recess 18 in the upper stage. The lower recess portion 19 having a width substantially equal to the width of the portion 23a is formed. At this time, the same ICP was used as the plasma device, and SiCl ₄ / SF ₆ /
Anisotropic etching is performed under the condition that a N ₂ mixed gas is introduced and high frequency power is applied to the substrate electrode.

Next, in the step shown in FIG. 2E, the gate electrode 20 made of Al is formed on the bottom surface of the recess 19 in the lower stage.

In this embodiment, as in the first embodiment, the recess etching is performed twice by using the same etching apparatus and different etching conditions in one photolithography process. Since this is formed, the same effect as that of the first embodiment can be exhibited.

Further, as shown in FIGS. 2B and 2C, after forming an opening 21a wider than the opening 23a of the resist film 23 in the insulating film 21 deposited on the substrate, the resist is formed. Using the film 23 and the insulating film 21 as a mask, a highly isotropic dry etching is performed to form the upper recess portion 18
Since the recess is formed, the recess width of the recess 18 in the upper stage can be made wider than that in the first embodiment. That is, since the width of the upper recess portion 18 can be increased while keeping the width of the lower recess portion 19 small, an FET having a higher gate breakdown voltage than that of the first embodiment can be obtained without destroying the fine structure. Has the advantage that it can be manufactured.

(Third Embodiment) Next, a third embodiment of the present invention will be described. Figure 3
(A)-(e) is sectional drawing which shows the structure in the manufacturing process of FET by 3rd Embodiment.

First, in the step shown in FIG. 3A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and 5 × 10 5 are formed on a semi-insulating GaAs substrate 11.
¹⁷ cm ⁻³ Si-doped thickness of 100 n
A first active layer 13a composed of an n-type GaAs layer of about m
And an etching stop layer 14 made of an AlGaAs layer having a thickness of about 10 to ²⁰ nm, and an n-type Ga having a thickness of about 400 nm doped with Si of about 5 × 10 ¹⁷ cm ^−3.
A second active layer 13b made of an As layer is sequentially epitaxially grown. Then, on the substrate, the thickness is 100n.
An insulating film 21 made of a SiO ₂ film having a thickness of about m is formed, a part of the insulating film 21 is opened, and a source made of an AuGe / Ni / Au film is provided at positions separated from each other on the second active layer 13b. The electrode 15 and the drain electrode 16 are formed.

Next, in the step shown in FIG. 3B, the opening 31a is formed in the region where the gate electrode is to be formed on the substrate.
After the formation of the first resist film 31 having the above, the insulating film 2 using CF ₄ gas with the first resist film 31 as a mask
1 dry etching is performed to form an opening 21a having a width substantially equal to that of the opening 31a of the first resist film 31. Subsequently, the second active layer 13b is isotropically etched by using the first resist film 31 and the insulating film 21 as a mask to form the upper recess portion 18 wider than the opening 21a of the insulating film 21. At this time, although illustration of a plasma device used for etching is omitted, isotropic etching is performed under the condition that ICP is used, SiCl ₄ / SF ₆ mixed gas is introduced into the reaction chamber, and high frequency power is not applied to the substrate electrode. .

Next, in the step shown in FIG. 3C, after the first resist film 31 is removed, the opening 21a of the insulating film 21 is formed on the region extending from the insulating film 21 to the recess 18 in the upper stage. A second resist film 32 having an overlapping opening 32a is formed. However, since the width of the opening 32a of the second resist film 32 is approximately the same as the width of the opening 31a of the first resist film 31 and is offset to the drain side, the opening 32a of the second resist film 32 is formed. The inside of the opening 21a of the insulating film 21 is exposed at the drain side edge. Then, the second active layer 13b is isotropically etched using the second resist film 32 and the insulating film 21 as a mask, and only the drain-side portion of the upper recess portion 18 is opened in the opening portion of the second resist film 32. 32a and the opening portion 21a of the insulating film 21 are enlarged laterally and downward so as to be wider than the overlap region. That is, the drain side side etch part 33 is formed. At this time, although illustration of the plasma device used for etching is omitted,
Using ICP, isotropic etching is performed under the condition that a SiCl ₄ / SF ₆ mixed gas is introduced into the reaction chamber and high frequency power is not applied to the substrate electrode.

Next, in the step shown in FIG. 3D, after the second resist film 32 is removed, the second active layer 13b is anisotropically etched using the insulating film 21 as a mask to form the upper recess. In the portion 18, a lower recess portion 19 having a width substantially equal to the width of the opening 21a of the insulating film 21 is formed. At this time, the same ICP is used as a plasma device, and SiCl ₄ / SF ₆ / N ₂ mixed gas is introduced into the reaction chamber, and anisotropic etching is performed under the condition that high frequency power is applied to the substrate electrode.

Next, in the step shown in FIG. 3E, the gate electrode 20 made of Al is formed on the bottom surface of the recess 19 in the lower stage.

In this embodiment, as in the first embodiment, the recess etching of the upper stage is performed by performing the recess etching twice in the same photolithography process using the same etching apparatus under different etching conditions. Since a two-step recess structure composed of 18 and the lower recess portion 19 is formed, the same effect as that of the first embodiment can be exhibited.

In addition, the upper side recessed portion 18 is enlarged in the depth direction and the drain direction by the drain side side etched portion 33 to have a shape offset to the drain side. The recess portion has a larger recess width and depth on the drain side than the recess portion according to the first embodiment. As a result, the formed FET has a structure capable of independently controlling the gate breakdown voltage on the source side and the drain side,
Moreover, there is an advantage that the gate breakdown voltage on the drain side, which is generally required to be higher than the gate breakdown voltage on the source side, becomes higher than that of the FET of the first embodiment.

In the step shown in FIG. 3B, isotropic etching may be performed instead of anisotropic etching when forming the opening 21a of the insulating film 21. In that case, in addition to the effects of the second embodiment, the above effects can be obtained.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described. Figure 4
(A)-(e) is sectional drawing which shows the structure in the manufacturing process of FET by 4th Embodiment.

First, in the step shown in FIG. 4A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and 5 × 10 5 are formed on a semi-insulating GaAs substrate 11.
¹⁷ cm ⁻³ Si-doped thickness of 100 n
A first active layer 13a composed of an n-type GaAs layer of about m
And an etching stop layer 14 made of an AlGaAs layer having a thickness of about 10 to ²⁰ nm, and an n-type Ga having a thickness of about 400 nm doped with Si of about 5 × 10 ¹⁷ cm ^−3.
A second active layer 13b made of an As layer is sequentially epitaxially grown. Then, on the substrate, the thickness is 100n.
An insulating film 21 made of a SiO ₂ film having a thickness of about m is formed, and AuGe / Ni / Au is formed in a connection hole penetrating the insulating film 21.
The source electrode 15 and the drain electrode 16 made of a film are formed.

Next, in the step shown in FIG. 4B, after the first resist film 31 is formed on the substrate, the first resist film 31 is used as a mask to dry the insulating film 21 using CF ₄ gas. Etching is performed to form an opening 21a having a width substantially equal to that of the opening 31a of the first resist film 31.

Next, in the step shown in FIG. 4C, after removing the first resist film 31, the opening 21 is opened from above the insulating film 21.
A second resist film 32 having an opening 32a that overlaps the opening 21a of the insulating film 21 is formed on the region extending over a. However, since the width of the opening 32a of the second resist film 32 is approximately the same as the width of the opening 31a of the first resist film 31 and is offset to the drain side, the opening 32a of the second resist film 32 is formed. The inside of the opening 21a of the insulating film 21 is exposed at the drain side edge. Then, isotropic etching of the second active layer 13b is performed using the second resist film 32 and the insulating film 21 as a mask, and the opening 32a of the second resist film 32 is formed.
Further, the upper recess portion 18 wider than the overlapping region of the opening 21a of the insulating film 21 is formed. At this time, although illustration of the plasma device used for etching is omitted,
Using ICP, isotropic etching is performed under the condition that a SiCl ₄ / SF ₆ mixed gas is introduced into the reaction chamber and high frequency power is not applied to the substrate electrode.

Next, in the step shown in FIG. 4D, after the second resist film 32 is removed, the second active layer 13b is anisotropically etched using the insulating film 21 as a mask to form the upper recess. Below the portion 18, a lower recess portion 19 having a width substantially equal to the width of the opening 21 a of the insulating film 21 is formed. The side surface of the lower recess portion 19 on the source side is formed closer to the source side than the side surface of the original upper recess portion 18, so that in the final finished shape, the source side surface of the upper recess portion 18 is formed. Thus, the source-side side surface of the recess portion 19 on the lower side is in a common plane. At this time, the same ICP was used as the plasma device, and SiC was used in the reaction chamber.
Anisotropic etching is performed under the condition that a l ₄ / SF ₆ / N ₂ mixed gas is introduced and high-frequency power is applied to the substrate electrode.

Next, in the step shown in FIG. 4E, the gate electrode 20 made of Al is formed on the bottom surface of the recess 19 in the lower stage.

In the present embodiment, as in the first embodiment, the recess etching of the upper stage is performed by performing the recess etching twice under different etching conditions using the same etching apparatus in one photolithography process. Since a two-step recess structure composed of 18 and the lower recess portion 19 is formed, the same effect as that of the first embodiment can be exhibited.

In addition, comparing the recesses as a whole,
Since the upper recess portion 18 offset to the drain side is formed, a recess portion having a larger recess width and depth is formed on the drain side as compared with the shape of the recess portion of the first embodiment. As a result, the formed FET has a structure in which the gate breakdown voltage on the source side and the drain side can be controlled independently, and the gate breakdown voltage on the drain side, which is often required to be higher than the gate breakdown voltage on the source side, is the first. It has the advantage of being even higher than the FET of the first embodiment.

In the step shown in FIG. 4D, the overall shape of the recess has a two-step recess structure only on the drain side. However, in the step shown in FIG. Depending on the position of 32a and the etching amount, the upper recess 18 may extend to the left of the opening 21a of the insulating film 21. However, even in that case, the above-described effects can be exhibited.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described. Figure 5
(A)-(e) is sectional drawing which shows the structure in the manufacturing process of FET by 5th Embodiment.

First, in the step shown in FIG. 5A, the steps shown in FIGS. 4A to 4C in the fourth embodiment are completed. Then, after removing the first resist film 31 shown in FIG. 4C, the recess portion 1 above the insulating film 21 is removed.
The second resist film 3 having an opening 32a that overlaps the opening 21a of the insulating film 21 on the region extending over 8
Form 2. However, the opening 3 of the second resist film 32
Since the width of 2a is about the same as the width of the opening 31a of the first resist film 31 and is offset to the drain side, the opening of the insulating film 21 is formed in the opening 32a of the second resist film 32. The edge of 21a on the drain side is exposed. Then, isotropic etching of the second active layer 13b is performed using the second resist film 32 and the insulating film 21 as a mask, and the opening 32a of the second resist film 32 is formed.
Further, the upper recess portion 18 wider than the overlapping region of the opening 21a of the insulating film 21 is formed. At this time, although illustration of the plasma device used for etching is omitted,
Using ICP, isotropic etching is performed under the condition that a SiCl ₄ / SF ₆ mixed gas is introduced into the reaction chamber and high frequency power is not applied to the substrate electrode.

Next, in the step shown in FIG. 5B, after removing the second resist film 32, the second isotropic etching of the second active layer 13b is performed using the insulating film 21 as a mask. By this second isotropic etching, the upper recess portion 18 is expanded downward and laterally, and a region directly below the source side edge portion of the opening 21a of the insulating film 21 in the second active layer 13b. Are side-etched. At this time, although illustration of a plasma device used for etching is omitted, ICP is used and SiCl ₄ / SF ₆ is used in the reaction chamber.
Isotropic etching is performed under the condition that a mixed gas is introduced and high frequency power is not applied to the substrate electrode.

Next, in the step shown in FIG. 5C, the insulating film 2 is formed.
1 is used as a mask to anisotropically etch the second active layer 13b to form a lower recess portion 19 having a width substantially equal to the width of the opening 21a of the insulating film 21 in the upper recess portion 18. . At this time, the same I
Using CP, anisotropic gas etching is performed under the condition that a SiCl ₄ / SF ₆ / N ₂ mixed gas is introduced into the reaction chamber and high frequency power is applied to the substrate electrode. As a result, basically, the recess portion having substantially the same shape as the recess portion in the third embodiment is formed.

Next, in the step shown in FIG. 5D, the gate electrode 20 made of Al is formed on the bottom surface of the recess 19 in the lower stage.

In this embodiment, as in the first embodiment, the recess etching of the upper stage is performed by performing the recess etching twice in the same photolithography process using the same etching apparatus under different etching conditions. Since a two-step recess structure composed of 18 and the lower recess portion 19 is formed, the same effect as that of the first embodiment can be exhibited.

In addition, since the upper recess portion 18 offset to the drain side is first formed and then expanded downward and laterally, the recess width and the recess width are further increased on the drain side as compared with the fourth embodiment. A recess having a large depth is formed. As a result, the formed FET has a structure in which the gate breakdown voltage on the source side and the drain side can be independently controlled, and the drain side gate breakdown voltage that requires a higher gate breakdown voltage than the source side is the FET of the fourth embodiment. It has the advantage of being even higher than.

In the step shown in FIG. 5A, when forming the opening 21a of the insulating film 21, isotropic etching may be performed instead of anisotropic etching. In that case, there is an advantage that the dimensions of the upper recess portion 18 can be adjusted more finely.

(Sixth Embodiment) The sixth embodiment of the present invention will be described below. Figure 6
(A)-(d) is sectional drawing which shows the structure in the manufacturing process of FET by 6th Embodiment.

First, in the step shown in FIG. 6A, a buffer layer 12 made of an undoped GaAs layer having a thickness of about 300 nm and 5 × 10 5 are formed on a semi-insulating GaAs substrate 11.
¹⁷ cm ⁻³ Si-doped thickness of 100 n
A first active layer 13a composed of an n-type GaAs layer of about m
And a first etching stop layer 14a made of an AlGaAs layer having a thickness of about 10 to ²⁰ nm and 5 × 10 ¹⁷ cm
^A second active layer 13b made of an n-type GaAs layer having a thickness of about 200 nm doped with Si of about ^{−3, a} second etching stop layer 14b made of an AlGaAs layer having a thickness of about 5 to 10 nm, and 5 × S of about 10 ¹⁷ cm ^-3
i-doped n-type GaAs with a thickness of about 200 nm
After the third active layer 13c made of a layer is sequentially epitaxially grown, the source electrode 15 made of an AuGe / Ni / Au film is formed on the third active layer 13c at positions separated from each other.
And the drain electrode 16 is formed.

Next, in the step shown in FIG. 6B, the opening 17a is formed in the region where the gate electrode is to be formed on the substrate.
After forming the resist film 17 having
Is used as a mask to perform isotropic etching of the third active layer 13c to form the upper recess portion 18 wider than the opening portion 17a of the resist film 17. At this time, although illustration of a plasma device used for etching is omitted, an inductively coupled dry etching device (hereinafter referred to as ICP) is used to introduce a SiCl ₄ / SF ₆ mixed gas into the reaction chamber and apply high frequency power to the substrate electrode. Isotropic etching is performed under the condition not to do so.

Next, in the step shown in FIG. 6C, the second etching stop layer 14b and the second active layer 13b are anisotropically etched using the resist film 17 as a mask to form the recess 18 in the upper stage. Inside the opening 17a of the resist film 17
Forming a lower recessed portion 19 having a width substantially equal to the width. At this time, the same ICP is used as a plasma device, and SiCl ₄ / SF ₆ / N ₂ mixed gas is introduced into the reaction chamber, and anisotropic etching is performed under the condition that high frequency power is applied to the substrate electrode. The second etching stop layer 14b is etched little by little by this etching gas, but since it is thinner than the first etching stop layer 14a, it can be removed by increasing the etching time. As a result, a recess portion having a shape substantially the same as that of the recess portion in the first embodiment is formed.

Next, in the step shown in FIG. 6D, the gate electrode 20 made of Al is formed on the bottom surface of the recess 19 in the lower stage.

According to the method of manufacturing the FET of this embodiment,
Similar to the first embodiment, by performing the recess etching twice under different etching conditions using the same etching apparatus in one photolithography process,
Since the two-step recess structure is formed, the same effect as that of the first embodiment can be exhibited.

In addition, in the present embodiment, two AlGaAs layers (first and second etching stop layers 14a and 14b) are provided in the semiconductor region, and not only the recess portion 19 in the lower stage but also the second depth It is possible to form the upper recess portion 18 reaching the etching layer with good dimensional accuracy. Therefore, not only the depth of the lower recess portion 19 but also the depth of the upper recess portion 18 is accurately controlled, so that an FET with less variation in threshold voltage and gate breakdown voltage characteristics is formed.

In the present embodiment, an example in which the two etching stop layers 14a and 14b are provided in the active layer in the manufacturing method of the first embodiment has been described, but the second to fifth embodiments are performed. Also in form, two or more etch stop layers can be provided.

In the above second to fifth embodiments, the upper recesses are all offset to the drain side, but the present invention is not limited to such embodiments, and in some cases, the present invention is not limited thereto. It may be offset to the source side.

[0079]

According to the present invention, the following effects can be exhibited.

[0080] After the opening mouth portion is an overlap resist film and the insulating film to form a upper recess by isotropic etching as a mask to each other, by forming a recessed portion of the lower insulating film as a mask, source is the Ru obtained side and the drain side a two-stage recess shape having different widths and depths in
In the case where the gate breakdown voltage characteristic differs between the source and drain sides is also required, it is possible to manufacture the FET having the desired properties.

[0081] After the enlarged recessed portion of the upper stage side and downward, by forming a lower recess, different width and depth between the source and drain sides, and is one of the width and depth particularly large double recess shape is obtained Runode, the above effect
The fruit can be obtained more significantly.

[0082] After forming the upper recessed portion by isotropic etching the insulation Enmaku as a mask, the upper recessed portion by isotropic etching and the resist film and the insulating film opening overlap each other as a mask By performing isotropic etching that expands downward and laterally, and then forming the lower recess by anisotropic etching using the insulating film as a mask, the width and depth differ between the source side and the drain side. and one of width and depth is particularly large double recess shape is obtained Runode, it is possible to obtain the effects described above more remarkably.

[0083] By forming the recessed portion is larger recess width and depth at drain side, it often drain side gate breakdown voltage be generally high gate breakdown voltage than the source side is required to produce a high FET You can

[0084] By performing a continuous isotropic etching and anisotropic etching by changing the etching conditions using the same etching apparatus, produce F ET by the simple control and complicated operation required can do.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure in each manufacturing process of a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a structure in each manufacturing process of a field effect transistor according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the structure in each manufacturing process of the field effect transistor according to the third embodiment of the invention.

FIG. 4 is a sectional view showing a structure in each manufacturing process of the field-effect transistor according to the fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a structure in each manufacturing process of a field effect transistor according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view showing a structure in each manufacturing process of a field effect transistor according to a sixth embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process in a conventional method for manufacturing a field effect transistor.

FIG. 8 is a cross-sectional view showing a manufacturing process in a conventional method for manufacturing a field effect transistor.

[Explanation of symbols]

11 Substrate (semi-insulating GaAs substrate) 12 Buffer layer (undoped GaAs layer) 13 Active layer (n-type GaAs layer) 14 Etching stop layer (AlGaAs layer) 15 Source electrode 16 drain electrode 17 Resist film 17a opening 18 Upper recess 19 Lower recess 20 gate electrode 21 Insulating film 21a opening 23 Resist film 31 First resist film 31a opening 32 Second resist film 32a opening 33 Drain side etched part

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-5-1666764 (JP, A) JP-A-62-202564 (JP, A) JP-A-6-310541 (JP, A) JP-A-1- 133374 (JP, A) JP 10-209181 (JP, A) JP 8-97239 (JP, A) JP 6-314668 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/812 H01L 21/3065

Claims (5)

(57) [Claims] 1. A first step of forming an insulating film on a semiconductor region on a substrate, and a second step of forming a first resist film having an opening in a gate electrode formation region on the insulating film. And a third step of etching the insulating film by using the first resist film as a mask to form an opening of the insulating film, and after removing the first resist film, A second opening having an opening overlapping the opening of the insulating film
And a isotropic etching of the semiconductor region using the insulating film and the second resist film as a mask to form an opening of the second resist film in the semiconductor region. A fifth step of forming an upper recess portion wider than the overlapping region of the opening of the insulating film, a sixth step of removing the second resist film, and the semiconductor region using the insulating film as a mask. And a seventh step of forming the lower recessed portion below the opening of the insulating film by performing anisotropic etching as described in 1. above. 2. The method of manufacturing a field effect transistor according to claim 1, wherein isotropic etching of the semiconductor region is performed between the sixth step and the seventh step by using the insulating film as a mask. And a method for manufacturing a field-effect transistor, characterized in that the upper recess portion is enlarged downward and laterally. 3. A first step of forming an insulating film on a semiconductor region on a substrate, and a second step of forming a first resist film having an opening in a gate electrode forming region on the insulating film. And a third step of etching the insulating film by using the first resist film as a mask to form an opening of the insulating film, and isotropic etching of the semiconductor region using at least the insulating film as a mask. And a fourth step of forming an upper recess portion wider than the opening of the insulating film in the semiconductor region, and after removing the first resist film, the opening of the insulating film is formed on the substrate. Second having an opening that overlaps the section
And a isotropic etching of the semiconductor region is performed by using the insulating film and the second resist film as a mask, and a part of the recessed portion in the upper stage is formed into the second resist. A sixth step of enlarging the opening of the film and the opening of the insulating film so as to be wider than the overlapping region, a seventh step of removing the second resist film, and the insulating film as a mask An eighth step of anisotropically etching the semiconductor region to form a lower recess portion in a region of the semiconductor region below the opening of the insulating film. Method. 4. The method of manufacturing a field effect transistor according to claim 1 , wherein the opening of the second resist film includes a drain side edge of the opening of the insulating film. As described above, the method for manufacturing a field effect transistor, wherein the opening of the second resist film and the opening of the insulating film overlap each other. 5. A semiconductor region including a GaAs layer on a substrate
And a resist film having an opening in the gate electrode formation region
And the isotropic process of the GaAs layer using the resist film as a mask.
Etching is performed to form the resist film on the semiconductor region.
Second process to form the upper recess that is wider than the opening
And the anisotropy of the GaAs layer using the resist film as a mask.
Etching is performed to form the resist film in the semiconductor region.
The lower recess in the area below the opening
A third step, the anisotropic etching of the GaAs layer is performed with SiCl4 and
The dry etching is performed using a mixed gas of N2 , and the anisotropic etching and the isotropic etching are performed using a common plasma dry etching apparatus. While plasma etching is performed by applying high-frequency power to the electrode on which the high frequency power is stopped, the high-frequency power is stopped when performing the isotropic etching, and the common gas is used for the isotropic etching and the anisotropic etching. A method of manufacturing a field effect transistor, characterized in that a gas containing a gas is used.