JPS6260269A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To limit Rs to a small value and maintain sufficient dielectric strength of a gate and realize high (gm) and improve high frequency characteristics significantly by a method wherein a source layer and a drain layer are kept from the gate only by the thickness of a side wall. CONSTITUTION:As source and drain layers 29 of a GaAsFET are formed by epitaxial growth, heat treatment for activation of the source and drain layers 29 is not necessary and hence variation of the distribution, caused by thermal diffusion, of impurity ions which compose carriers is not created. Moreover, as the source and drain layers 29 are formed on an active layer 22 and do not touch a GaAs semi-insulating substrate directly, leakage current flowing from the low resistance source and drain layers 29 to the semi-insulating substrate 21 can be reduced and short-channel effect can be suppressed. Further, the source and drain layers 29 are kept from a gate 36 only by the thickness of a side wall 28 so that Rs can be limited to a small value and sufficient dielectric strength of the gate can be maintained. With this constitution, high (gm) and significant improvement of high frequency characteristics can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a self-aligned Schottky field effect transistor (hereinafter referred to as M) by selective epitaxial crystal growth.
The present invention relates to a method of manufacturing a field effect transistor that can be used for high frequency communications, high speed computers, etc. by forming a source and drain of a field effect transistor (abbreviated as ESFICT).

Conventional technology In recent years, in the fields of analog high-frequency communications using several to tens of GHz bands, such as those found in satellite communications, and digital circuits such as high-speed computers that require high-speed arithmetic processing, semiconductor devices have become increasingly faster and have lower noise. Developments are being actively made to improve performance such as conversion. In particular, compared to silicon, which has traditionally been the mainstream semiconductor, gallium arsenide (hereinafter referred to as GaAs)
(abbreviated as) 3) ■-■ group compound semiconductors, represented by H1/, have a higher mobility of charge carriers than silicon, and are suitable for practical use not only in the analog field but also in the digital field as higher-speed semiconductor devices. With the aim of further improving high-speed performance and shortening the gate length and reducing parasitic resistance and capacitance, we are developing ME using various I-V compound semiconductors.
SFET has been proposed.

Hereinafter, an example of a method for manufacturing a conventional field effect transistor using the above-mentioned ■-■ group compound semiconductor will be explained with reference to the drawings.

Figure 2 a, b, c, d, e, f are conventional MKSFETs.
It is a structural sectional view of the process of creating.

In Figure 2, 1 is a GaAs semi-insulating substrate, 2 is a GaAs
an active layer that becomes a channel of s M K S F K T;
3 is an ion implantation mask for forming the active layer 2 by selective ion implantation, 4 is a silicon nitride (hereinafter abbreviated as SiN) film, and 5 is a silicon dioxide (hereinafter referred to as 5in2) film that is a mask for forming the dummy gate 8a. abbreviated) pattern,
6 is an organic film that will become the dummy gate (6a) in a later process, 7 is a photoresist for forming the 5in2 pattern 6 using fluorine-based plasma 8, and 9 is a photoresist for forming the dummy gate 6a by plasma etching using the 5i02 pattern 6 as a mask. The oxygen plasma to be formed, l is the over-etch length by plasma etching using the oxygen plasma 9, and 1o is the silicon ion beam 11 using the SiO2 pattern 6 and the dummy gate 6a as a mask.
The n+ implantation order 12 formed by selective ion implantation is a 5i02 inversion pattern formed as an inversion pattern of the dummy gate 61L, and 13 and 14 are the Ga
These are the gate and source/drain electrodes of As MIC8FET.

MESFI configured as above! : The manufacturing method of T will be explained below.

First, the active layer 2 is formed on the GaAs semi-insulating substrate 1 by selective ion implantation using the ion implantation mask 3 (second
Diagram a). Next, after removing the ion implantation mask 3, a plasma-enhanced chemical vapor deposition process is performed.
Chemical Vapor Deposition
A SiN film 4 is formed by a method (abbreviated as P-IVD below),
Subsequently, a three-layer film consisting of an organic film 6, a 5in2 film, and a photoresist film is formed on the SiN film 4, and the photoresist film is patterned by photolithography to form a photoresist 7. Reactive ion etching using fluorine plasma 8 as a mask.
The 5102 film (hereinafter abbreviated as RIM) is patterned to form a groove 5102 pattern 5 (FIG. 2b).

Next, using the photoresist 7 and the 5i02 pattern 5 as a mask, the organic film 6 is formed perpendicularly to the GaAs semi-insulating substrate 1 by RIM using oxygen plasma 9, and then overetching is performed to length l. A dummy gate 8a is formed. Note that the photoresist 7 disappears by RIIC using the oxygen plasma 9 (FIG. 2C), and then selective ion implantation is performed with the silicon ion beam 11 using the SiO□ pattern 5 and the dummy gate 6a as a mask. An entrance 1o is formed (FIG. 2d).

In FIG. 2d, the n+ implanted region 10 is formed apart from the dummy gate 6a by the overetch length l. Next, 8i0. After forming the film, a SiO 2 inversion pattern 12 is formed by a lift-off method using the dummy game (esL) and the organic film 6 (FIG. 2e). Furthermore, the active layer 2 and the n+
800 to activate the ions implanted at implantation order 0.
After annealing for about 20 minutes, a part of the SiO2 inversion pattern 12 and a part of the SiN film 4 are removed, and the source/drain electrodes 14 of the MESFIET are removed.
460'03 so that the source/drain/electrode 14 and the n+ implantation order 0 are in ohmic contact.
Perform alloying for about 0 seconds. Finally, the S in the opening of the 5i02 inversion pattern 12 on the active layer 2
After removing the iN film 4, the gate 13 is formed to complete the GaAs MICS FET (second
Figure f). (For example, Yamazaki et al., Institute of Electrical and Electronics Engineers, Meeting on Electronic Devices, Vol. 7, Vol. 7, Vol. 29, No. 11, pp. 1772-1777.

1982 (IEE Transaction
ns □nElectron Devices, VO
LiD-29, No, 11°PP1772-1777 (
(1982)). As described above, by forming the dummy gate 6a to have an overetch length l with respect to the 5i02 pattern 5, the gate 13 and the n+ implanted part 1o are formed.
are formed by self-alignment separated by the overetch length e, which reduces the parasitic resistance (hereinafter abbreviated as Rs) between the gate and source of the GaAs MESFET, and also increases the gate resistance by the overetch length l. The withstand voltage is also maintained, and the GaAs MKSFET
This is the second characteristic.

Problems to be Solved by the Invention However, in the above structure, during annealing for activating the selectively implanted ions, the n+ implanted portion 10 is damaged by thermal diffusion of the implanted ions.
Direction parallel to the surface of the aAs semi-insulating substrate 1, that is, MKS
Spreading in the direction of the channel of the FET, the MF, 5FIC
A so-called short channel effect occurs in which the pinch-off voltage of T changes in a negative direction as the gate length becomes shorter. The short channel effect makes it difficult to control the drain current by the Gate of the MESFET, increases drain conguctance (hereinafter abbreviated as gd), decreases mutual conductance (hereinafter abbreviated as gm), and causes a short gate. Increasing the length will actually deteriorate the characteristics. (For example, Matsumoto et al.

IEICE Technical Report, Volume 82, No. 131.

fga pages 9-94, (, 5SD82-69))
.

Further, the n+ implanted portion 1o becomes the source/drain of the MESFET, but as the gate length of the MIC5FKT becomes shorter, the source/drain interval also becomes shorter.・The leakage current flowing between the drains also causes the g
Since d increases and the gm decreases, there is a problem in that this impedes improvement in characteristics.

In view of the above problems, the present invention provides an MF
, the source and drain of the 5FET are fabricated in a self-aligned manner by the epitaxial 9-7' shear method, reducing the short channel effect and reducing Rs, thereby creating a method for manufacturing high-speed, high-performance field effect transistors. This is what we provide.

Means for Solving the Problems In order to solve the above problems, the method for manufacturing a field effect transistor of the present invention provides a method for manufacturing a Schottky field effect transistor by gate pattern inversion. A dummy gate is formed on a compound semi-insulating substrate to form a pattern-inverted gate in a later process, a sidewall film that can be selectively removed from the dummy gate is formed on the sidewall of the dummy gate, and the A low resistance epitaxial layer is grown on the active layer to serve as the source and drain of the Schottky field effect transistor by self-alignment, and at the same time a polycrystalline layer or an amorphous layer is grown on the dummy gate and the sidewall film. The method includes the steps of growing a polycrystalline layer or an amorphous layer, and then removing the sidewall film on which the polycrystalline layer or amorphous layer has grown, and then inverting the pattern of the dummy gate to form 10 gates.

Effect of the present invention By forming the source and drain of the MESFET as an epitaxial layer on the upper surface of the active layer through the above-described process, there is no need for annealing and the distance between the source and drain can be shortened by thermal diffusion of implanted ions. GaA source and drain with low resistance
By forming the active layer with respect to the GaAg semi-insulating substrate, leakage current from the source/drain to the GaAg semi-insulating substrate is suppressed, and the short channel effect is reduced. In addition, the source and drain are formed in self-alignment with the gate, and are separated from the gate by the sidewall film provided on the dummy gate, so Rs is small and the gate has a sufficient breakdown voltage, making it possible to achieve high g
This results in improvements in speed and high-speed performance.

EXAMPLE A method of manufacturing a field effect transistor according to an example of the present invention will be described below with reference to the drawings.

Figure 1"+ b+ C+ d+ 8+ f1g+ h+
'+j is a structural cross-sectional view showing a method of manufacturing a field effect transistor according to an embodiment of the present invention.

Figure 1'+ b+ C+ d+ θ+ f+ g, h+
'+j, k, 21 is a GaAs semi-insulating substrate,
22 is a GaAsME formed by selective ion implantation of a silicon ion beam 24 using an ion implantation mask 23;
SFET active layer; 25, gate pattern; 26, fluorine-based plasma 27 using the gate pattern 26 as a mask;
28 is a sidewall film formed on the sidewalls of the dummy gate (26a) and the insulating film 26, and 29 is a sidewall film formed on the side wall of the active layer 2
The Ga layer formed as a low resistance epitaxial layer on 2
Source/drain layers of the AsMESFET; 3o is a deposited layer formed as an amorphous or polycrystalline film on the dummy gate 26& and on the insulating film 26; 31 is a deposited layer for selectively removing the deposited layer 30; oxygen plasma 32
33 is a source/drain electrode that is ohmically connected to the source/drain layer 22; 34 is a gate inversion resist that becomes an inversion pattern of the dummy gate (26a); 35 is a gate 36 that is lifted off together with the gate inversion resist 34; This is a lift-off resist to be formed using a method.

A method of manufacturing the field effect transistor configured as described above will be described below with reference to FIG. 1.

Figure 1 shows the manufacturing process. First, a silicon ion beam 24 with an acceleration voltage of 100 keV is implanted into a GaAs semi-insulating substrate 21 having a resistivity of 107 Ω or more by patterning a photoresist. Dose amount 6 using mask 23. ○X 1012dos
Selective ion implantation is performed at θ/d to form an active layer 22 (FIG. 1a). Next, after removing the ion implantation mask 23 with an organic solvent, the S10□ film is deposited by low pressure chemical vapor deposition (Low
Pressure Chemical Vapor De
The active layer 22 is formed to a thickness of approximately 0.2 μm by a method (hereinafter abbreviated as LPGVD), and cap annealed for 85013B/'020 minutes.
Activation. Next, after removing the SiO□ film in 171,
The 5in2 film was made to a thickness of about 0.8μm using the LPCVD method again.
After forming an insulating film 26 that will become a dummy gate 261L in a later process, a gate pattern 2 is formed using aluminum (hereinafter abbreviated as A7) to a thickness of 0.1 μm using a lift-off method.
6 (Fig. 1b).

Next, the gate pattern 25 is masked and the insulating film 26 is removed by RIK using a fluorine-based plasma 27.
A dummy gate 2eSIL is formed by performing anisotropic etching substantially perpendicular to the aAs semi-insulating substrate 21 (first
Figure C). Next, after removing the gate pattern 25 made of A4 with hydrochloric acid, a SiN film with a thickness of about 0.15 μm is formed on the entire surface by P-CVD method, and then R is again applied with fluorine-based plasma 27.
The SiN film on the active layer 22 is removed by IIC, and at the same time, the SiN film is left on the side walls of the dummy game (26) to form a side wall film 28 (FIG. 1d). Next, molecular beam epitaxial
Substrate source 14 by taxia1 (abbreviated as MBK) method
Low-resistance GaAs with a carrier density of about 3 x 1018 cm with silicon de-hunted at 600'C
A source/drain layer 29 made of low-resistance GaAs is formed on the active layer 22 by depositing it on the active layer 22, and at the same time, a source/drain layer 29 made of low-resistance GaAs is formed on the active layer 22, and at the same time, a multilayer layer 29 is formed on the dummy gate 26IL, the insulating film 26, and the sidewall film 28. A deposited layer 30 made of crystallized GaAs with high resistance is formed (FIG. 1e).

Next, after spin-coating photoresist, oxygen plasma 32
The 7th photoresist is etched to form an organic film 31 with the deposited layer 3o exposed (FIG. 1f).
. Next, the deposited layer 3o which has been exposed is removed using a tartaric acid/hydrogen peroxide based GaAs etchant (FIG. 1g).

Next, the organic film 31 is removed using an organic solvent, and
After removing the sidewall film 28 with hot phosphoric acid heated to ~180°C, ohmic electrodes made of a gold-germanium alloy are formed and used as source/drain electrodes 33 (first
Figure h). Next, after spin-coating a negative resist, the negative resist 15-,-; is etched again using oxygen plasma 32 to form a gate inversion resist 34, and the dummy gate 26a is located (first
Figure i). Next, patterning is performed using a positive resist so that the beginning portion of the dummy gate 261L is sufficiently exposed to form a lift-off resist 35, and then the dummy gate 26& is removed using a hydrofluoric acid-based etchant (FIG. 1). )).

Next, Al is vacuum-deposited, and the gate 36 is formed by a lift-off method by removing the lift-off resist 36 and the gate inversion resist 34 (FIG. 1k).

As described above, according to this embodiment, since the source/drain layer 29 of the GaAsFET is formed by epitaxial growth, heat treatment for activating the source/drain layer 29 is not required, and impurities that provide carriers are not required. Furthermore, the source/drain layer 2
9 is formed on the top of the active layer 22 and is not in direct contact with the GaAs semi-insulating substrate, so there is little leakage current from the low-resistance source/drain layer 29 to the GaA semi-insulating substrate 21, which reduces the short channel effect. This results in a reduction in The cut source/drain layer 29 is separated from the gate 36 by only the thickness of the sidewall film 28 (approximately 0.15 μm in this embodiment), which suppresses Rs and allows GaA
s M E S F E T +7) The gate breakdown voltage can be maintained, the gm of the GaAs MESFET can be increased, and the high frequency characteristics can be significantly improved.

In this example, the dummy game) 28a is a 5102 film,
Although the sidewall film 28 is a SiN film, the dummy gate 26a and the sidewall film 28 may be made of any material as long as they do not react with the active layer 22 and can be selectively removed from each other. For example, the dummy gate 26a may be made of Ga, -xAdxAs (x40 .3) The sidewall film 28 may be made of a high melting point metal such as tungsten (W) or a silicide thereof. In addition, the formation of the source/drain layer 29 was performed using a liquid phase method of 17 l, -7
Epi taxial (LPE) method and vapor phase epitaxy'
l:/ ya# (VaperPhase Epitax
ial (V P E ) method or metal organic chemical vapor deposition (Metal Organic Chemical
l Vaper Deposition (MO-CV
D)) It may be formed by the method.

Effects of the Invention As described above, the present invention enables the gate to be formed by pattern inversion in a later process on a semi-insulating substrate of an IV group compound having an active layer when manufacturing a Schottky field effect transistor by inverting the gate pattern. A dummy gate is formed for forming the dummy gate, a sidewall film that can be selectively removed from the dummy gate is formed on the sidewall of the dummy gate, a low resistance epitaxial layer is grown on the active layer, and a low resistance epitaxial layer is grown on the active layer. growing a polycrystalline layer or an amorphous layer as a source and a drain of a Schottky field effect transistor, and simultaneously growing a polycrystalline layer or an amorphous layer on the dummy gate and the sidewall film, and further growing the polycrystalline layer or the amorphous layer. After removing the distorted sidewall film, proceed to step 18- By inverting the pattern of the dummy gate and forming the gate, heat treatment for forming the source/drain is unnecessary, and carrier distribution due to thermal diffusion is reduced. Since the source/drain, which has no change and has a low resistance, does not directly contact the IV group compound semi-insulating substrate, the leakage current to the ■-■ group compound semi-insulating substrate is also small. Since the short channel effect is reduced and the source/drain layer is separated from the gate by only the thickness of the sidewall film, Rs can be kept small and the gate withstand voltage can be maintained sufficiently, making it possible to increase the gm of MISFETs and realize high frequencies. The characteristics will be significantly improved.

[Brief explanation of drawings]

Figure 1 a, b, c, d, e, f, g, h, i. Figures 2a, 2b, and 2c are structural cross-sectional views showing a method for manufacturing a field effect transistor according to an embodiment of the present invention.
d, e, and f are structural cross-sectional views showing a conventional method of manufacturing a field effect transistor. 1.21...GaAs semi-insulating substrate, 2,22
...19 bae. ...Active layer, 3, 23...Ion implantation mask, 4...Silicon nitride film, 6a, 26a...
...Dummy gate, 11.24...Silicon ion beam, 1°...N+ implantation part, 12.
...5i02 inverted putter/, 13.36...
・Gate, 14.33... Source drain/electrode, 28... Side wall film, 29... Source...
Drain layer, 30... Deposition layer, 6, 31...
...Organic film, 32...Oxygen plasma, 34.
...Gate inversion resist, 36...Lift-off resist.

Claims (2)

[Claims] (1) When manufacturing a Schottky field effect transistor by gate pattern inversion, III-
forming a dummy gate on a group V compound semi-insulating substrate for forming a gate by pattern inversion in a later step; forming a sidewall film on the sidewall of the dummy gate that can be selectively removed from the dummy gate; A low resistance epitaxial layer is grown on the active layer to serve as the source and drain of the Schottky field effect transistor by self-alignment, and at the same time a polycrystalline layer or an amorphous layer is grown on the dummy gate and the sidewall film. A method for manufacturing a field effect transistor, comprising growing a layer and removing the grown sidewall film of the polycrystalline layer or the amorphous layer, and then inverting the pattern of the dummy gate to form a gate. (2) A method for manufacturing a field effect transistor according to claim 1, characterized in that the dummy gate is made of silicon oxide and the sidewall film is made of silicon nitride.