JPS62274670A - Manufacture of junction type field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent the generation of an interfacial deterioration and to contrive reduction in the gate capacitance of the title transistor by a method wherein a gate electrode is provided on the gate region formed by ion-implanting impurities through a window provided on a mask layer, the mask layer is removed, and after the surface of a substrate has been removed, a source region and a drain region are formed. CONSTITUTION:As the surface of the GaAs substrate 7, the interfacial characteristics of which are deteriorated by the application of heat, is removed after a P<+> region 2 has been formed, the problem of deterioration in element characteristics resulting from the interfacial characteristics between the GaAs and an SI3N4 film, generated on the J-FET which was heretofore in use, is not generated. In the FET which was heretofore in use, the width of a diffused P<+> region in the state as it is became the gate length of the completed FET, but the circumferential part of the P<+> region 2 in the GaAs substrate is removed by etching, and the gate length can be made short easily. Therefore, the effective gate length of the substrate can be made to 1.0 mum or less. Besides, as the circumferential part of the P<+> region 2 is removed, no P-N junction is present on the side wall, and a gate capacitance can be reduced to that extent.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a manufacturing method for obtaining a submicron gate junction field effect transistor using a self-line.

[Summary of the invention]

The present invention is a method for manufacturing a junction field effect transistor, in which a mask layer made of a 5iJ-film or the like is provided on a semiconductor substrate such as GaAs, a window is formed in the mask layer, and impurity ions are implanted through the window. After removing the mask layer and removing the exposed semiconductor substrate surface, a source region and a drain region are formed to prevent interface deterioration. A junction field effect transistor with a short gate length and reduced gate capacitance is obtained using the Selfa line.

[Conventional technology]

Field effect transistors (FETs) include Schottky gate transistors, junction gate transistors, and insulated gate transistors. MOSFET on Si semiconductor substrate
Insulated gate transistors such as GaAs
Since a good insulating film cannot be obtained on the substrate, a Schottky gate or junction gate transistor is used. Ga
As As has a large band cap, a semi-insulating substrate with a high specific resistance of 108 Ω/edge can be obtained, and L is formed in this surface area.
Forming an SI facilitates element isolation and reduces parasitic capacitance. Junction gate transistors are more thermally stable than Schottky gate FETs. When a surge-resistant enhancement type FET is constructed of a junction gate FET and a logic circuit is used, the logic amplitude can be increased. On the other hand, junction gate transistors using compound semiconductors have drawbacks such as difficulty in shortening the gate length, high gate resistance, complicated processes, and difficulty in reducing source resistance. It is not used as a semiconductor device.

A conventional method for manufacturing a junction gate FET will be explained based on FIGS. 2A, B, and C. First, as shown in Figure A, an N-type N1
form. Next, as shown in figure B, 5ti is applied to the surface of the substrate 7.
N,lI! 3 is formed on the entire surface, a window for forming a gate region is opened, and Zn is diffused to form a P-type diffusion layer 2. After that, as shown in Figure C, windows for the source and drain are opened in the 5iJ4 film 3, and Au-Ge metal is deposited on the source electrode 8.
, a drain electrode 9 is provided, an ohmic electrode is formed on the P-type diffusion layer 2 using an Au--Zn metal, and a gate electrode 4 is provided to complete the junction gate FET. (Unexamined Japanese Patent Publication No. 5
9-213172) [Problems to be solved by the invention] In the conventional method for manufacturing a junction gate FET, GaA
The 5IJ4 film 3 provided on the surface of the s-substrate 7 is used as a diffusion mask, and after the device is completed, it is used as a passivation film. However, since this 5iJ4 film 3 is subjected to heat treatment during diffusion, etc., the interface characteristics with the GaAs substrate surface deteriorate. For example, in the conventional example shown in Figure 2, after the ion implantation process shown in Figure A, annealing is performed at 800°C for 20 to 30 minutes in order to recover crystal defects generated by the ion implantation. GaA
The interfacial properties of the s surface deteriorate. However, in the subsequent diffusion step in Figure B, heat treatment is performed at 600 to 650°C for 20 minutes or more, and the GaAs substrate 7 and the 5iJa film 3
The interfacial properties between the two will further deteriorate. In the conventional junction gate FET, the 5iJL film 3 is used as a passivation film without being removed, and the GaAs surface with deteriorated interface characteristics remains, resulting in a large leakage current in the completed FET and isolation There is a problem that the characteristics are not good.

Furthermore, in the conventional method for manufacturing junction gate FETs,
Since the P'' region 2 serving as the gate region is formed only by a diffusion process, it is difficult to shorten the gate length due to lateral diffusion, and it is extremely difficult to reduce the effective gate length to 1.0 μm or less.

[Means for solving problems]

The present invention is a junction field effect transistor (J-FET)
In the manufacturing method, a mask layer made of a 5iJ4 film or the like is provided on a semiconductor substrate such as GaAs, a window is formed therein, and a gate region is formed by implanting impurity ions through the window. The above problem can be solved by providing a gate electrode on the gate region, removing the mask layer, removing the exposed surface of the semiconductor substrate, and then forming a source region and a drain region by ion implantation using the gate electrode as a mask. Settled.

[Effect]

In the manufacturing method of the present invention, after the P' region 2 is formed, heat is applied to the GaAs substrate 7 whose interface characteristics have deteriorated.
Since the surface of the 5i3Na film is removed, the problem of deterioration in device characteristics due to the interface characteristics between the GaAs substrate and the 5i3Na film does not occur as in conventional J-FETs.

In the conventional FET, the width of the diffused P'' region is the gate length of the completed FET, but in the manufacturing method of the present invention, the peripheral part of the P'' region 2 in the GaAs substrate is Since it is easy to remove by etching and shorten the gate length, the effective gate length can be easily reduced to 1.0 μm or less.

Furthermore, since the peripheral portion of the P'' region 2 is removed, no PN junction exists on the sidewall, and the gate capacitance is reduced accordingly.

〔Example〕

The manufacturing method of the present invention will be explained based on FIGS. 1A to 1E.

A Similar to FIG. 2A, an N-channel layer 1 was formed in the semi-insulating GaAs layer 7 by Si ion implantation, and the
Anneal for 0-30 minutes. Furthermore, 5i3Nn film 3
Open a window and implant Zn ions, then 600 to 65
Annealing is performed at 0° C. for 20 minutes to form P′ region 2. Next, W-5i 4, a refractory metal, is deposited.

The 5i3L film 3 used to form the B P+ region 2 is completely removed.

The N-channel N10 surface of the GaAs substrate whose interface characteristics have deteriorated due to C surface levels and the like is removed by etching. The amount of etch-off at this time does not necessarily have to reach the purity of the P-N junction, but in order to reduce the gate capacitance or shorten the effective gate length, it is necessary to etch off to near the depth of the P-N junction. °
Need to cut off. However, regarding controllability,
It is better not to etch off too deeply.

Therefore, the amount of etching may be controlled depending on the required characteristics of the device.

Using the gate electrode 4 made of DW-Si metal as a mask, an N'' region 5 is formed by Si ion implantation.

As a result, the source and drain regions can be formed with the same precision as self-alignment.

E Passivation film 6 made of Si3N4 film on the entire surface
After forming the N'' region 5, infrared annealing is performed using a halogen lamp to activate the N'' region 5.

Note that it is not always necessary to provide this passivation film 6.

Thereafter, source and drain electrodes are formed to complete the J-FET.

In the above description, GaAs is used as the semiconductor substrate, but it goes without saying that other semiconductor materials such as 1-2 group compounds and Si may also be used.

〔Effect of the invention〕

The manufacturing method of the present invention has the following features.

(i) Since the surface with degraded interfacial properties caused by heat treatment has been removed, the FET manufactured according to the present invention will not have increased leakage current or degraded isolation properties.

(ii) Since there is no PN junction in the sidewall portion, the gate capacitance is reduced accordingly.

(iii) Since the source and drain regions are formed using the gate electrode as a mask for ion implantation, these regions are formed as self-aligned lines. −′ ゛(1v
) Since the periphery of the gate region is etched off, the gate length can be shortened.

(v) In the J-FET structure according to the present invention, it is easier to separate the N" region from the P" region compared to the conventional J-FET structure, so that the J-FIE deviates from the design value.
The value of vth of T can be made extremely small.

[Brief explanation of the drawing]

FIGS. 1A to 1E are diagrams showing a method of manufacturing a J-FET according to the present invention. FIGS. 2A to 2C are diagrams showing a conventional J-PET manufacturing method. 1...N channel 2...P'' region 3...5iJ4 film 4...Gate electrode 5...N° channel 6... ... Passivation film 7 ... Semi-insulating GaAs layer 8 ... Source electrode 9 ... Drain electrode

Claims (1)

[Claims] A step of forming a mask having an opening on a semiconductor substrate, a step of forming a gate region in the semiconductor substrate through the opening, and a step of forming a gate electrode on the gate region. A method for manufacturing a junction field effect transistor, comprising the steps of: removing the mask; removing the exposed surface of the semiconductor substrate; and forming a source region and a drain region on the semiconductor substrate.