JPH0897232A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To form a Schottky barrier gate type FET, improve the gate withstand voltage, reduce the capacitance between the gate and the drain, and improve high frequency characteristics. CONSTITUTION: The surface of an N-type GaAs layer 3 exposed in an aperture part formed in a silicon film 4 formed on an N-type GaAs layer 3 is irradiated with inert gas plasma, thereby forming a damage layer 6. A side wall spacer is formed on the side wall of the aperture part. The silicon oxide film and the side wall spacer are used as masks, and the damage layer 6 and the N-type GaAs layer 3 are isotropically etched. Thereby a recess 8 which is shallow and wide is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a Schottky barrier gate type field effect transistor.

[0002]

2. Description of the Related Art A compound semiconductor device, which is often used as an amplifying element in the microwave and millimeter wave band, uses a recess structure that can realize a high gate breakdown voltage in order to improve high output characteristics. In order to improve the above, a T-shaped gate electrode having a short gate length and a large cross-sectional area of the gate electrode is used.

FIGS. 4A to 4D are schematic sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

First, as shown in FIG. 4A, a non-doped GaAs layer 2 and an n-type GaAs layer 2 are formed on a semi-insulating GaAs substrate 1.
L on the operation layer formed by sequentially laminating the p-type GaAs layers 3.
A silicon oxide film 4 having a thickness of 300 nm is formed by a PCVD (low pressure CVD) method, and is selectively anisotropically dry-etched to form a gate opening 15.

Next, as shown in FIG. 4B, the silicon oxide film 4 is masked and n-type GaAs in the gate opening 15 is formed.
The surface of the layer 3 is treated with sulfuric acid (H ₂ SO ₄ ) + hydrogen peroxide solution (H ₂
O ₂ ) + water (H ₂ O) mixture or phosphoric acid (H ₃ PO ₄ ) +
The recess 8 is formed by wet etching using a mixed solution of aqueous hydrogen peroxide (H ₂ O ₂ ) + water (H ₂ O) or isotropic dry etching using a gas containing chlorine (C ₁₂ ). . Here, if the width of the recess 8 is widened, the gate breakdown voltage can be improved and the gate-drain capacitance can be reduced, but in the case of isotropic etching, the etching rate in the horizontal direction is equal to or slightly higher than the etching rate in the vertical direction. Since it is slow, when the recess having the recess depth D _r is formed, the width of the side etching generated on both sides of the end of the gate opening is at most D _r . If the dimension of the gate opening 14 is L _g ,
Recess width L _r is maximized L _g + 2 × D _r.

Next, as shown in FIG. 4C, after the photoresist film 9 applied on the silicon oxide film 4 is patterned to form an inversely tapered opening, for example, as a metal for a gate electrode, for example, A laminated film 10 of aluminum and titanium (hereinafter referred to as an A1 / Ti film) 10 is deposited.

Next, as shown in FIG. 4D, the T-shaped gate electrode 11 is formed by removing the photoresist film 9 and the Al / Ti film 10 on the photoresist film 9 by a lift-off method. The semiconductor device is formed by removing the silicon oxide film 4 in the electrode and drain electrode formation region and selectively forming the source electrode 12 and the drain electrode 13 by an evaporation method or a sputtering method.

[0008]

In this conventional method of manufacturing a semiconductor device, in order to improve the gate breakdown voltage and reduce the gate-drain capacitance, even if the recess width L _r is widened, the depth D _r is increased. In the case of forming the recess of the above, the recess width L _r is up to 2 × D _r larger than the dimension L _g of the gate opening.
Although it becomes longer and becomes L _g + 2 × D _r , it was difficult to further widen the recess width L _r .

[0009] The longer the etching time recessed to lengthen the recess width L _r, resulting in the active layer is etched deeply. In this case, since the amount of carriers in the n-type GaAs layer is reduced, the current flowing between the source and the drain of the compound semiconductor device is reduced, and the output is reduced. That is, in the conventional method, the recess width L _r is determined by the gate opening size L _g and the recess depth D _r ,
It has been difficult to freely increase the recess width L _r .

An object of the present invention is to provide a method of manufacturing a semiconductor device which can improve the gate breakdown voltage and high frequency characteristics by expanding the recess width without increasing the recess depth.

[0011]

According to a first method of manufacturing a semiconductor device of the present invention, a first insulating film is formed on an operation layer formed on a semiconductor substrate, and the first insulating film is selectively formed. Forming an opening in the substrate to expose the surface of the operating layer, irradiating the exposed surface of the operating layer with plasma to form a damage layer, and forming a second insulating film on the surface including the damage layer. And etch back to deposit the first of the opening
Forming a side wall spacer on the side wall of the insulating film, and forming a recess by isotropically etching the surface of the operating layer including the damaged layer using the first insulating film and the side wall spacer as a mask. And forming a gate electrode in the recess of the opening using the sidewall spacer as a mask.

A second method of manufacturing a semiconductor device according to the present invention is
A step of forming a damaged layer by irradiating the surface of the operating layer with plasma using a photoresist film, which is applied and patterned on the operating layer formed on a semiconductor substrate, as a mask; and after removing the photoresist film, the damaged layer Forming an insulating film on the surface including and forming an opening for forming a gate electrode to expose the surface of the damaged layer; and a surface of the operation layer including the damaged layer using the insulating film as a mask. Isotropically etched to form a recess, and a step of forming a gate electrode in the recess of the opening using the insulating film as a mask.

[0013]

Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1E are schematic cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention.

First, as shown in FIG. 1A, a non-doped G having a thickness of 500 nm is formed on a semi-insulating GaAs substrate 1.
After forming the n-type GaAs layer 3 having a thickness of about 250 nm doped with the aAs layer 2 and Si at about 2 × 10 ¹⁷ cm ⁻³ , the silicon oxide (thickness: 300 nm) is formed on the n-type GaAs layer 3 by LPCVD. An SiO ₂ ) film 4 is formed. Then, the silicon oxide film 4 is coated and patterned by a lithography technique to form a recess width L _r (1 μm
m) Using a photoresist film (not shown) having an opening equivalent to that of m) as a mask, the silicon oxide film 4 is dry-etched using CHF ₃ , CF _4, SF ₆ gas or the like, and the surface of the n-type GaAs layer 3 An opening for exposing is formed. Next, the exposed surface of the n-type GaAs layer 3 is irradiated with plasma using an inert gas 5 such as argon (Ar) or xenon (Xe) or a nitrogen (N ₂ ) gas, thereby forming the n-type GaAs layer 3 in the opening. The damage layer 6 is formed from the surface of the substrate to a depth of about 80 nm, and the photoresist film is removed.

Here, the dry etching of the silicon oxide film 4 and the plasma irradiation for forming the damaged layer 6 can be performed by the same apparatus, and the apparatus is a reactive ion etching apparatus (RIE), a magnetron reactive ion etching apparatus (MIE). ), A dry etching apparatus such as an electron cyclotron resonance plasma apparatus (ECR) can be used.
Further, the depth of the damage layer 6 needs to be shallower than the recess depth D _r .

Next, as shown in FIG. 1B, a 500 nm thick silicon oxide film 7 is formed by LPCVD on the surface including the n-type GaAs layer 3 in the opening where the damage layer 6 is formed. .

Next, as shown in FIG. 1 (c), CH
F _3, CF ₄ gas and SF ₆ gas anisotropic dry etching of a silicon oxide film 7 by using (etch back), to form sidewall spacers 7a leaving the silicon oxide film 7 on the side surface of the silicon oxide film 4, N-type GaA having damage layer 6
A gate opening having a width of 0.3 μm that exposes the surface of the s layer 3 is formed. Next, by wet etching using _{H2SO 4 + H 2 O 2 +} H 2 O mixture or _{H 3 PO 4 + H 2 O} 2 + H 2 O mixed solution of the silicon oxide film 4 and the sidewall spacer 7a as a mask, n-type The GaAs layer 3 is isotropically etched to form a recess 8 having a depth of 0.1 μm and a width of 1.0 μm. At this time, the damaged layer 6 is in an amorphous state and has an etching rate faster than that of the undamaged GaAs layer, so that the side etching easily proceeds in the horizontal direction. Further, since the depth of the damage layer 6 is shallower than the recess depth Dr, the damage layer does not remain in the n-type GaAs layer 3. Incidentally, the recess formation, not only wet etching, C1 is ₂ is also possible by dry etching using a mixed gas containing, isotropic in the relatively high pressure conditions (hundreds mTorr) in this case It is necessary to enable etching.

Next, as shown in FIG. 1D, a photoresist film 9 is applied on the silicon oxide film 4 and patterned to have a size larger than the gate opening size L _g and a reverse taper shape. Form an opening. Next, an Al film having a thickness of 500 nm and a 50 nm
The Al / Ti film 10 in which the Ti film is laminated is deposited.

Next, as shown in FIG. 1E, the photoresist film 9 and the Al / Ti film 10 on the photoresist film 9 are removed by a lift-off method to form a gate electrode 11, and a source electrode and a drain are formed. The source electrode 1 is formed on the surface of the n-type GaAs layer 3 exposed by selectively removing the silicon oxide film 4 in the electrode formation region by vapor deposition or sputtering.
2 and the drain electrode 13 to form a Schottky barrier gate FET.

Although the gate electrode is formed by lift-off in the above method, after forming the recess 8 in the steps up to FIG. 1C, as shown in FIG. 2A, the surface including the gate opening is formed. Al / Ti film 10 is deposited on the
(B), a, Ar ion milling or C1 ₂
By RIE etching using a mixed gas containing
The gate electrode 11 may be formed by patterning the 1 / Ti film 10.

Further, although the case where the GaAs layer is formed on the GaAs substrate has been described, aluminum gallium arsenide (A1GaAs) / GaAs or A1GaAs / indium gallium arsenide (InGaA) is formed on the GaAs substrate.
s) / GaAs or the like can be grown to form a two-dimensional electron gas layer. In this case, the above-mentioned H ₂
SO ₄ + H ₂ O ₂ + H ₂ O mixture or H ₃ PO ₄ + H ₂
O ₂ + H ₂ O wet etching mixture with or, in addition the dry etching using a mixed gas containing C1 _2, citric acid and hydrogen peroxide (H ₂ O ₂₎ + water (H ₂
O) selective wet etching using a mixed solution or selective dry etching using a mixed gas containing chlorine and fluorine to selectively etch the GaAs layer with respect to the A1GaAs layer or the InGaAs layer to form a recess. It can also be formed.

3 (a) to 3 (e) are sectional views of the semiconductor chip in the order of steps for explaining the second embodiment of the present invention.

First, as shown in FIG.
Non-doped GaAs layer 2 and n-type GaA on the substrate 1
The s layer 3 is sequentially laminated and formed, and a photoresist film 9 is applied on the n-type GaAs layer 3 and patterned to form an opening having a size equivalent to the recess width L _r (1 μm). Next, using the photoresist film 9 as a mask, argon (A
r) or xenon (Xe) or another inert gas 5 or nitrogen (N ₂ ) gas is applied to the n-type GaAs layer 3 by plasma irradiation.
The damage layer 6 is formed to a depth of about 80 nm from the surface.

Next, as shown in FIG. 3B, after removing the photoresist film 14, a 300 nm-thick film is formed on the n-type GaAs layer 3 having the damaged layer 6 by LPCVD.
The silicon oxide film 4 is formed, and the silicon oxide film is selectively dry-etched using CHF ₃ , CF ₄ gas or SF ₆ gas to form the gate opening 15.

Next, as shown in FIG. 3C, using the silicon oxide film 4 as a mask, H ₂ SO ₄ + H ₂ O ₂ + H ₂ O
The mixture or _{H 3 PO 4 + H 2 O} + H 2 O mixture n-type surface of the GaAs layer 3 by wet etching using the isotropically etching depth 100 nm, to form a recess 8 of width 1.0μm . Here, in the recess formation, as in the first embodiment, dry etching may be used instead of wet etching.

Next, as shown in FIG. 3D, a photoresist film 9 having an inversely tapered opening is formed on the silicon oxide film 4 as in the first embodiment, and Al / Ti is formed.
A film 10 is deposited to form a T-shaped gate electrode 11 in the recess 8.

Next, as shown in FIG. 3E, the photoresist film 9 and the Al / Ti film 10 are formed by the lift-off method.
Is removed, and a source electrode 12 and a drain electrode 13 are respectively formed in the openings formed in the silicon oxide film 4 to form a semiconductor device.

The second embodiment has an advantage that the step of forming the side wall spacer can be omitted and the step can be simplified.

[0030]

As described above, according to the present invention, a damaged layer is formed by selectively irradiating the surface of the operation layer with plasma.
By providing a gate opening in the insulating film provided on the surface including the damaged layer and forming a recess by isotropically etching the damaged layer exposed in the gate opening, the width of the side etch is made smaller than the recess depth. The recess width L _r is L _g without increasing the recess depth.
A wide recess wider than (gate opening size) + 2D _r (recess depth) can be formed, and the gate breakdown voltage can be significantly improved. Incidentally, L _g = 0.
FET of 3 μm, L _r = 0.5 μm, D _r = 0.1 μm
L _g = 0.3 μm and L _r = 1.0 μ according to the present invention.
The withstand voltage was improved by 5 V in the FET in which m and D _r = 0.1 μm.

Further, when a wide recess having a large recess width is formed even though the recess depth is shallow, the capacitance between the gate and the drain is reduced, so that the maximum effective power gain of the FET is improved and the high frequency characteristics are improved. With the size shown in the above example, the capacitance C _gd between the gate and the source was halved as compared with the conventional example, and the maximum active power gain could be improved by about 2 dB.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor chip, which is shown in the order of steps for explaining a first embodiment of the present invention.

2A to 2C are schematic cross-sectional views of a semiconductor chip, which are shown in the order of steps for explaining an example in which a part of the first embodiment of the present invention is modified.

3A to 3C are schematic cross-sectional views of a semiconductor chip, which are shown in the order of steps for explaining a second embodiment of the present invention.

4A to 4C are schematic cross-sectional views of a semiconductor chip, which are shown in the order of steps for explaining a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 GaAs substrate 2 non-doped GaAs layer 3 n-type GaAs layer 4, 7 silicon oxide film 5 inert gas 6 damage layer 7 a side wall spacer 8 recess 9, 14 photoresist film 10 Al / Ti film 11 gate electrode 12 source electrode 13 drain electrode 15 Gate opening

Claims (2)

[Claims] 1. A step of forming a first insulating film on an operating layer formed on a semiconductor substrate and selectively forming an opening in the first insulating film to expose the surface of the operating layer. A step of irradiating the exposed surface of the operating layer with plasma to form a damaged layer, and depositing a second insulating film on the surface including the damaged layer and etching back the first insulating film in the opening. Forming a side wall spacer on the side wall of the substrate, forming a recess by isotropically etching the surface of the operating layer including the damaged layer using the first insulating film and the side wall spacer as a mask, And a step of forming a gate electrode in the recess of the opening using a spacer as a mask. 2. A step of forming a damaged layer by irradiating the surface of the operating layer with plasma using a photoresist film coated and patterned on the operating layer formed on a semiconductor substrate as a mask, and removing the photoresist film. After that, a step of forming an insulating film on the surface including the damaged layer and patterning it to form an opening for forming a gate electrode to expose the surface of the damaged layer, and including the damaged layer using the insulating film as a mask Manufacturing a semiconductor device comprising: a step of forming a recess by isotropically etching the surface of the operating layer; and a step of forming a gate electrode in the recess of the opening using the insulating film as a mask. Method.