JPH11135522A - Manufacture of compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method with good yield and good use of a low-damage dry etching method like an electron cyclotron resonance(ECR) method for a compound semiconductor device, in which characteristics, such as a threshold voltage of an FET and the like, are made uniform in plane and between wafers, and resistance of electrodes is prevented from increasing. SOLUTION: A channel layer 2 and a contact layer 3 are formed on a semiconductor substrate 1. A contact hole is patterned and an insulating film 4 is formed. The insulating film 4 is etched with a mask of a photo-resist mask 5 having an opening at a gate forming position in a reactive ion etching(RIE) method to from a gate opening 6 with a shallow bottom. The resist film is removed. Then, the gate opening 6 is drilled through in a low-damage etching method like an electron cyclotron resonance(ECR) method. A gate electrode 7, and source-drain electrodes 8 and 9 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a compound semiconductor Schottky junction field effect transistor (MESFET) or a heterojunction field effect transistor (HJFET) and formed similarly to these FETs. The present invention relates to a method for forming an electrode in an element such as a diode.

[0002]

2. Description of the Related Art In recent years, the spread of portable telephones, portable information terminals, satellite communication / broadcast receivers and the like utilizing a high frequency band of 0.5 GHz or more has been remarkable. Such devices are required to be small and have low power consumption, and compound semiconductor devices having excellent performance such as power efficiency are used. In order to achieve the designed performance in a circuit device to be mass-produced, it is indispensable that the characteristics of the mounted elements are uniform. The production of this element cannot be handled by manual adjustment of the characteristics during the process. It is necessary to control the process statistically with a high-precision processing device, that is, to increase the processing accuracy of each process. It is extremely important to employ a process that can reduce the variation in the size.

[Conventional Example 1] In a manufacturing method entitled "Method of Forming Gate Electrode" in JP-A-6-45293, which is the most common method of manufacturing a MESFET, a method shown as a conventional technique is used. Will be described first as Conventional Example 1. 12A to 12D are cross-sectional views showing a method of forming the gate electrode in the order of steps.

[0004] As shown in FIG.
A channel layer (conductive semiconductor layer) 2 made of n-type GaAs is formed on a semiconductor substrate 1 which is an As substrate by an epitaxial growth method or an ion implantation method, and an insulating film 4 made of a silicon oxide film (SiO ₂ ) is formed by a CVD method. After that, a photoresist film 5 having an opening corresponding to the gate electrode pattern is formed thereon.

Next, as shown in FIG. 12B, anisotropic dry etching by reactive ion etching (RIE) is performed on the insulating film 4 using the photoresist film 5 as a mask. Then, a gate opening 6 for exposing the surface of the channel layer 2 is formed in the insulating film 4.
For this RIE, for example, a mixed gas of CHF ₃ and O ₂ is used.

Next, as shown in FIG. 12C, the photoresist film 5 used as a mask is removed with an organic solvent or the like.

Subsequently, as shown in FIG. 12D, a metal film for forming a Schottky junction with the exposed semiconductor layer is deposited by a sputtering method or an evaporation method such as an electron gun, and this is masked with a photoresist film pattern. The gate electrode 7 is formed by dry processing by ion milling or RIE. Although not shown in FIG. 12 (d), by providing a source electrode and a drain electrode in ohmic contact with the channel layer on both sides of the gate electrode, M
An ESFET is formed.

[0008] Since RIE, which is a kind of dry etching, has an important meaning in the present invention, this principle will be described below. Refer mainly to Chapter 6, Plasma Dry Etching, especially pages 86 to 87 of "Plasma Chemistry in the Era of LSI" (issued by the Industrial Research Council).

In a glow discharge between parallel flat plates at a low gas pressure, the vicinity of the anode (anode) is in a plasma emission state of ions and electrons, but the secondary electrons emitted from the cathode remain near the cathode (cathode). The cathode is negatively charged. This is called an ion sheath, which causes a large electric field concentration due to space charge. The progress of the etching is due to the physical sputtering effect in which the cations are accelerated by this electric field and vertically collide with the film of the substrate, and the chemical reaction due to the radicals adsorbed on the surface. Although anisotropic etching is performed due to acceleration by the electric field generated by the ion sheath, damage occurs in the crystal substrate due to collision of the accelerated ions. Not only the mass but also the energy of the ion state, the energy given by the collision is large.

The voltage of the ion sheath can be monitored, and is also called a self-bias voltage or a substrate voltage. In order to increase the ion sheath voltage and increase the anisotropy, the gas pressure can be reduced, and the electrode interval can be reduced. On the other hand, when this is reversed, the self-bias voltage decreases, and damage to the crystal substrate can be reduced. However, there has been a problem that the anisotropy becomes weak and isotropic. In addition, since there is a range in gas pressure at which stable glow discharge occurs, there is also a range in the controllable ion sheath voltage.

When an opening is formed in an insulating film by RIE, the channel crystal layer is damaged by ion bombardment and the carriers near the surface are exposed if the semiconductor crystal surface is exposed under a condition of high anisotropic voltage and strong anisotropy. There are problems such as non-uniform decrease, damage that cannot be completely recovered by heat treatment, and non-uniform device characteristics such as FET, resulting in poor yield.

As a countermeasure, we conducted a verification experiment in the past under conditions of high anisotropy until the thickness of the insulating film was reduced, and the last opening of the insulating film under the condition of increasing the gas pressure and lowering the ion sheath voltage. Done. In addition, since the conductive semiconductor layer formed by ion implantation or epitaxial growth could not be controlled precisely, the thickness was adjusted by forming the semiconductor conductive layer thicker and etching the semiconductor layer from the opening while measuring the current value. At this time, the semiconductor layer on the damaged surface could be scraped off. However, this bad accuracy of productivity and device characteristics, it is also difficult to improve the performance such as the mutual conductance gm and cut-off frequency f _T in the gate length reduction and thinning.

Recently, various types of low-damage anisotropic dry etching methods using microwaves based on a principle different from the parallel plate type RIE have been proposed. As an example of these,
Reference is made to the monthly “Semi-Congector World”, March 1996, pages 19 to 24, and the above-cited pages 79 to 80. These are based on the principle of generating high-density plasma, and are based on electron cyclotron resonance (ECR).
on Resonance) method, ICP (Inductive Coupled Plasm)
a) The method is classified into the Helicon method and the like. Hereinafter, the first ECR method will be described. The ECR method is
Electrons in a magnetic field are subjected to cyclotron resonance by applying microwaves to efficiently increase the efficiency even at a low gas pressure as compared with parallel plate RIE (hereinafter, simply referred to as RIE means parallel plate RIE). A density plasma can be obtained. In this etching, the direction of ion movement can be made uniform by placing the substrate at the ECR position, and the mean free path can be extended and the anisotropy can be enhanced even at a low gas pressure.
Further, etching with low damage can be performed in a state where the ion sheath is very small.

On the other hand, with the development of compound semiconductor devices, epitaxial growth apparatuses for mass production have been developed.
It has become possible to produce a thin film layer having a high impurity concentration in VD with high accuracy and high reproducibility. Then, this provided a fine gate electrode on the conductive semiconductor layer using a high impurity concentration thin layer, it has become a challenge to produce reproducibly high gm and f _T FET.

Therefore, an attempt was made to use dry etching by the ECR method using the epitaxial semiconductor substrate manufactured by MOCVD. That is, when the opening of the SiO ₂ film, after performing in-conventional RIE to leave the SiO ₂ film of 100nm so damage does not occur, were etched by an ECR method. ECR dry etching is SiO ₂
As polymerizable above it does not occur strong polymer, CF ₄ to 3
% O ₂ at a pressure of 1 mTorr. However, when observing the inside of the opening after this etching,
As shown in FIG. 13, a reaction product 16 was generated on the GaAs crystal surface as the channel layer 2. As a result of Auger analysis, it was found that the product was a reaction product of Ga, As, and carbon as crystal components.

The reaction product remains undissolved by organic washing or dilute hydrochloric acid treatment. When such a reaction product remains in the gate Schottky electrode forming region, no forward current flows even when a Schottky electrode is formed and a forward bias is applied. Therefore, in this state, no good Schottky barrier is formed, and the gate effect cannot be obtained. As a countermeasure, when an ashing process of oxygen plasma is added, the oxidation of the semiconductor crystal proceeds in addition to the reaction product. When the reaction product is dissolved and removed with dilute hydrochloric acid, as shown in FIG. Layer scraping 17 occurs on the surface, and the surface becomes rough. Further, the channel layer becomes thin melt is oxidized, the threshold voltage V _T of the FET becomes shallow or its uniformity is impaired. Such a reaction product is also generated when SF ₆ gas containing no carbon is used. As another countermeasure, when the proportion of oxygen mixed in the ECR dry etching is increased to 10% or more, the generation of reaction products is suppressed. However, as in the case of the ashing treatment using oxygen plasma, the semiconductor crystal is oxidized. The oxide is dissolved and removed by the diluted hydrochloric acid treatment. The series of phenomena is RIE
This also occurs when the semiconductor surface is exposed under the condition that the gas pressure is increased and the ion sheath voltage is decreased.

Further, it has been confirmed that the above-mentioned phenomenon that a reaction product of a crystal component and carbon is generated occurs not only in the GaAs-based crystal but also in the InP-based crystal.

[Conventional Example 2] The "method of forming a gate electrode" described in the above-mentioned Japanese Patent Application Laid-Open No. 6-45293 discloses a method of forming a SiO ₂ film so that a channel layer is not damaged when a gate formation region is opened by RIE. Is to solve the problem that the opening is non-uniformly widened by isotropic wet etching in a conventional example in which wet etching is performed after leaving 30 nm or more, and two types of insulating films having different etching properties. It is proposed to laminate. FIG. 15 is a cross-sectional view of the prior art as a conventional example 2 in the order of steps.
This will be described with reference to (a) to (d).

As shown in FIG. 15A, the semiconductor substrate 1
On the channel layer 2 formed thereon, a silicon oxide film (S
a first insulating film 14 made of iO ₂ ) and a silicon nitride film (S
A second insulating film 15 made of iN _x ) is sequentially deposited, and a photoresist film 5 having an opening in a gate formation region is formed thereon.

Next, as shown in FIG.
RIE using mixed gas of ₃ and O _2
A gate opening 6 is provided in the _x film 15. Lower SiO ₂ film 1
4 can be left because the etching rate decreases.

Next, as shown in FIG. 15C, the lower layer of sulfuric acid is mixed with buffered hydrofluoric acid mixed with ammonium fluoride.
The iO ₂ film 14 is wet-etched to expose the surface of the channel layer 2. Since the etching rate of the upper SiN _x film 15 is low, the size of the opening can be maintained.

Next, as shown in FIG. 15D, the photoresist film 5 is removed, and a gate electrode 7 is formed. In this method, the lower SiO ₂ film 14 is formed as thin as 50 nm, so that the channel layer is not damaged and variation in the opening size is suppressed.

However, in this formation method, as shown in FIG. 16, side etching occurs in the lower SiO ₂ film 14 by wet etching, and as a result, the deposited electrode metal 18 breaks down in the side etching portion. I will.

[Conventional example 3] A method is known in which a fine gate opening is obtained and an inclined side surface is used in order to improve the connectivity of the deposited metal at the gate opening. One example is described as a conventional technique in Japanese Patent Application Laid-Open No. 63-174374, entitled "Method of Manufacturing Field-Effect Semiconductor Device". This will be described as Conventional Example 3 with reference to FIGS. 17A to 17D which are sectional views in the order of the steps.

As shown in FIG. 17A, the channel layer 2
Anisotropic dry etching is performed on the insulating film 4 formed thereon using the photoresist film 5 as a mask to form a gate opening 6.

Next, as shown in FIG. 17B, an insulating film 13 for forming a sidewall film is deposited on the entire surface. Next, FIG.
As shown in (c), anisotropic dry etching is performed to form a side wall insulating film 19 in the first opening of the insulating film and to narrow the gate opening 6a. Next, as shown in FIG. 17D, a gate electrode 7 is provided in the gate opening 6a.

When another insulating film is deposited on the vertical opening of the insulating film, the corner of the opening becomes a curved surface. When this is etched back by anisotropic dry etching, the inclined curved surface is maintained and the upper surface of the opening is maintained. A reduced opening with sloping sides can be formed.

However, as shown in FIG. 18, when the initial opening is as narrow as 0.4 μm and as deep as 0.6 μm, the thickness is 0.3 μm.
When the side wall film forming insulating film 13 having a thickness of μm is additionally grown, the upper portion becomes a shadow so that it does not enter the bottom portion, and the side surface becomes reversely inclined. When this is etched back, as shown in FIG.
The side wall insulating film 19 is formed while the side surface having the reverse inclination is maintained. In this case, since the etching includes isotropic rather than complete anisotropy, the etching is performed in the lateral direction even at the bottom. When the electrode metal 18 is vapor-deposited in such an opening shape, as shown in FIG. 20, since the upper portion becomes a shadow and almost no vapor-deposited metal enters the inside of the opening, the metal on the side surface becomes thinner and the series resistance of the electrode increases.

[0029]

SUMMARY OF THE INVENTION Accordingly, the first object of the present invention is to provide a reaction product between a crystal component and carbon when a crystal surface of a compound semiconductor is exposed by dry-etching an insulating film. Is that good Schottky barriers are not formed. Further, the addition of oxygen plasma or the like as a countermeasure, crystals because they are cut crystals melts with acid treatment after being oxidized, by the threshold voltage V _T of the FET becomes shallow and its uniformity is impaired is there.

The second problem is that, when an electrode is formed in a finely formed opening, the electrode metal deposited in the opening hardly adheres to the side surface, and becomes thinner, so that the series resistance of the electrode increases or the wire breaks. Or to do.

The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to draw out the performance of low-damage dry etching such as an ECR method and to achieve the threshold voltage V _{T of} an FET. And the like can be made uniform within a plane and between wafers, the increase in resistance of fine electrodes can be suppressed, and the productivity of these elements can be increased.

[0032]

According to the present invention, there is provided a semiconductor device comprising: a first step of forming an element semiconductor layer on a surface of a compound semiconductor substrate; and forming an insulating film on the element semiconductor layer. A second step of applying a photoresist,
A third step of performing exposure and development to form a photoresist film having an opening on an electrode formation region of the element semiconductor layer, and etching the insulating film halfway by dry etching using the photoresist film as a mask. A fourth step of forming an opening at the bottom where the insulating film is left, a fifth step of removing the photoresist film, and a partial surface of the element semiconductor layer by etching the entire surface of the insulating film by a dry etching method And a seventh step of forming an electrode in contact with the element semiconductor layer through an opening formed in the insulating film, thereby obtaining a compound semiconductor device. .

In the method of manufacturing a semiconductor device according to the present invention, preferably, the fourth step is a step of forming an opening having a side wall surface perpendicular to the insulating film by etching under a highly anisotropic condition. And a second etching step in which after the first etching step, the photoresist film is laterally etched and a slope is formed above an opening formed in the insulating film. .

In the method of manufacturing a compound semiconductor device according to the present invention, more preferably, the second etching step includes adding oxygen to an etching gas, increasing a gas pressure in an etching chamber, and using a chlorine-based gas. And using a mixed gas containing a chlorine-based gas.

Further, according to the present invention, a first step of forming an element semiconductor layer including an etching stop layer on the surface of a compound semiconductor substrate, and a second step of forming an insulating film on the element semiconductor layer A third step of applying a photoresist, performing exposure and development to form a photoresist film having an opening on an electrode formation region of the element semiconductor layer, and a dry etching method using the photoresist film as a mask,
A first etching step in which the insulating film is partially etched to leave the insulating film at the bottom, and after the first etching step, the photoresist film is laterally etched and formed on the insulating film. A fourth step including a second etching step of forming an opening by forming a slope by providing a slope on the top of the opening and etching the bottom insulating film.
A fifth step of removing the photoresist film, a sixth step of etching the element semiconductor layer from the opening formed in the insulating film to the etching stop layer to dig the opening, and an insulating film for forming a sidewall film A step of forming a sidewall insulating film on the side surface of the opening formed in the insulating film and the element semiconductor layer by performing anisotropic etching, and exposing through the opening formed by the sidewall insulating film. Forming an electrode in contact with the element semiconductor layer thus formed.

Here, in the method of manufacturing a compound semiconductor device according to the present invention, preferably, the second etching step includes any one of adding oxygen to an etching gas and increasing a gas pressure in an etching chamber. It is performed using or.

Further, in the method of manufacturing a compound semiconductor device according to the present invention, preferably, a ninth step of exposing the exposed element semiconductor layer by etching is provided between the seventh step and the eighth step. Is to have more.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing embodiments of the present invention, the principle of the present invention will be described in more detail.

First, an opening is formed in an insulating film by dry etching such as ECR using a fluorine-based gas using a photoresist film pattern as a mask to expose a crystal surface of a compound semiconductor such as GaAs or InP. The problem was that the reaction product of the component and carbon covered the crystal plane, but as a result of investigation, it was found that the supply source of this carbon was mainly a photoresist film provided on the upper part. Then, it is considered that the crystal face is exposed and the semiconductor crystal activated by the fluorine radical causes a strong bonding reaction with carbon rather than fluorine. In addition, lowering the ion sheath voltage and weakening the physical sputtering effect in order to reduce damage to the crystal surface also causes a reaction product to remain.

Therefore, in the present invention, after removing the photoresist film serving as a carbon source, the carbon-free SF ₆ or NF ₃ is left in a state where the insulating film is left at the bottom of the opening of the insulating film.
Etch back with a fluorine-based gas such as to expose the crystal plane of the compound semiconductor.

Elements other than carbon, such as S, N, and F, do not strongly react with the compound semiconductor, and can be easily removed only by dissolving a few nm of crystals by dilute acid treatment. For GaAs, hydrochloric acid can be used in a 36% stock solution, but diluting with pure water improves permeation into fine openings. Since the stock solution of phosphoric acid has a very high viscosity of 85%, it is desirable to dilute it to 10% or less. Sulfuric acid is unsuitable for dissolving GaAs. On the other hand, for InP, since hydrochloric acid dissolves crystals, it is desirable to use a solution obtained by diluting phosphoric acid or sulfuric acid to 10% or less. It is also possible to perform an alkali treatment diluted on the entire compound semiconductor. For this purpose, for example, ammonia NH ₄ OH, ammonium fluoride NH ₄ F, and ammonium sulfide (NH ₄ ) ₂ S can be used.

It is to be noted that a gas such as CF ₄ containing carbon contains oxygen O
_{Although the} use of a gas to which ₂ is added as an etching gas suppresses the formation of a reaction product of carbon, it is inappropriate because the compound semiconductor surface is oxidized and melted and removed by an acid treatment afterwards. In addition, CCl ₂ F ₂ containing chlorine or CCl ₄
Is also unsuitable for etching GaAs or InP of a compound semiconductor.

Further, according to the embodiment of the present invention, a slope can be provided on the side surface of the insulating film opening. That is, after the insulating film is etched to about half by RIE with strong anisotropy using the photoresist film as a mask, the insulating film is etched while the opening of the photoresist film is retreated in the lateral direction. By etching the film, a slope is formed on the side surface of the opening.

The method of retreating the photoresist film in the lateral direction includes adding oxygen to the fluorine-based gas, increasing the pressure with the fluorine-based gas, using a chlorine-based gas, or adding a fluorine-based gas to the chlorine-based gas. It is possible to use a mixture of gases. Although the top of the insulating film is inclined by the receding photoresist, the first RI
Even if the upper photoresist is lost, the groove formed by E retains its shape due to the anisotropy of etching and is transferred to the lower part of the opening. The first method of adding oxygen can keep the etching gas pressure low, easily secure anisotropy, and is the most stable. The second method for increasing the etching gas pressure is effective when oxygen cannot be introduced.

As described in the prior art, since the etching becomes more isotropic, the etching in the lateral direction proceeds. Third
Is easy to etch the photoresist and tends to be isotropic. Therefore, it is effective to mix fluorine-based gas to weaken the effect of chlorine.

According to the above-described method of retreating the photoresist film from the middle of the etching, it is possible to form a slope on the side surface of the upper portion of the opening. Thus, it is possible to prevent the electrode metal from being broken and the resistance value from increasing.

Now, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a cross-sectional view in the middle of manufacturing which is common to the first to fourth embodiments of the present invention, and FIG. 2 is a sectional view of the first to fourth embodiments. FIG. 13 is a layout pattern diagram common to these embodiments for describing the embodiment. FIG. 1 is a cross-sectional view taken along line AA ′ of FIG.

First, as shown in FIG.
The MOCVD method (Metal
Organic Chemical Vapor Deposition) or MBE
A crystal layer is grown by a method (Molecular Beam Epitaxy). That is, i-type GaAs has a thickness of 500 nm as the buffer layer 11 and a carrier concentration of 2.
0 × 10 ¹⁸ cm ⁻³ n-type Al _0.3 Ga _0.7 As
0 nm, the carrier concentration of the contact layer 3 is 4.0 ×
An n-type GaAs of 10 ¹⁸ cm ^-3 is sequentially grown to a thickness of 100 nm. Note that the buffer layer 11 is omitted in drawings other than FIG.

The management of the channel layer 2 is performed as follows. After taking out the substrate from the growth apparatus without growing the contact layer in a state where the channel layer has been grown, aluminum Al is immediately deposited and patterned into a predetermined shape to form a Schottky electrode. An ohmic electrode formed by alloying indium In is formed close to the electrode, and the distribution characteristic of the carrier concentration is obtained from the relationship between the applied voltage and the capacitance (that is, CV characteristic). Check. The management specification of the channel layer in the CV characteristics is that the concentration of the doped carrier at an applied voltage of 0 V and the accuracy thereof are ± 10% at 2 × 10 ¹⁸ cm ⁻³ , and the carrier concentration is 1 × 10 ¹⁶ cm ⁻³ . The pinch-off voltage is -1.3 ± 0.20V. Incidentally, after making FET, although the accuracy of the threshold voltage V _T can manage by a ± 0.15V, the accuracy for the management method described above using the measurement method of simple capacitance lower ing.
Note that 2 ± was used as the ± value of each precision. σ is the standard deviation.

Further, regarding the growth film thickness, the buffer layer is made i
X-type GaAs and i-type AlGaAs are repeatedly laminated.
The average repetition film thickness can be inspected by the line measurement. For example, each layer is grown for 10 cycles of 20 nm using a rotation-revolution type MOCVD, and one cycle (40 nm) is formed.
The accuracy of the film thickness per minute can be ± 2 nm.

Next, a semiconductor device is manufactured by processing the epitaxially grown semiconductor substrate by utilizing photolithography technology. The process of forming the FET will be briefly described with reference to the layout diagram shown in FIG. First, a photoresist film covering an active region having a pattern opposite to that of the element isolation region 21 is provided, and element isolation is performed by ion implantation. That is, ¹¹ B ⁺ ions are converted to an acceleration energy of 200 ke.
Ion implantation is performed under the conditions of V and an implantation dose of 1 × 10 ¹³ cm ⁻² to cause defects in the element isolation region 21 and increase the resistance. Next, a photoresist film covering the contact region 22 is formed, and the contact layer 3 is processed (see FIG. 1). Next, an insulating film covering the entire surface is provided, and the gate opening 23 is formed.
A gate opening 23 is formed by providing a photoresist film having the opening pattern described above and etching the insulating film. Next, an electrode metal is deposited and processed into a pattern of the gate electrode 24. Next, a photoresist film having an opening in the pattern of the ohmic electrodes 25 and 26 is formed to open an insulating film, and the ohmic metal is lifted off using the photoresist film to form a source electrode (25) and a drain electrode. By forming (26), the FET forming process is completed. The gate opening 2
3 is closer to the source side.

Next, the steps of the present embodiment after the production of the epitaxial growth substrate will be described with reference to FIGS.
This will be described in more detail with reference to FIGS. 3A to 3D, which are cross-sectional views in the order of steps along the line A ′.

As shown in FIG. 1, a photoresist film 12 corresponding to the contact region 22 shown in FIG. 2 is provided, and the contact layer 3 is dry-etched. Using an ECR apparatus, BCl ₃ was 15 sccm and SF ₆ was 5 sccm (2 sccm).
5%) at a pressure of 1 mTorr. When the lower channel layer 2 is exposed, the etching is stopped because aluminum fluoride AlF _x covers the surface. The etching selectivity between GaAs and AlGaAs is 100
More than double. When the photoresist film 12 is removed with an organic solvent and immersed in diluted hydrochloric acid for several minutes, the fluorinated layer is removed. Note that the organic washing is performed by applying ultrasonic waves, performing several times with methyl ethyl ketone and then isopropanol, and drying. The diluted hydrochloric acid is a 20 ° C. liquid obtained by mixing 36% concentrated hydrochloric acid and pure water at a ratio of 1: 1.

Under the GaAs etching conditions, the photoresist film is used as a mask, but the reaction product of carbon does not matter. This is probably because the etching ratio between GaAs and the photoresist is as large as about 50 times, and the etching of the photoresist is small. Further, since the etching rate of GaAs is high, the etching power is small, the photoresist is not hardened, and it can be easily removed with an organic solvent.

Next, as shown in FIG.
Then, a silicon oxide film SiO ₂ is deposited to a thickness of 700 nm, and a photoresist film 5 having an opening corresponding to the gate opening 23 in FIG. 2 is provided. The thickness is about 1 μm, and the width of the opening is 1.0 μm. An antireflection film is inserted under the photoresist film 5 to increase the exposure accuracy of the stepper.
A WSi film can be used as the anti-reflection film. Using the photoresist film as a mask, the insulating film film 4 is etched by a parallel plate type RIE apparatus until the remaining film thickness becomes about 100 nm, thereby forming a gate opening 6 partially leaving the insulating film at the bottom. The conditions are a mixed gas of CF ₄ and H ₂ at a flow rate of 20%, a gas pressure of 80 mTorr, and an ion sheath voltage of 70 V.

Next, as shown in FIG. 3B, the photoresist film 5 is ashed and removed with oxygen plasma, and organic cleaning is performed. Thereafter, as shown in FIG. 3C, the insulating film 4 is etched by 150 nm by ECR dry etching.
The gate opening 6 penetrates to the channel layer 2. The etching conditions were SF ₆ gas, a pressure of 1 mTorr, an ion sheath voltage of 2 V or less, and an SiO ₂ etching rate of 36.
nm / min.

[0058] Thereafter, a thickness of 200nm to WSi _x as a Schottky metal 10 performs diluted hydrochloric acid treatment and organic cleaning
Is deposited by sputtering. By separating the semiconductor substrate from the sputter target to some extent, for example, 15 cm or more, the influence of electrons and ions existing near the target can be suppressed. Thereafter, heat treatment is performed at 400 ° C. for 30 minutes in a hydrogen atmosphere to recover the light damage. Again, for the purpose of lowering the resistance, 30 nm thick Ti and 600 nm thick Au are deposited by sputtering.

Next, as shown in FIG. 3D, the gate electrode 7 is formed by ion milling with the pattern of the gate electrode 24 of FIG. Further, the ohmic electrode 2 of FIG.
The insulating film 4 is opened with buffered hydrofluoric acid in patterns 5 and 26, AuGeNi as an ohmic metal is deposited, lifted off, and then alloyed by heat treatment to form a source electrode 8.
And a drain electrode 9 are formed.

Approximately 8 for a 76 mm (3 inch) diameter wafer
Zero prototypes were produced. The threshold voltage V _T of the obtained FET is M
-0.9 including between OCVD growth batches and within the wafer
2 ± 0.15V (2σ), maximum transconductance g
m was 360 mS / mm on average. The standard deviation σ in the wafer surface of the V _T was 30～50MV. According to the TEM observation after the device formation, the shaving of the channel layer 2 was about 3 nm by etching the contact layer 3 and about 3 nm by forming the opening of the insulating film 4. 6 for an initial thickness of 40 nm
nm is shaved off, leaving 34 nm. Since V _T of about 100mV to changes in the membrane channel thickness in V _T near thickness 1nm changes correspond, overall thickness accuracy than the measurement results can be estimated to be ± 1.5 nm.

As a comparative experiment, the SiO 2 in the first RIE was
_{2 When the} remaining film thickness is reduced from 100 nm, 50 nm
Becomes below V _T becomes shallow changed to the positive side, the uniformity in the wafer surface is reduced. If the opening is made without leaving the SiO ₂ film, the channel layer will be damaged and the carriers will disappear, resulting in complete non-conduction. This damage
The heat treatment at 400 ° C. failed to recover.

Therefore, the remaining film thickness of the SiO ₂ film in the first RIE needs to be 50 nm or more at which damage starts to appear, but in the present embodiment, it is twice as large in consideration of the etching accuracy of the RIE. It was set to 100 nm.

As a second comparative experiment, SiO 2
_{(2) The} remaining film was set to 100 nm, and the remaining film was etched by ECR method while the photoresist film was left. 150~300nm the SiO ₂ film etching amount
After removing the photoresist film by organic washing, a diluted hydrochloric acid treatment was performed to form each electrode in the same manner as in the first embodiment. In the voltage-current characteristics in the gate forward direction in the wafer surface, current did not easily flow (close to a non-conductive state) and was non-uniform. Regarding the characteristics of the gate voltage and the drain current, in many cases, the drain did not substantially change because the gate did not function properly. In addition, SiO
_This is because the reaction product of carbon remains at the gate electrode interface almost without depending on the etching amount of the _two films.

As a third comparative experiment, this ECR
After the etching by the method, oxygen plasma was added by a cylindrical device, the photoresist film was removed by organic washing, and a diluted hydrochloric acid treatment was performed to similarly form each electrode. The gate conduction characteristics with forward bias were improved by the oxygen plasma treatment for 10 minutes, but non-conductive samples remained. When the treatment was performed for 30 minutes, the gate non-conduction was eliminated, and the characteristics became uniform. However, the threshold voltage V _T is -0.6 ± 0.
It became shallow to 2 V, and the σ value in the wafer surface also increased to 40 to 80 mV. It is considered that the surface was oxidized non-uniformly by the oxygen plasma, and was melted and cut by the acid treatment.

As a fourth comparative experiment, the influence of over-etching of the SiO ₂ film by the ECR method in the present embodiment was examined. The etching rate in an opening having an opening width of 1.0 μm is about 5% smaller than 36 nm / min in a plane. The etching amount of the SiO ₂ film in the plane is 150, 200, 25 for about 100 nm of the SiO ₂ film left in the opening.
0 and 300 nm. The average V _T / σ value when five wafers were each prototyped was -936/42 mV,-
928 / 39mV, -851 / 47mV, -683/6
It became 2 mV. The ECR overetching is believed that the damage to the channel crystal layer, effective in V _T of both scraping crystals by subsequent acid treatment has become shallow uneven. Even in the case of using the ECR method, which is said to be low damage, if the over-etching is large, an adverse effect occurs.

(Second Embodiment) As a fifth comparative experiment, the final etching of the insulating film 4 was performed by a parallel plate type RIE instead of the ECR method. The conditions are 150 for SF ₆ gas.
The gas pressure was increased to mTorr, the high-frequency power was brought close to the minimum at which plasma was generated, and the ion sheath voltage was reduced to 20V. The etching rate of the SiO ₂ film is 4 nm / min.
The etching amount of the SiO ₂ film in the plane is 150, 200, ₂
It was changed to 50 nm. The value of the average V _T / sigma when the prototype of each 5 wafers, -927 / 46mV, -78
4/65 mV and -259/143 mV. ECR
V compared to SiO ₂ film overetching
_T becomes shallower and the uniformity becomes faster and worse. This is because the ECR method has lower damage. However, even in the case of RIE, if the ion sheath voltage is reduced and over-etching is reduced, it is possible to use the RIE with a small margin.

(Third Embodiment) An example in which the method of narrowing the gate opening with the side wall insulating film and inclining the upper part of the opening as described in Conventional Example 3 is applied to the present invention will be described. FIGS. 4A to 4D are process cross-sectional views for explaining a third embodiment of the present invention. Steps until a photoresist film having an opening is provided are the same as those in the first embodiment, and FIG. 4A corresponds to FIG. 3B.

As shown in FIG. 4A, a silicon oxide film is deposited as an insulating film 4 to a thickness of 700 nm, and a 1 μm thick photoresist film 5 having a 1.0 μm wide opening is provided thereon. Insulating film 4 by a parallel plate type RIE device
Is etched until the remaining film thickness becomes about 100 nm, thereby forming a gate opening 6 partially leaving an insulating film at the bottom. Next, as shown in FIG. 4B, the photoresist film 5 is removed, and SiO ₂ having a thickness of 3 is formed as an insulating film 13 for forming a side wall film.
Deposit at 00 nm.

Next, as shown in FIG. 4C, the entire surface is etched by RIE until about 100 nm of the insulating film 4 is left to form a side wall insulating film 19. Subsequently, the insulating film 4 is etched by 200 nm by ECR dry etching,
The gate opening 6a is penetrated to reach the channel layer 2.
At this time, the gate opening 6a is formed to be narrowed by the side wall insulating film 19. The lateral dimension of the gate opening bottom is the gate length, in this case 0.6 μm. If a sidewall insulating film having a thickness equal to the plane thickness is simply formed, the gate length should be 0.4 μm. This is caused by etching in the lateral direction.

Next, as shown in FIG. 4D, each electrode is formed in the same manner as in the first embodiment, and the fabrication process of the FET is completed.

By using the sidewall insulating film, the gate opening is reduced, and at the same time, a curved surface is formed by the sidewall insulating film above the gate opening, so that the burying property of the gate metal is improved. The threshold voltage V _T of the obtained FET is −0.98 ± 0.1 including between MOCVD growth batches and within a wafer.
At 5 V (2σ), the maximum transconductance gm averaged 420 mS / mm. The standard deviation σ in the wafer surface of the V _T was 30～50MV. Exemplary gate length as compared with the example of the first is the V _T the short channel effect is shortened from 1.0μm to 0.6μm have improved Deeper simultaneously gm is.

(Fourth Embodiment) An example in which the connectivity of a fine electrode is improved without using a sidewall insulating film will be described. FIGS. 5A to 5D are process cross-sectional views for explaining a fourth embodiment of the present invention.

The steps up to the provision of the insulating film are the same as those in the first embodiment, and FIG. 5A corresponds to FIG. 3B.
As shown in FIG. 5A, the insulating film 4 has a thickness of 700 n.
After the m-th silicon oxide film is deposited, a photoresist film 5 having a thickness of about 1 μm and a short opening having a width of 0.4 μm is provided thereon. An antireflection film is inserted under the photoresist film 5 in order to improve the exposure accuracy of the stepper. Using this photoresist film as a mask,
The gate opening 6 is formed by etching the insulating film 4 by RIE until half of the insulating film 4 remains about 300 nm. Conditions is carried out at a gas pressure of 80mTorr used and H ₂ of CF ₄ and flow rate of 20%. Next, as shown in FIG. 5 (b), an ECR method dry etching, oxygen O ₂ 6sc the CF ₄ 14 sccm
Etching is performed at a pressure of 1 mTorr with a gas mixed with a concentration of 30 cm (30%), and the insulating film 4 in the gate opening 6 is formed by about 50 mTorr.
Thin to nm. At this time, the photoresist film 5 is etched and its opening widens in the lateral direction, but at the same time, an inclination occurs above the gate opening of the insulating film 4. However, the opening shape provided by the first RIE is transferred to the lower portion of the opening as it is by etching back even if the photoresist film is not present on the upper portion. However, since the ECR dry etching has low anisotropy under low damage conditions, the lateral dimension of the bottom is 0.5 μm.
And spread. The lateral dimension of the upper part of the inclined gate opening 6 is about 1.2 μm.

Next, as shown in FIG. 5C, the photoresist film 5 is ashed and removed by oxygen plasma, and organic cleaning is performed. Then, the insulating film 4 is subjected to ECR dry etching using SF ₆ gas. Is etched by 100 nm to expose the surface of the channel layer 2 from the gate opening 6. Next, FIG.
As shown in (1), each electrode is formed in the same manner as in the first embodiment, and the manufacturing process of the FET is completed.

A slope is formed above the gate opening due to the retreat of the photoresist in the lateral direction, thereby improving the burying property of the gate metal. Further, since the etching is performed by the ECR method which is less damaged than RIE, the thickness can be reduced to just before the crystal plane is exposed. Rather, based on the uniformity of film formation and the etching uniformity of the RIE and ECR methods, it is possible to determine the film thickness to be left without exposing the crystal plane. In the above embodiment, since the film is thin around the wafer and the etching is fast, the remaining film thickness at the center is 50n.
m. Therefore, the amount of etch back after the removal of the photoresist film can be reduced. Further, since the upper portion of the opening is inclined and widened, the etching rate at the bottom of the opening does not decrease much.

The threshold voltage V _T of the obtained FET is expressed as MO
-1.03 including between CVD growth batches and within the wafer
At ± 0.15 V (2σ), the maximum transconductance gm was 440 mS / mm on average. The standard deviation σ in the wafer surface of the V _T was 30～60MV. First and third
Since that is the shorter gate length as compared to the example of the embodiment, although V _T in the short channel effect becomes deeper, uniformity and reproducibility itself is the same as that in the case of the other embodiments.

(Fifth Embodiment) A description will be given of the case where the backward etching in the lateral direction is performed not by the ECR method but by increasing the etching gas pressure by RIE. The condition is CF
_The gas pressure was increased to 150 mTorr with _four gases, and the ion sheath voltage was reduced to 40 V. The etching rate of the SiO ₂ film is 18 nm / min. The process is performed until the insulating film 4 on the bottom of the gate opening is left at 100 nm. In this case, the lateral dimension of the bottom widened to about 0.6 μm. The size of the opening above the opening was about 1.2 μm, and a slope could be formed above the opening.

(Sixth Embodiment) A gas for etching a photoresist film in a lateral direction is an insulating film (SiO 2) because the etching does not expose a semiconductor crystal.
It can be almost used if it can etch ₂ ). In the fluorine type, SF ₆ or NF ₃ can be used, and oxygen can be further added. If the chlorine-based gas has an etching rate of the insulating film close to that of the photoresist,
Since it is smaller than this and tends to be isotropically etched, it can be used. However, when the proportion of chlorine is increased, it becomes difficult to control the etching of the photoresist. Therefore, the shape can be adjusted by mixing a fluorine-based gas or the like with the photoresist. For example, BCl ₃ and CF ₄ are mixed at a ratio of 1: 2.

(Seventh Embodiment) An example in which the connectivity to the fine electrode is improved by the lateral retreat of the photoresist film opening and the side wall insulating film will be described. 6 (a) to 6 (d)
FIG. 19 is a process sectional view for describing the seventh embodiment of the present invention.

FIG. 6A is the same as FIG. 5A until the insulating film is provided with an opening and an upper portion provided with a slope.
(B). As shown in FIG. 6A, a silicon oxide film having a thickness of 700 nm is deposited as the insulating film 4,
A photoresist film 5 having a thickness of about 1 μm and an opening having an opening width of 0.4 is formed thereon. An antireflection film is inserted under the photoresist film 5 in order to improve the exposure accuracy of the stepper. Thereafter, the insulating film 4 is etched by RIE until half of the insulating film 4 remains about 300 nm. Next, CF ₄ and 3
The insulating film 4 at the bottom of the opening is thinned to about 50 nm by ECR dry etching using a mixed gas containing 0% oxygen O ₂ as an etching gas, and at the same time, an inclination is generated at the upper portion of the opening of the insulating film 4. The lateral dimension of the bottom of the formed gate opening 6 extends to 0.5 μm.

Next, as shown in FIG. 6B, the photoresist film 5 is ash-removed by oxygen plasma and organic cleaning is performed, and then SiO ₂ having a thickness of 3 is formed as an insulating film 13 for forming a sidewall film.
Deposit at 00 nm. With this film formation, the lateral dimension of the bottom of the opening is 0.1 μm. The thickness of the insulating film at the bottom of the opening is smaller than that of the plane portion.

Next, as shown in FIG. 6C, the SiO _{2 at the} bottom of the opening was formed by RIE using CF ₄ gas and H ₂ gas.
Etch until the film remains about 100 nm. The flat portion is etched by 200 nm, and the inside of the opening is fine, so that the etching rate is reduced. Subsequently, the insulating film 4 is etched to a thickness of 200 nm in a flat portion using SF ₆ gas by ECR dry etching to expose the channel layer 2 from the gate opening 6a. Lateral dimension as gate length at bottom of opening is 0.2μ
m.

Next, as shown in FIG. 6D, each electrode is formed in the same manner as in the first embodiment, and the fabrication process of the FET is completed. Above the gate opening 6a, the photoresist recedes in the horizontal direction and the sidewall insulating film is inclined to improve the burying property of the gate metal.

The threshold voltage VT of the obtained FET is MOC
-1.20 ± including VD growth batch and within wafer
At 0.20 V (2σ), the maximum transconductance gm was 480 mS / mm on average. The standard deviation σ of the wafer surface in V _T was 50～9OmV. The gate length as compared with the example of other embodiments is short and 0.2 [mu] m, V _T in the short channel effect becomes deeper, uniformity and reproducibility are a little worse than the other examples .

(Eighth Embodiment) In the above embodiments, a one-stage recess gate structure in which a gate is provided on a flat bottom surface of a recess in which an element semiconductor layer is dug has been described. The feature of this structure is that the withstand voltage such as the drain withstand voltage and the gate reverse withstand voltage of the FET can be increased. Used for high output or when surge voltage is required. The present invention
The present invention is not limited to the step recess gate structure. The above embodiments are also effective for a two-stage recess buried gate structure in which a semiconductor element layer is further dug from an insulating film opening before a gate electrode is formed. This manufacturing method is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2-105540, “Method for manufacturing semiconductor device”.
The title is disclosed.

The feature of the two-stage recess buried gate structure is that the influence of the surface depletion layer extending from the surface of the semiconductor layer can be eliminated by embedding the gate in the semiconductor layer. In the one-stage recess gate structure, the surface depletion layer extending beside the gate functions to increase the breakdown voltage. Since the charge state of the surface level of the semiconductor surface related to the surface depletion layer varies with the FET operating condition, the waveform becomes dull in steep pulse amplification, and the analog amplification varies on the low frequency side. was there. In the single-stage recess gate structure, the high-frequency band is limited, and there is no problem unless the bias state of the circuit is changed. By burying the gate in the semiconductor layer with a two-stage recess buried gate structure, the gate depletion layer is made deeper than the surface depletion layer to increase the degree of amplification as the controllability of channel current, and the response and frequency dependence of pulse amplification are also improved. Improved and wider band is possible. However, in exchange for these effects,
There are lowering of the drain withstand voltage, lowering of cutoff frequency as high frequency characteristics due to increase of gate capacitance, and the like. Therefore, F
The design is to adjust each FET functional characteristic by the depth of the second recess and the structural element according to the required performance of the ET.

According to the present invention, contamination and crystal shaving before the second recess is provided are small, so that the second recess can be formed with high accuracy. FIGS. 7A to 7C are process cross-sectional views for explaining an eighth embodiment of the present invention. FIG. 7A shows FIG. 3C of the first embodiment, FIG. 4C of the third embodiment, and FIG. 5 of the fourth embodiment.
(C) corresponds to FIG. 6 (c) of the seventh embodiment. However, in the formation of the crystal layer of the epitaxial semiconductor substrate described in the first embodiment, the thickness of the n-type Al _0.3 Ga _0.7 As as the channel layer 2 is set to 50 n instead of 40 nm.
m and 10 nm corresponding to the second recess depth.

In FIG. 7A, the SiO ₂ film 4 is etched back without a photoresist film, and the n-type AlGaAs channel layer 2 exposed from the gate opening 6 or 6a.
Has been purified by organic washing and dilute hydrochloric acid treatment. Note that S
The gate length of the iO ₂ film opening was set to 0.4 μm.

As shown in FIG. 7B, the n-type AlGaAs channel layer 2 is dug by about 10 nm by wet etching to provide a second recess 27.

Two methods will be described as wet etching. The first method is to repeat the A solution for crystal oxidation and the B solution for oxide layer removal. Solution A is a hydrogen peroxide solution (31 wt.
%): Water = 1: 50 dilution at a temperature of 20 ° C. Solution B is diluted with hydrochloric acid (36 wt%): water = 1: 5 and at a temperature of 20 ° C. The temperature of the liquid tank is close to room temperature for better management.

After the wafer set in the Teflon case is washed with water for 1 minute, it is immersed in the solution A for 1 minute, and the crystal surface is oxidized (hydroxylated) with a hydrogen peroxide solution, followed by shower water washing.
Crushed in liquid B for 1 minute to remove the crystal oxide layer with dilute hydrochloric acid, and in a series of steps of shower water washing 2 minutes, a 2.3 nm crystal was shaved. By repeating this step four times, about 10 nm was shaved. . To measure the actual etching rate, this process is repeated ten times or more, and the cross section of the sample is scanned with a scanning electron microscope (SE).
Observed in M), the digging depth was measured and divided by the number of times to obtain an average value.

The second method is to perform wet etching while rotating a wafer. The solution is phosphoric acid (85wt
%): Aqueous hydrogen peroxide (31 wt%): water = 4: 1: 20
0 and the temperature is 20 ° C. The back surface of the wafer is stopped with a vacuum chuck, the wafer is placed horizontally, pure water is raised on the wafer, and the wafer is rotated at a low speed of 20 rpm. At the same time, pure water is applied to the center of the wafer for 10 seconds.
Stop the pure water and apply the etchant to the center of the wafer at the same time.
Etch for 23 seconds. At the same time as the etching solution is stopped, pure water is applied and washing is performed for 60 seconds. The pure water is stopped, the number of rotations of the wafer is increased to 200 rpm, and the wafer is centrifugally dried for 30 seconds.

By using such a fresh etching solution and instantaneously switching the solution, the etching amount can be considerably controlled. The actual measurement of the etching rate was obtained by changing the etching time, observing the cross section of the sample by SEM, and measuring the digging depth. This etching rate is 2
6 nm / min.

As shown in FIG. 7C, each electrode is formed in the same manner as in the previous embodiments, starting with the step of diluting hydrochloric acid and sputter depositing WSi as the Schottky metal 10. The gate electrode 7 is the second recess 2
7 embedded. The second recess is shallow and has little side etching, and metal is wrapped around and embedded by sputter deposition. Further, when the second recess becomes deep, side etching occurs, and as described in the conventional example 2 (FIG. 16), the metal is disconnected. For this reason, it is our experience that the depth of the second recess is desirably 50 nm or less.

Each second recess method has a diameter of 76 m.
30 m wafers were prototyped. The method according to the first alternating two liquids carried by shifting the timing for every five wafers, the gate threshold voltage V _T of the FET -0.96 ± 0.18 V (2
σ), the σ value in the wafer plane was 30 to 60 mV.

The second method using the wafer rotation is the wafer 10
Performed by shifting the timing for each sheet, V _T is -0.98 ± 0.2
1V (2σ), the σ value in the wafer plane is 40 to 80 mV
In, there was a tendency that the V _T of the wafer center becomes shallow.

In the first method, the in-plane σ value is close to 30 to 50 mV in the embodiment in which the second recess is not provided, and the rate control of wet oxidation is used. It is maintained and the wafer surface is substantially uniformly etched.

In the second method, since the etching solution is applied to the center of the wafer, the etching at the center tends to be large.
However, since the scraping crystalline due to the reduction or oxygen plasma treatment of etching by contamination effects a crystal surface of the present invention is suppressed, the 1, ± of the third and 4 V _T distribution of embodiment and the like of There is no extreme increase compared to 0.15 V (2σ), and it can be confirmed that the wet etching is performed almost uniformly and the second recess is formed with good reproducibility.

(Ninth Embodiment) In the present embodiment,
JP-A-63-174 cited for describing the prior art 3.
The method of the present invention is applied to an opening forming step disclosed in "Method of Manufacturing Field-Effect Semiconductor Device" of Japanese Patent No. 374. The feature of the method disclosed in this publication is that a crystal is side-etched from the opening of the insulating film to form a recess, a sidewall insulating film is formed inside the recess, and then self-aligned from the side face of the crystal by the sidewall insulating film. Is to form a gate electrode which is separated from each other. In this manufacturing method, the method of the present invention is applied to the first step of forming an opening in an insulating film. FIG.
(A)-(f) is process sectional drawing for demonstrating 9th Embodiment of this invention.

The epitaxial growth substrate used is the same as that described in the first embodiment. However, the processing of the contact crystal layer using the photolithography method described in the first embodiment is not performed. On the other hand, element isolation by B ⁺ ion implantation is performed.

As shown in FIG. 8A, a silicon oxide film having a thickness of 700 nm is deposited as an insulating film 4 on an epitaxially grown substrate having undergone element isolation, and an opening having an opening width of 0.4 μm is formed thereon. Is formed with a photoresist film 5 having a thickness of about 1 μm. Under the photoresist film 5,
An antireflection film is inserted to improve the exposure accuracy of the stepper. Thereafter, as in the fourth embodiment, a gate opening 6 having an inclined portion is formed in the insulating film 4 (FIG. 8A corresponds to FIG. 5B). That is, an opening is formed halfway by RIE using CF ₄ and H _2, and the insulating film 4 on the bottom of the opening is reduced to about 50 nm by ECR dry etching using a mixed gas containing CF ₄ and 30% oxygen O _2. At the same time as the thickness is reduced, a slope is provided above the gate opening 6. At this time, the lateral dimension of the opening bottom spreads to 0.5 μm.

Next, as shown in FIG. 8B, the photoresist film 5 is ashed and removed by oxygen plasma, organic cleaning is performed, and then the insulating film 4 is subjected to ECR dry etching using SF ₆ gas. Is etched by 100 nm to expose the contact layer 3 from the gate opening 6. After that, the semiconductor crystal surface is purified with organic washing and diluted hydrochloric acid.

Next, as shown in FIG. 8C, the contact layer (n-type GaAs layer) 3 is formed by ECR dry etching.
Is etched. As described in the first embodiment, the conditions are set at a pressure of 1 mTorr using a gas obtained by mixing 25% SF ₆ with BCl ₃ . A of lower channel layer 2
Aluminum fluoride Al when lGaAs is exposed
F _x is an etching for covering the surface to stop. After the organic washing, it is immersed in diluted hydrochloric acid for several minutes to remove the fluorinated layer.

Next, as shown in FIG. 8D, SiO ₂ is deposited to a thickness of 300 nm as an insulating film 13 for forming a side wall film. With this film formation, the lateral dimension of the bottom of the opening of the contact layer becomes 0.1 μm. The thickness of the insulating film at the bottom of the opening is smaller than that of the plane portion.

[0105] Next, as shown in FIG. 8 (e), SiO opening bottom by RIE using a CF ₄ gas and H ₂ gas
₂ Etch until the film remains about 100 nm. Oxygen plasma and organic cleaning to purify polymers, carbon, etc.
Insulating film 4 by ECR dry etching using F ₆ gas
Is etched by 200 nm in the plane portion to expose the surface of the channel layer 2 from the gate opening 6a. The lateral dimension as the gate length at the bottom of the opening is 0.2 μm.

Next, as shown in FIG. 8F, the respective electrodes are formed in the same manner as in the first embodiment, and the step of forming the FET is completed. The gate electrode is separated from the contact region in a self-aligned manner by the sidewall insulating film and is narrowed. In addition, the upper portion of the gate opening 6a is receded in the lateral direction and is inclined by the side wall, so that the burying property of the gate metal is improved. In the step of etching the contact layer using the insulating film 4 in which the gate opening 6 is formed as a mask (FIG. 8C), there is no adhesion of a reaction product, so that no etching failure occurs.

The threshold voltage V _T of the obtained FET is MO
-1.20 including between CVD growth batches and within the wafer
± 0.15V (2σ), maximum mutual congectance gm
Was 530 mS / mm on average. The standard deviation σ of the wafer surface in V _T was 40～80MV. Uniformity and reproducibility are slightly improved compared to the example of the seventh embodiment,
gm is improved. It is considered that the source resistance is reduced by the self-alignment using the sidewall insulating film.

In this embodiment, the recess is formed by dry etching by providing an etching stop layer in the middle of the element semiconductor layer. However, wet etching without using a stop layer can be employed.

(Tenth Embodiment) As can be seen from the ninth embodiment described above, in the etching back of an insulating film under dry etching conditions with low anisotropy and low damage, the openings are formed in the lateral direction. There is a disadvantage that it becomes wider. In the case of forming a fine gate electrode having a size of about 0.1 μm, since the spread of the opening lowers the accuracy of the final gate length, it is necessary to increase the management of the insulating film processing step in the middle. On the other hand, in the ninth embodiment, since the etching stop layer of the element semiconductor layer is used, the element semiconductor layer exposed in the step of forming the opening in the insulating film can be scraped. For this reason, a method for solving the problem of the prior art, in which a good Schottky barrier is not formed, which is a disadvantage of the prior art, without having to solve the problem, is described as an improvement of the ninth embodiment.

FIGS. 9 (a) to 9 (d) and FIGS.
(C) is a process sectional view for explaining the tenth embodiment of the present invention.

The element separation of the epitaxial growth substrate and B ⁺ ion implantation is the same as in the ninth embodiment.

As shown in FIG. 9A, a silicon oxide film having a thickness of 400 nm is deposited as an insulating film 4 on the epitaxially grown substrate having been subjected to element isolation, and an opening having an opening width of 0.50 μm is formed thereon. A photoresist film 5 having a thickness of about 1 μm is formed. The thickness of the silicon oxide film 4 is ninth
In this embodiment, the thickness is 700 nm. However, the thickness is reduced here by an amount that does not etch back. After this, CF
RIE using gas mixed with H ₂ at a flow rate of 20% to ₄
Then, the gate opening 6 is formed by etching the insulating film 4 until half of the insulating film 4 is left at 180 nm. Since the polymer adheres to the side surface of the gate opening 6, the bottom of the opening is narrowed to 0.44 μm.

As shown in FIG. 9B, 30% was added to CF _4.
E at a pressure of 1 mTorr using a mixed gas of oxygen O ₂
27% silicon oxide film by CR dry etching
By performing the etching for 0 nm, the n-type GaAs contact layer 3 is exposed at the bottom of the gate opening 6 of the insulating film 4.
The size of the bottom of the insulating film 4 at the opening 6 is 0.52 μm, and the size of the tapered top is 0.98 μm. In the ninth embodiment, there is no etch-back, the thickness of the insulating film 4 is reduced, and the etching amount is reduced as a whole, so that the lateral spread of the bottom of the opening is suppressed. It is almost the same as the film width dimension. On the other hand, since the etching gas contains oxygen, the exposed GaAs crystal plane has no carbon volume, but a few nm on the extreme surface is oxidized.

As shown in FIG. 9C, the remaining photoresist film 5 is ashed and removed by oxygen plasma, and is cleaned by organic cleaning and dilute hydrochloric acid treatment. Oxidation proceeds by the oxygen plasma, and the crystal surface of the n-type GaAs contact layer 3 having a thickness of about 10 nm is shaved by the diluted hydrochloric acid treatment. However, the original thickness of the contact layer 3 is 100 nm, and most remains.

[0115] As shown in FIG. 9 (d), the BCl ₃ 25
% SF ₆ at a pressure of 1 mtorr.
The CR method dry etching is performed to etch the n-type GaAs of the contact layer 3. A of lower channel layer 2
When the lGaAs is exposed, aluminum fluoride is generated and the etching stops. After organic washing, the fluorinated layer is removed by dilute hydrochloric acid treatment. This step corresponds to the ninth step.
This embodiment corresponds to FIG. 8 (c), and thereafter is the same as the ninth embodiment.

Next, as shown in FIG. 10A, SiO ₂ is deposited to a thickness of 300 nm as an insulating film 13 for forming a side wall film. The lateral dimension of the bottom of the opening newly deposited in the opening of the contact layer 3 by this film formation is 0.14 μm, and the thickness of SiO _{2 in} the vertical direction is 220 nm.

[0117] As shown in FIG. 10 (b), the SiO ₂ film of the open bottom when 150nm etching the SiO ₂ film of the flat portion by RIE using a mixed gas of flow rate 20% H ₂ in CF ₄ is approximately 100 nm remains. The polymer and carbon are removed by oxygen plasma and organic cleaning to purify the film. Subsequently, the insulating film 4 is etched by 200 nm in a flat portion by ECR dry etching using SF ₆ gas, and a channel layer 2 is formed through a new gate opening 6a. Expose the surface. The lateral dimension as the gate length at the bottom of the opening is 0.22 μm.

Next, as shown in FIG. 10C, the respective electrodes are formed in the same manner as in the first embodiment, and the step of forming the FET is completed. The pretreatment for sputter-depositing the gate metal is an organic cleaning and a dilute hydrochloric acid treatment.

The horizontal dimension of the bottom of the opening is 0.22 μm, and this dimension continues vertically and vertically by 0.16 μm. The opening gradually expands toward the top and is about 0.9 μm at the top. WSi 200 nm sputter-deposited in this tapered opening and A
The u600 nm gate metal is buried in the opening. The connection to the fine gate electrode is performed well without disconnection or constriction.

In the ninth and tenth embodiments, the accuracy (2σ) of the gate length including between manufacturing lots is ± 0.02.
6 μm and ± 0.014 μm. By eliminating the etch-back and reducing the initial thickness of the insulating film, the lateral spread of the bottom of the opening is suppressed, and the gate length accuracy is increased.

When the gate length is shortened, the gate capacitance is reduced and the cut-off frequency f _T is improved, but on the other hand, the gate reverse breakdown voltage and the drain breakdown voltage are reduced, and the element reliability is also reduced. If the shortest gate length is set to a limit from the viewpoint of reliability, if the accuracy is poor, it is necessary to increase the setting center of the gate length by that accuracy, and the high-frequency performance is reduced. Therefore, it is desired that the gate length accuracy is high. The gate length is 0.22 μm and V
Maximum cut-off frequency f _T average _T value in the element of -1.1V is 90 GHz, the gate reverse breakdown voltage -7V, 3 terminal drain breakdown voltage was 6V.

The backward etching in the lateral direction of the opening of the insulating film can be performed by increasing the gas etching gas pressure without adding oxygen and increasing the isotropy as described in the fifth embodiment. However, in the parallel plate type RIE, since the crystal face is exposed, it is necessary to reduce the high frequency power, lower the ion sheath voltage, and reduce the damage as described in the second embodiment.
On the other hand, the chlorine-based gas described in the sixth embodiment cannot be used in the tenth embodiment because it etches a compound crystal. The only gases that can be used are fluorine-based gases such as CF ₄ , SF ₆ and NF ₃ which do not etch compound crystals.

(Eleventh Embodiment) In the tenth embodiment, the one-stage recess gate structure has been described. However, as described in the eighth embodiment, the channel semiconductor layer is dug before forming the gate electrode. In addition, it is possible to form a two-stage recess buried gate structure. FIGS. 11A to 11C are process cross-sectional views for explaining an eleventh embodiment of the present invention.

The epitaxial substrate used is the same as that of the eighth embodiment. The manufacturing method is the same from FIGS. 9A to 9D and 10B of the tenth embodiment, and this drawing corresponds to FIG. 10A. EC using SF ₆ gas
The insulating film 4 is etched by the R method dry etching to expose the AlGaAs surface of the channel layer 2 from the new gate opening 6a, and this surface is purified by organic cleaning and dilute hydrochloric acid treatment. As shown in FIG. 11B, the n-type AlGaAs channel layer 2 is dug by 10 nm by wet etching described in the eighth embodiment to provide a second recess 27. As shown in FIG. 11C, the respective electrodes are formed in the same manner as in the first embodiment, and the step of forming the FET is completed.

In the present invention, as in the eighth embodiment, contamination and crystal shaving before the second recess is provided are small.
It is possible to accurately form the depth of the second recess. In addition, high accuracy can be obtained for the gate length as in the tenth embodiment. Further, the gate opening gently widens toward the upper portion due to the formation of the taper, and the connection to the fine gate electrode is performed well without disconnection or constriction.

In the above embodiment, in order to compare the effect with the comparative example, a two-dimensional high mobility two-dimensional structure is formed at the heterojunction interface between the channel layer and the buffer layer. Although a simple heterojunction field-effect transistor (HJFET) having an electron gas has been described, the present invention is not limited to these embodiments, and other types of FETs and furthermore, such as a diode or a Hall element, may be used. The present invention can be applied to an electrode forming step in a manufacturing process of a compound semiconductor element. Further, although the example in which the ECR method is used as the low-damage dry etching method has been described, similar effects can be obtained by using the ICP method or the helicon method instead of the ECR method.

[0127]

As described above, in the method of manufacturing a compound semiconductor device of the present invention, an opening is formed in an insulating film using a photoresist mask while leaving a thin insulating film, and after removing the photoresist film, Since the insulating film on the bottom surface of the opening is removed by etching under a low damage condition, it is possible to prevent a reaction product of a semiconductor component and carbon from being formed on the crystal surface. Therefore, according to the present invention, it is possible to avoid the adverse effects caused by the attachment of the reaction product, for example, the inconvenience that a good Schottky barrier is not formed. Then, it is not necessary to add oxygen to the etching gas or to add an oxygen plasma treatment in order to prevent the generation of a reaction product, and it is possible to prevent film reduction and surface roughness due to oxidation of the crystal surface. F
The threshold voltage V _T of ET becomes shallow it is possible to suppress the the uniformity is impaired, it is possible to improve the manufacturing yield.

Further, according to the embodiment of the present invention in which the inclination is formed in the upper part of the opening, the embedding property of the deposited electrode metal is improved, the disconnection of the electrode is prevented, and the increase in the resistance of the electrode is suppressed. Can be.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view at an early stage of a manufacturing process according to first to seventh embodiments of the present invention.

FIG. 2 is a layout diagram (top view) of the field-effect transistor according to the first to seventh embodiments of the present invention. Figure 1
3 to 6 are cross-sectional views taken along line AA 'in FIG.

FIG. 3 is a process cross-sectional view for explaining the first embodiment of the present invention.

FIG. 4 is a process sectional view for illustrating a third embodiment of the present invention.

FIG. 5 is a process cross-sectional view for explaining a fourth embodiment of the present invention.

FIG. 6 is a process cross-sectional view for explaining a seventh embodiment of the present invention.

FIG. 7 is a process cross-sectional view for explaining an eighth embodiment of the present invention.

FIG. 8 is a process sectional view for explaining a ninth embodiment of the present invention.

FIG. 9 is a process cross-sectional view for explaining a tenth embodiment of the present invention.

FIG. 10 is a process cross-sectional view for explaining a tenth embodiment of the present invention.

FIG. 11 is a process cross-sectional view for explaining an eleventh embodiment of the present invention.

FIG. 12 is a process sectional view of Conventional Example 1.

FIG. 13 is a cross-sectional view for explaining a problem of Conventional Example 1.

FIG. 14 is a cross-sectional view for explaining a problem of Conventional Example 1.

FIG. 15 is a process sectional view of Conventional Example 2.

FIG. 16 is a cross-sectional view for explaining a problem of Conventional Example 2.

FIG. 17 is a process sectional view of Conventional Example 3.

FIG. 18 is a cross-sectional view for explaining a problem of Conventional Example 3.

FIG. 19 is a cross-sectional view for explaining a problem of Conventional Example 3.

FIG. 20 is a cross-sectional view for explaining a problem of Conventional Example 3.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate (i-type GaAs) 2 Channel layer (n-type AlGaAs) 3 Contact layer (n-type GaAs) 4 Insulating film (SiO ₂ ) 5, 12 Photoresist film 6, 6a Gate opening 7 Gate electrode 8 Source electrode 9 Drain electrode 10 Schottky metal (WSi _x) 11 buffer layer (i-type GaAs) 13 side wall film formation insulating film (SiO ₂₎ 14 first insulating film (SiO ₂₎ 15 second insulating film (SiN _x) 16 reaction product Object 17 Layer scraping 18 Electrode metal 19 Side wall insulating film 21 Element isolation region 22 Contact region 23 Gate opening 24 Gate electrode 25 Ohmic electrode (source) 26 Ohmic electrode (drain) 27 Second recess

Claims (14)

[Claims] A first step of forming an element semiconductor layer on the surface of the compound semiconductor substrate; a second step of forming an insulating film on the element semiconductor layer;
A third step of performing development to form a photoresist film having an opening on an electrode formation region of the element semiconductor layer; and etching the insulating film halfway by a dry etching method using the photoresist film as a mask to form a bottom portion. A fourth step of forming an opening leaving the insulating film, a fifth step of removing the photoresist film, and exposing the entire surface of the insulating film by a dry etching method to expose a partial surface of the element semiconductor layer A method of manufacturing a compound semiconductor device, comprising: a sixth step of forming a first electrode; and a seventh step of forming an electrode in contact with the element semiconductor layer through an opening formed in the insulating film. 2. The method of manufacturing a compound semiconductor device according to claim 1, wherein said fourth step is a step of forming an opening having a side wall surface perpendicular to said insulating film by performing etching under a highly anisotropic condition. A first etching step and a second etching step after the first etching step, wherein the photoresist film is laterally etched and a slope is formed above an opening formed in the insulating film. A method for manufacturing a compound semiconductor device. 3. The method of manufacturing a compound semiconductor device according to claim 2, wherein said second etching step includes adding oxygen to an etching gas, increasing a gas pressure in an etching chamber, and using a chlorine-based gas. And a method using a mixed gas containing a chlorine-based gas. 4. The method for manufacturing a compound semiconductor device according to claim 1, wherein between the fifth step and the sixth step, an insulating film for forming a sidewall film is deposited and anisotropic etching is performed. 8. A method for manufacturing a compound semiconductor device, comprising an eighth step of forming a sidewall insulating film on a side surface of an opening formed in an insulating film. 5. The method of manufacturing a compound semiconductor device according to claim 1, wherein the dry etching in the sixth step is performed by an ECR (Electron Cyclotron Resonance) method or an IC.
P (Inductive Coupled Plasma) method or Helicon (Hel
icon) A method for manufacturing a compound semiconductor device, wherein the method is performed using a method. 6. The method for manufacturing a compound semiconductor device according to claim 1, wherein the dry etching in the sixth step is performed using an etching gas containing no carbon. . 7. The method according to claim 1, wherein the electrode formed in the seventh step is a Schottky junction electrode, and the element semiconductor layer formed in the first step is: A method for manufacturing a compound semiconductor device, comprising: a channel layer; and a pair of contact layers formed on the channel layer with a Schottky junction electrode formation region set on the channel layer interposed therebetween. 8. The method of manufacturing a compound semiconductor device according to claim 1, wherein
A method for manufacturing a compound semiconductor device, further comprising a ninth step of excavating the exposed element semiconductor layer by etching between the step and the seventh step. 9. The method of manufacturing a compound semiconductor device according to claim 8, wherein the etching depth in said ninth step is 50 nm or less. 10. The method for manufacturing a compound semiconductor device according to claim 1, wherein the element semiconductor layer formed in the first step includes a channel layer and a contact layer formed on the channel layer. The sixth step and the seventh step
A tenth step of etching the contact layer using the insulating film as a mask to form an opening exposing the surface of the channel layer in the contact layer, and depositing an insulating film for forming a sidewall film on the contact layer. The method according to claim 1, further comprising an eleventh step of forming sidewall insulating films on side surfaces of the openings formed in the insulating film and the openings formed in the contact layer by performing isotropic etching. The manufacturing method of the compound semiconductor device of the above. 11. A first step of forming an element semiconductor layer including an etching stop layer on the surface of a compound semiconductor substrate,
A second step of forming an insulating film on the element semiconductor layer;
A third step of applying a photoresist, performing exposure and development to form a photoresist film having an opening on an electrode formation region of the element semiconductor layer, and the insulating process is performed by a dry etching method using the photoresist film as a mask. A first etching step in which the film is etched partway to leave the insulating film at the bottom, and after the first etching step, the photoresist film is laterally etched and an opening formed in the insulating film is formed. A fourth step including a second etching step of forming an opening by etching the bottom of the insulating film and forming an opening, a fifth step of removing the photoresist film, and forming the insulating film on the bottom of the insulating film. A sixth step of etching the element semiconductor layer from the opened opening to the etching stop layer to dig the opening, and depositing an insulating film for forming a sidewall film; A seventh step of forming a side wall insulating film on the side surface of the opening formed in the insulating film and the element semiconductor layer by performing anisotropic etching; and forming an element semiconductor layer exposed through the opening formed by the side wall insulating film. Forming a contacting electrode. 12. The method for manufacturing a compound semiconductor device according to claim 11, wherein said second etching step uses one of adding oxygen to an etching gas and increasing a gas pressure of an etching chamber. A method for manufacturing a compound semiconductor device. 13. The method for manufacturing a compound semiconductor device according to claim 11, further comprising a ninth step of excavating the exposed element semiconductor layer by etching between the seventh step and the eighth step. A method for manufacturing a compound semiconductor device, comprising: 14. The method for manufacturing a compound semiconductor device according to claim 13, wherein the etching depth in said ninth step is 50 nm or less.