JPS59205765A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the input capacitance of a FET by forming an initial opening for forming a Schottky junction to an insulating film shaped on a GaAs substrate, depositing an insulating film in approximately half thickness of the insulating film on the whole surface while being buried into the opening, leaving the thin insulating film only to the side wall of the opening through reactive plasma etching and digging a groove in predetermined depth on the bottom of a formed opening. CONSTITUTION:An N type active layer 2 is diffused and formed to the surface layer section of a semi-conductor GaAs substrate 1, the whole surface containing the active layer 2 is coated with a SiO2 film 3, and an initial opening 5 is bored to the film 3 through etching while using a photo-resist film 4 with an opening as a mask. A Si3N4 film 6 in approximately half thickness of the thickness of the SiO2 film 3 is applied on the whole surface while being attached on the bottom and side wall of the initial opening, and the film 6 adhering on the bottom is removed. Consequently, the width of the opening 5 to which a gate electrode 8 is formed in narrowed, a dug groove 7 in desired depth is bored in the exposed layer 2, and the gate electrode 8 is shaped in the groove 7. Accordingly, the gate electrode with width larger than one formed through photoetching technique is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a manufacturing method useful for improving the performance of a semiconductor device, particularly a Schottky junction field effect transistor formed by forming a Schottky junction in a compound semiconductor such as gallium arsenide.

Generally, in order to improve the performance of a Schottky junction field effect transistor (hereinafter referred to as ME8 FET), it is required to reduce parasitic capacitance such as input capacitance, wiring ground capacitance, and inter-wiring capacitance, and increase mutual conductance. be done. To this end, measures are being taken to improve performance from various viewpoints, such as shortening gate length, improving FET structure, and improving semiconductor substrate materials.

Currently, the optical exposure equipment commonly used has a
Although it is said to be difficult to form patterns as fine as 100 m or less, there has been remarkable progress in processing technology, especially for shortening gate lengths, and lithography techniques include electron beam exposure and X-ray exposure. is about to be used as the next generation manufacturing technology. Additionally, dry processing equipment that makes full use of gas plasma and ion beams is being developed as a processing technology for accurately transferring fine and highly accurate patterns onto devices, and is becoming established as a core technology for device manufacturing.

However, the EB exposure equipment and X-ray exposure equipment for forming the above-mentioned fine patterns are currently too expensive, and in terms of manufacturing capacity, they are not comparable to the currently commonly used phosphorography equipment. It is considered to be inferior. Moreover, these devices have their own problems, such as electron beam damage, edge effects, and X-ray damage.

The purpose of the present invention is to form fine patterns of 1 μm or smaller with high precision using optical exposure equipment commonly used at present, and to improve breakdown voltage and reduce parasitic resistance of GaAsMES FETs, etc., and to reduce parasitic resistance at low cost. The purpose of the present invention is to provide a method that can be manufactured by forming an initial opening for forming a Schottky junction in an insulating film on a compound semiconductor substrate such as gallium arsenide, and then using vapor phase epitaxy or plasma enhancement vapor phase epitaxy. An insulating film is deposited to a thickness of about 1/2 of the desired shortened dimension from the initial opening gluing method, and then hydrogen (H2) is mixed with 7 Leon gas (CF4) at a ratio of 5 to 50%. The insulating film deposited on the side wall of the initial opening is removed by reactive plasma etching using gas plasma, and the insulating film is removed from the A-shaped portion, leaving the insulating film deposited on the side wall of the initial opening. The structure includes digging a groove of a desired depth in the bottom of the opening using an etching solution for etching the substrate.

Next, the present invention will be explained using examples.

1 to 7 are cross-sectional views of a semiconductor substrate in the middle of a process in order to explain an embodiment of the present invention. First, as shown in FIG. 1, a silicon oxide film is deposited by chemical vapor deposition on a semi-insulating gallium arsenide substrate 1 on which an N-type active layer 2 is provided by ion implantation, vapor deposition, etc. 3 to the desired thickness. Next, as shown in FIG. 2, an initial opening 5 is formed by etching away the oxide film 3 over a predetermined dimension L μm using a photoresist film 4 formed by photolithography, which is used in a normal semiconductor device manufacturing process, as a mask. After removing the photoresist film 4, as shown in FIG. 3, the size of the initial opening 5 (L μm) is
), an insulating film 6 such as an oxide film or a silicon nitride film is deposited to a thickness of half the desired shortening (1 μm). continue,
A diode type F sputter etching system, which is commonly used as a plasma etching system for silicon nitride films and silicon oxide films, is used to generate a gas plasma in which Freon gas (CF4) and hydrogen (H2) are mixed at a ratio of 5 to 50%. By performing directional etching, the silicon nitride film 6 is formed only on the side wall of the initial opening 5, as shown in FIG.
All other areas are etched off except for.

Through the above steps, the dimension of the opening 5 in which the gate electrode is provided can finally be reduced by 21 minutes from the initially opened dimension, resulting in a gate length of (L-21). For example, an initial opening of 1.5 μm is made, and a 0.4 μm opening is made on the side wall.
If a μm thick nitride film is deposited and the above dry etching is performed, the finished gate length can be 0.7 μm.

As described above, according to the present invention, even if the initial opening size is relatively easily formed by ordinary photolithography, short dimensions that are difficult to form by ordinary photolithography can be formed by the above-mentioned method. It is possible to easily form up to

Next, from the viewpoint of improving the withstand voltage and reducing the parasitic resistance in the MB2 FET, in order to form the opening 5 into a forward tapered recess structure or a reverse tapered recess structure, the gallium arsenide substrate 1 is heated with phosphoric acid as shown in FIG. Grooves 7 are excavated by etching only the substrate as desired using hydrogen peroxide-hydrogen and sodium hydroxide-hydrogen peroxide-hydrogen gallium arsenide etchants without attacking the silicon oxide film or silicon nitride film 6. In addition, the thickness of the active layer of the field effect transistor is controlled to adjust the desired pinch-off voltage, saturation current, etc. Next, as shown in Figure 6, the usual gallium arsenide MES
The gate electrode 8 is formed by vacuum evaporation and ordinary photolithography, as is done in the FET manufacturing process. Next, as shown in FIG. 7, the source and drain electrodes 9, 9 of the field effect transistor are formed at the same time, after opening the silicon nitride film by ordinary photolithography, by vacuum evaporation or the like, for example, as ohmic electrodes. AuGe/Ni or Au Qe/P
After vapor-depositing and alloying in a hydrogen atmosphere at 400° C., Ti/Pt/Au and the like are formed by making full use of a so-called lift-off technique using a normal photolithography method.

As shown in the embodiments described above, the present invention combines the shortening of the gate length by leaving an insulating film on the sidewall of the gate opening, and the reduction of parasitic resistance by further etching the semiconductor substrate after forming the sidewall film. It is possible to reduce the input capacitance, etc. in MES FETs made of gallium arsenide, etc., and to reduce the parasitic resistance at a desired active layer thickness, and also to reduce the manufacturing cost of the product.

[Brief explanation of the drawing]

1 to 7 are cross-sectional views of the substrate in the middle of the process to explain the manufacturing process of an embodiment of the present invention. 1... Gallium arsenide substrate, 2... N-type active layer, 3... Oxide film, 4... Photoresist film, 5...・Opening, 6...Silicon nitride film, 7...Drilled groove', 8...
...Gate electrode, 9...Source/drain electrode.

Claims (1)

[Claims] When manufacturing a Schottky junction field effect transistor (hereinafter referred to as MES FET) in which a Schottky junction is formed on a compound semiconductor substrate such as gallium arsenide, an initial opening for forming a Schottky junction is provided in an insulating film provided on the substrate, Next, an insulating film is deposited by vapor phase epitaxy or plasma enhancement vapor phase epitaxy to a thickness of about 172 mm, which is the desired shortening from the initial opening dimension, and hydrogen ( By reactive plasma etching using gas plasma mixed with H2) at a ratio of 5 to 50 cm, the insulating film deposited on the side wall of the initial opening is removed, and the other parts of the insulating film are removed. 1. A method of manufacturing a semiconductor device, comprising: digging a groove of a desired depth at the bottom of the opening using an etching solution that etches the semiconductor substrate without corroding the insulating film on the side wall.