JPS63116430A - Method of forming mask - Google Patents

Method of forming mask

Info

Publication number
JPS63116430A
JPS63116430A JP62117263A JP11726387A JPS63116430A JP S63116430 A JPS63116430 A JP S63116430A JP 62117263 A JP62117263 A JP 62117263A JP 11726387 A JP11726387 A JP 11726387A JP S63116430 A JPS63116430 A JP S63116430A
Authority
JP
Japan
Prior art keywords
layer
mask
substrate
forming
lithography
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62117263A
Other languages
Japanese (ja)
Other versions
JP2553078B2 (en
Inventor
ニコラス・ジェームズ・ジャマーコ
アレキサンダー・ジンペルソン
ジョージ・アンソニー・カプリタ
アレキサンダー・ダニエル・ロパタ
アンソニー・フランシス・スカデュト
ジョセフ・フランシス・シェパード
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS63116430A publication Critical patent/JPS63116430A/en
Application granted granted Critical
Publication of JP2553078B2 publication Critical patent/JP2553078B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322—Composite web or sheet

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 Ａ、産業上の利用分野 この発明は集積回路（ＩＣ）の製造用のりソグラフィ画
像の大きさを縮小する方法に関するものである。詳細に
いえば、この発明はりソグラフイで得られる大きさより
も小さな開口を有するマスクを形成する方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to a method for reducing the size of lithographic images for the manufacture of integrated circuits (ICs). More particularly, the present invention relates to a method of forming a mask having an aperture smaller than that available with lithography.

Ｂ、従来技術 デバイスを縮小することが絶えず要望されているため、
ＩＣ業界には硝子たる進歩がみられる。B. Due to the constant desire to shrink prior art devices,
The IC industry is seeing tremendous progress.

デバイスの寸法を小さくすることは、製造コストを削減
すると同時に、性能（スピード）を改善するものである
。この進歩は湿式エツチングを乾式エツチング（プラズ
マ・エツチング、反応性イオン・エツチングおよびイオ
ン・ミリング）への変更、高比抵抗のポリシリコンの相
互接続に代わるものとしての低比抵抗のケイ素化合物と
超硬合金の使用、精密な細線リソグラフィを損なうウエ
ハ表面の変動を補πする複式レジスト、純度を高め材料
の欠陥を削減するレーザおよび電子ビーム処理、低マイ
クロメートル・レベルでの線幅および層間整合状態を測
定することのできない光学的方法に代わってこれらのパ
ラメータを検査する非光学的方法などの、新しい処理手
法に負うものではあるが、リソグラフィはすべての工程
を進歩させる推進力であった。深紫外線源および光学手
段を備えた１：１光学投射システムなどの改善されたり
ソグラフィ・ツール、電子ビーム、直接ステップ・ウェ
ハ、ならびにＸ　１．ｆｉｔおよびイオン・ビーム・シ
ステムおよび改善されたフォトレジスト材料、およびＸ
線または電子ビームに感光させた頂部レジストと底部の
直線光学レジスト層を利用した多層レジストなどの方法
は、この推進力の原因の一部である。Reducing device dimensions reduces manufacturing costs while improving performance (speed). This advancement has led to the change of wet etching to dry etching (plasma etching, reactive ion etching and ion milling), and the use of low resistivity silicon compounds and carbide as an alternative to high resistivity polysilicon interconnects. The use of alloys, duplex resists to compensate for wafer surface variations that compromise precision fine-line lithography, laser and e-beam processing to increase purity and reduce material defects, and improve linewidth and interlayer alignment at the low micrometer level. Lithography has been the driving force behind advances in all processes, although this is due to new processing techniques, such as non-optical methods that examine these parameters instead of optical methods that cannot measure them. Improved lithography tools such as 1:1 optical projection systems with deep UV sources and optical means, electron beams, direct step wafers, and X1. fit and ion beam systems and improved photoresist materials, and
Methods such as multilayer resists that utilize a top resist that is exposed to a line or electron beam and a bottom linear optical resist layer are partly responsible for this drive.

Ｃ０発明が解決しようとする問題点 この目覚ましい進歩にもかかわらず、リソグラフィ・ツ
ール、材料および方法自体に対する拡張機能によって提
供されるもの以上の画像の大きさを小さくすることに対
する要望は、絶えず存在している。しかしながら、従来
技術はこの要望に対処できなかった。Problems that the C0 Invention seeks to solve Despite this remarkable progress, there continues to be a desire to reduce image size beyond that provided by enhancements to lithography tools, materials, and methods themselves. ing. However, the prior art has not been able to address this need.

Ｄ０問題点を解決するための手段 最も範囲の広い形態において、この発明は画像を得るた
めに使用されるリソグラフィ・マスク材料の開口内面に
側壁を設けることによって、リソグラフィ画像の大きさ
を縮小する方法を提供する。SUMMARY OF THE INVENTION In its broadest form, the invention provides a method for reducing the size of a lithographic image by providing sidewalls on the inner surface of an opening in the lithographic mask material used to obtain the image. I will provide a.

特定の実施例において、この発明はりソグラフィによっ
て得られる大きさよりも小さな開口を有するマスクを作
成する方法を提供する。基板（たとえば、半導体、絶縁
物または金属）から始めた場合、フォトレジストおよび
二酸化シリコンなどの絶縁材の薄いリリース層が基板上
に形成される。In certain embodiments, the invention provides a method of making a mask having an opening smaller than that obtained by lithography. Starting with a substrate (eg, semiconductor, insulator, or metal), a thin release layer of photoresist and an insulating material such as silicon dioxide is formed on the substrate.

次いで、感光材料の厚い層が貼付される。厚い層にはり
ソグラフィ手段によって、リソグラフィの限界によって
決定される最小の開口を有するように、パターンが形成
される。その後、開口の大きさをさらに小さくするため
に、コンフォーマル層材料がパターンの形成された感光
材料層、およびパターンの形成された層の開口によって
露出された基板部分に貼付される。コンフォーマル層材
料の厚さは、開口の大きさの希望する縮尺によって決定
される。たとえば、細長い開口の場合、開口の幅の縮小
率は、コンフォーマル層の厚さの約２倍である。コンフ
ォーマル層材料の例としては、プラズマ堆積ヘキサメチ
ルジシラザン（ＨＭＤＳ）によって形成されたＳ　１ｘ
０．が挙げられる。指向性反応性イオン・エツチング（
ＲＩＥ）によって、コンフォーマル層がすべての水平表
面から除去され、感光材料内の開口に対応した非水平面
上に、コンフォーマル層材料の側壁が残される。感光材
料内の開口によって露出させられたリリース層も、ＲＩ
Ｈによって除去される。コンフォーマル層材料の側壁と
組み合わされた厚い感光マスクが、リソグラフィ単独で
得られるものよりも小さな開口を有する新しいマスク（
ステンシル）を構成する。A thick layer of photosensitive material is then applied. The thick layer is patterned by lithography means with a minimum opening determined by lithography limitations. A conformal layer material is then applied to the patterned layer of photosensitive material and the portion of the substrate exposed by the aperture in the patterned layer to further reduce the size of the aperture. The thickness of the conformal layer material is determined by the desired scaling of the aperture size. For example, for an elongated aperture, the reduction factor in the width of the aperture is approximately twice the thickness of the conformal layer. Examples of conformal layer materials include S 1x formed by plasma deposited hexamethyldisilazane (HMDS).
0. can be mentioned. Directional reactive ion etching (
RIE) removes the conformal layer from all horizontal surfaces, leaving sidewalls of conformal layer material on non-horizontal surfaces corresponding to openings in the photosensitive material. The release layer exposed by the opening in the photosensitive material also
removed by H. A thick photosensitive mask combined with the sidewalls of the conformal layer material provides a new mask (
stencil).

この新しいマスクは、縮小された門口によって露出させ
られた基板に注入を行なうためのイオン注入を含むさま
ざまな目的に使用できる。例えばこの新しいマスクを基
板に幅の狭いトレンチをエツチングするためのＲＩＥマ
スクとして、半導体基板の露出領域に埋込絶縁分離を形
成するための酸化マスクとして、基板に対する幅の狭い
接触または基板上の導線を確立するための接触マスクま
たはメタライゼーション・マスクとして、あるいはその
他の目的で使用できる。このような用途に使用したのち
、リリース層に湿式エツチングを施して、新しいマスク
を基板から剥離させる。This new mask can be used for a variety of purposes, including ion implantation to implant into the substrate exposed by the reduced portal. For example, this new mask can be used as an RIE mask for etching narrow trenches in a substrate, as an oxidation mask for forming buried isolation in exposed areas of a semiconductor substrate, for making narrow contacts to a substrate or for conductive lines on a substrate. It can be used as a contact mask or metallization mask to establish After such use, the release layer is wet-etched and the new mask is peeled from the substrate.

幅が狭くしかも深いトレンチを半導体基板内に形成する
ためには、上面にフォトレジストまたはポリイミドなど
の厚い絶縁層を有する半導体基板から始めることによっ
て、上述のマスク形成方法を手直しする。上述の新しい
マスクは厚い絶縁属上に形成され、その後、新しいマス
クなＲＩＢマスクとして使用したＲＩＥによって、厚い
絶縁層にパターンを形成する。リリース層の剥Ｓ後、基
板上のパターンの形成された厚い絶縁層は、リソグラフ
ィの限界よりも幅の狭い、深いトレンチを半導体材料中
にエツチングするためのトレンチＲ１Ｂマスクとして機
能する。To form narrow and deep trenches in a semiconductor substrate, the mask formation method described above is modified by starting with a semiconductor substrate having a thick insulating layer, such as photoresist or polyimide, on the top surface. The new mask described above is formed on the thick insulating layer, and then the thick insulating layer is patterned by RIE, which is used as the new mask RIB mask. After stripping of the release layer, the patterned thick insulating layer on the substrate serves as a trench R1B mask for etching deep trenches into the semiconductor material that are narrower than the lithographic limits.

Ｅ、実施例 第１図ないし第４国に示した処理工程において、処理は
基板１０から開始される。基板１０はその上に光活性層
をコーティングでき、かつリソグラフィ手法によってパ
ターンを形成することのできる任意の材料である。たと
えば、基板１０は半導体材料、ガラス、絶縁体、−大恩
光材料、金属またはこれらを組み合わせたものである。E. EXAMPLE In the processing steps shown in FIGS. 1-4, processing begins with the substrate 10. Substrate 10 is any material onto which a photoactive layer can be coated and patterned by lithographic techniques. For example, the substrate 10 may be a semiconductor material, glass, an insulator, a large-scale material, a metal, or a combination thereof.

次に、リリース層１２を基板１０に貼付する。リリース
層１２を基板から容易に除去できる材料で構成する。Next, the release layer 12 is attached to the substrate 10. Release layer 12 is constructed from a material that is easily removed from the substrate.

このような除去は湿式化学エツチング液によって、ある
いは酸素アッシング（灰化法）によって行なわれる。リ
リース層の基本的な機能はそれ自体の除去を容易とする
ことであるから、この層の上にこのあとで形成されるあ
らゆる層／構造も同様に除去される。Ｂ１２を形成する
のに適した材料の例としては、フォトレジストが挙げら
れる。ひとつの例においては、ＡＺ１３５０Ｊ［アメリ
カン・ヘキスト（Ａｍｅｒｉｃａｎ　Ｈｏｅｃｈｔｓｔ
　）社の商標］というフォトレジストを、スピン・コー
ティングによって貼付し、その後、約２００ないし２５
０℃の温度において約３０ないし６０分間焼き付けるこ
とによって、約２００ないし１０００人のリリース層１
２を得た。約２００人未満の厚さでは、リリース層は基
板１０を高い信頼性でコーティングするには薄過ぎるこ
とになる。Such removal may be accomplished by wet chemical etching solutions or by oxygen ashing. Since the basic function of the release layer is to facilitate its own removal, any layers/structures subsequently formed on top of this layer will be removed as well. An example of a suitable material for forming B12 includes photoresist. In one example, AZ1350J [American Hoechst
) photoresist is applied by spin coating, followed by a coating of about 200 to 25
By baking at a temperature of 0° C. for about 30 to 60 minutes, about 200 to 1000 release layers 1
I got 2. At a thickness less than about 200 nm, the release layer will be too thin to reliably coat the substrate 10.

リリース層１２の形成後、この方法を継続し、感光材料
の薄い結像層１４を、たとえばスピン・コーティングに
よって、第１図に示すように塗布する。結像層１４の厚
さは０．８ないし３ミクロンの範囲で十分である０層１
４の材料の例はＡＺ１３５０Ｊフォトレジストである。After the formation of the release layer 12, the method continues and a thin imaging layer 14 of photosensitive material is applied, for example by spin coating, as shown in FIG. The thickness of the imaging layer 14 is preferably in the range of 0.8 to 3 microns.
An example of material number 4 is AZ1350J photoresist.

感光材料のコーテイング後、層にはりソグラフィ・ツー
ルのパターン露出、現像、洗浄および乾燥によって希望
するパターンが形成される。説明を簡単化するため、第
１図においては、横方向寸法がＡである単一の開口１６
が、はぼ水平な表面１８およびほぼ垂直な表面２０−２
０を有する居１４内に示されている０寸法Ａはリソグラ
フィで得られる最小の画像の大きさである。換言すると
、幅Ａはリソグラフィ（Ｘ線、電子ビームなどを含む）
の解像度を限界まで上げることによって達成できる最小
の寸法である。次に、パターンの形成された感光材料の
層に硬化処理を施し、層１４を熱的に安定させる。After coating the photosensitive material, the layer is formed into the desired pattern by pattern exposure of a lithography tool, development, washing and drying. For ease of explanation, in FIG. 1 a single opening 16 with lateral dimension A is shown.
However, the nearly horizontal surface 18 and the nearly vertical surface 20-2
The zero dimension A, shown in box 14 with a zero, is the smallest image size that can be obtained with lithography. In other words, the width A is lithography (including X-ray, electron beam, etc.)
This is the minimum dimension that can be achieved by increasing the resolution of The patterned layer of photosensitive material is then subjected to a curing process to thermally stabilize layer 14.

深紫外線露出または約１ないし２分間の約２００ないし
２５０℃の熱処理を、硬化処理に使用することができる
。他の層１４の硬化方法は、この層をハロゲン・ガス・
プラズマにさらすことである。Deep ultraviolet light exposure or heat treatment at about 200 to 250° C. for about 1 to 2 minutes can be used for the curing process. The method for curing the other layer 14 is to cure this layer using halogen gas.
exposure to plasma.

この硬化処理工程は、層１４に以降の層を堆積させる際
に、この層１４を構成している感光材料に泡が生じたり
、この層が溶融したり、流れたり、あるいは劣化するこ
とを防ぐために、公知のフォトレジストには必要である
。This curing step prevents the formation of bubbles in the photosensitive material of which layer 14 is deposited, as well as the melting, running, or deterioration of the layer 14 when subsequent layers are deposited thereon. This is necessary for known photoresists in order to

この方法の次の工程は垂直表面２０−２０に側壁を確立
し、開口１６の横方向寸法Ａを、リソグラフィ単独で達
成できるものよりも小さくすることである。側壁技術は
以下の特許で例示されているように、公知である。本発
明の出願人の米国特許第４２０９３４９号はマスク内に
小さな開口を形成するのに、側壁技術を利用している。The next step in the method is to establish sidewalls on the vertical surfaces 20-20, making the lateral dimension A of the opening 16 smaller than that which can be achieved with lithography alone. Sidewall technology is known, as exemplified by the following patents: Assignee of the present invention, US Pat. No. 4,209,349, utilizes sidewall technology to form small openings in a mask.

この方法によれば、第１の絶縁領域が基板上に形成され
、水平および垂直表面が得られる。第１層の材料とは異
なる材料の第２の絶縁体層が貼付され、第２の絶縁体の
水平領域が除去され、この層のきわめて幅の狭い領域だ
けが、第１の絶縁体の垂直表面領域および基板のそれぞ
れの領域に残るような態様で、ＲＩＥが施される。その
後、露出した基板の領域が熱酸化され、かつ希望するマ
スクの開口を最終的に形成するために、その部分の第２
の絶縁体層の領域が除去される。米国特許第３３５８３
４０号には、側壁の像転写を使用してサブミクロンのデ
バイスを作成する方法が記載されている。According to this method, a first insulating region is formed on the substrate, providing horizontal and vertical surfaces. A second insulator layer of a different material than that of the first layer is applied, horizontal areas of the second insulator removed, and only very narrow areas of this layer RIE is applied in such a manner that the surface area and the respective areas of the substrate remain. The exposed areas of the substrate are then thermally oxidized and a second
A region of the insulator layer is removed. U.S. Patent No. 33583
No. 40 describes a method for making submicron devices using sidewall image transfer.

サブミクロンの厚さの導電性フィルムが分離の隣接する
表面の間の垂直なステップに堆積され、次いで、導電性
フィルムの垂直ステップに隣接した部分だけが残るよう
になるまで、垂直にエツチングされる。導電体に覆われ
ていない他の分離は除去され、これによって、Ｍ　ＯＳ
　Ｔｉ界効果トランジスタのサブミクロンの幅のゲート
が得られる。本発明の出願人の米国特許第４４１９８０
９号および同第４４１９８１０号は、側壁を使用して狭
いゲートを画定することによって、自己整合電界効果ト
ランジスタを作成する方法を開示している。A submicron-thick conductive film is deposited in vertical steps between adjacent surfaces of the separation and then vertically etched until only portions of the conductive film adjacent to the vertical steps remain. . Other separations not covered by conductors are removed, thereby making the MOS
Submicron width gates of Ti field effect transistors are obtained. Assignee's U.S. Pat. No. 4,419,800
No. 9 and No. 4,419,810 disclose methods of making self-aligned field effect transistors by using sidewalls to define narrow gates.

米国特許第４４６２８４．６号は側壁を使用して、埋込
絶縁分離領域のバーズ・ピークを最小限のものとするこ
とを開示している０本発明の出願人の米国特許第４５０
２９１４号は、垂直壁を有する高分子材料の構造体を提
供することによって、サブミクロンの構造体を作成する
方法を記載している。この垂直壁はサブミクロンの幅の
側壁構造を作成するのに役立つものである。側壁構造は
マスクとして、直接使用される。ネガ・リソグラフィを
行なうため、他の層が側壁構造に貼付され、側壁構造の
ピーク部分が露出するまで、部分的に除去される。その
後、側壁構造自体が除去され、結果として得られる開口
が集積回路装置を製造するためのマスク開口として使用
される。U.S. Pat. No. 4,462,84.6 discloses the use of sidewalls to minimize bird peaks in buried isolation regions.
No. 2914 describes a method for making submicron structures by providing structures of polymeric material with vertical walls. This vertical wall is useful for creating submicron width sidewall structures. The sidewall structure is used directly as a mask. To perform negative lithography, other layers are applied to the sidewall structure and partially removed until the peak portions of the sidewall structure are exposed. The sidewall structure itself is then removed and the resulting opening is used as a mask opening for manufacturing integrated circuit devices.

層１４内の開口１６の大きさを小さくするため（第２図
）、コンフォーマル層２２がパターンの形成された感光
性層１４、およびその内部の開口１６によって露出され
たリリース層１２の部分に形成される。コンフォーマル
層の材料はポリシリコン、Ｓｌ、０．、二酸化シリコン
、チッ化シリコン、オキシチッ化シリコンまたはこれら
を組み合わせたものである。一般に、コンフォーマル層
２２はパターンの形成された感光性層１４の劣化を生じ
させない程度の十分低い温度で堆積できる任意の材料で
ある。層２２を形成するのに好ましい材料は、ヘキサメ
チルジシラザン（ＨＭＤＳ）のプラズマ堆積によって得
られる５１ｘＯｙである。To reduce the size of openings 16 in layer 14 (FIG. 2), conformal layer 22 is applied to patterned photosensitive layer 14 and the portions of release layer 12 exposed by openings 16 therein. It is formed. The material of the conformal layer is polysilicon, Sl, 0. , silicon dioxide, silicon nitride, silicon oxynitride, or a combination thereof. Generally, conformal layer 22 is any material that can be deposited at a temperature sufficiently low to not cause degradation of patterned photosensitive layer 14. A preferred material for forming layer 22 is 51xOy obtained by plasma deposition of hexamethyldisilazane (HMDS).

典型的な場合、層２２は第１図の構造を有する基板をプ
ラズマ堆積システム内に取り付け、液体ＨＭＤＳを処理
チェンバに導入し、その内部に、液体ＨＭ　Ｄ　ＳをＨ
ＭＤＳプラズマに変換するのに必要な電界を発生させる
ことによって形成される。Typically, layer 22 mounts a substrate having the structure of FIG. 1 into a plasma deposition system, introduces liquid HMDS into a processing chamber, and injects liquid HMDS into the process chamber.
It is formed by generating the electric field necessary to convert it into an MDS plasma.

ＨＭ　Ｄ　Ｓは第１図の構造に堆積し、５ｉｘｔｙ化合
物を有するプラズマ堆積ＨＭ　Ｄ　Ｓの共形で均一な層
２２をもたらす。層２２の厚さＢは感光材料層１４のリ
ソグラフィ画像の大きさの希望する縮尺によって決定さ
れる。典型的な場合、超大規模集積回路の製造において
、層２２の厚さは０．０１ないし０．６ミクロンの範囲
である。層２２の厚さの下限は、５１４のほぼ垂直な壁
部分２０に関連するステップを良好に覆うための要件、
ならびに藩閥としての層２２の可能性によって決定され
る。層２２の厚さの上限は、層１４内の開口１６の大き
さの希望する縮小率によって決定される。HM D S is deposited on the structure of FIG. 1, resulting in a conformal, uniform layer 22 of plasma deposited HM D S with a 5ixty compound. The thickness B of layer 22 is determined by the desired scale of the lithographic image size of photosensitive material layer 14. Typically, in the manufacture of very large scale integrated circuits, the thickness of layer 22 ranges from 0.01 to 0.6 microns. The lower limit on the thickness of layer 22 is the requirement for good coverage of the steps associated with substantially vertical wall portions 20 of 514;
It is also determined by the possibility of layer 22 as a clan faction. The upper limit on the thickness of layer 22 is determined by the desired reduction in the size of opening 16 in layer 14.

開口の大きさの縮小率は、２Ｂ／Ａという係数によって
左右される。換言すると、開口の大きさが３ミクロンで
ある場合、開口１６の大きさを６６゜６％縮小する（孔
の実際の大きさを１ミクロンに縮小する）には、１ミク
ロンの厚さのＨＭＤＳが堆積される。コンフォーマル層
２２を形成したのち、異方性エツチングを行なうことに
より、はぼ水平な表面のすべてから除去し、層１４のほ
ぼ垂直な表面にだけ残るようにする。ハロゲン含有エツ
チング・ガスによって、ｒｔｌＥを行なってもかまわな
い。適切なエツチング・ガスのひとつは、ＣＦ４である
。第３図は結果として得られる構造を示すものであって
、２４で表わす層２２の未エツチング部分は、層１４の
垂直表面２０上で側壁としての役割を果たす。開口の垂
直表面の内面に側壁２４を確立することにより、開口１
６の大きさは第３図のＣで示されている新しい寸法に縮
小される。パラメータＡ、ＢおよびＣの間の関係は、Ｃ
＝Ａ−２Ｂで与えられる。The reduction rate of the aperture size is influenced by a factor of 2B/A. In other words, if the aperture size is 3 microns, to reduce the size of the aperture 16 by 66°6% (reducing the actual size of the hole to 1 micron), a 1 micron thick HMDS is required. is deposited. After conformal layer 22 is formed, it is removed from all nearly horizontal surfaces by anisotropic etching, leaving only the generally vertical surfaces of layer 14. RtlE may be performed using a halogen-containing etching gas. One suitable etching gas is CF4. FIG. 3 shows the resulting structure in which the unetched portions of layer 22, designated 24, serve as sidewalls on the vertical surface 20 of layer 14. Opening 1 by establishing side walls 24 on the inner surface of the vertical surface of the opening
The size of 6 is reduced to the new size shown at C in FIG. The relationship between parameters A, B and C is C
=A-2B.

開口１６の垂直表面に側壁２４を確立したのち、縮小さ
れた開口１６によって露出させられたリリース層１２の
部分が、たとえば層１４の水平表面からの層２２の除去
を容易化したものと同じエツチング液種または０２プラ
ズマのいずれがを使用したＲＩＥによって除去される。After establishing the sidewalls 24 on the vertical surfaces of the apertures 16, the portions of the release layer 12 exposed by the reduced apertures 16 are etched with the same etching that facilitated the removal of the layer 22 from the horizontal surfaces of the layer 14, for example. Removed by RIE using either liquid species or 02 plasma.

このようにして製造された側壁２４と組み合わされた感
光性マスクは、リソグラフィ単独で得られるものよりも
相当程度縮小された寸法の開口を有する新しいマスク（
ステンシル）を構成する。The photosensitive mask combined with the sidewalls 24 produced in this way is a new mask (
stencil).

新しいマスクはさまざまな用途に役立つ。たとえば、第
４図に示すように、基板１０のきわめて幅が狭く、小さ
な領域２６に注入を行なうためのイオン注入マスクとし
て使用することができる。新しいマスクの他の用途は、
基板１０にきわめて狭い／深いトレンチをエツチングす
るエツチング・マスクとしてのものである。他の用途は
、基板およびその上にあるステンシル構造に低温酸化を
施すことによって、幅がほぼ寸法Ｃに等しい、バーズ・
ピークおよびバーズ・ヘッドのない埋込絶縁分離を成長
させることである。新しいマスクのさらに他の用途は、
基板に対して高度に局在した電気接点を確立するための
、接触（剥離）マスクとしてのものである。マスクの他
の用途は、基板上に幅Ｃの狭い導線または絶縁体線を形
成することである。The new masks serve a variety of purposes. For example, as shown in FIG. 4, it can be used as an ion implantation mask for implanting very narrow, small regions 26 of substrate 10. Other uses for the new mask include:
It is intended as an etch mask to etch very narrow/deep trenches in substrate 10. Other applications can be achieved by low-temperature oxidation of the substrate and overlying stencil structure to create a bird's-eye structure with a width approximately equal to dimension C.
The goal is to grow buried isolation that is free of peaks and bird's heads. Further uses for the new mask include:
It is intended as a contact (stripping) mask to establish highly localized electrical contacts to the substrate. Another use of the mask is to form narrow conducting or insulating lines of width C on a substrate.

目的とする用途の新しいマスクが完成したら、リリース
層１２を利用して、マスクを基板から除去する。リリー
ス層１２を適切なエツチング液、たとえば硝酸、硫酸ま
たは熱石炭酸などの熱酸化酸にさらすことによって、リ
リース層を基板の表面から剥難し、これによって重畳層
１４および関連する側壁２４を除去する。あるいはまた
、感光性層１４およびリリース層１２を、酸素プラズマ
によって同時に除去することもできる。残留する側壁２
４を、機械的手段、ＣＦ４プラズマ・エツチングまたは
液体塩基内での洗浄などによって除去する。Once the new mask for its intended use is complete, the release layer 12 is utilized to remove the mask from the substrate. Exposure of release layer 12 to a suitable etchant, such as a thermal oxidizing acid such as nitric acid, sulfuric acid or hot carbonic acid, strips the release layer from the surface of the substrate, thereby removing superimposed layer 14 and associated sidewalls 24. Alternatively, photosensitive layer 14 and release layer 12 can be removed simultaneously by oxygen plasma. Remaining side wall 2
4 is removed by mechanical means, CF4 plasma etching or washing in liquid base.

第５図には、リソグラフィ単独で可能なものよりも小さ
い開口を有する非腐食性のステンシルを製造する他の方
法が示されている。この方法においては、アンダレイヤ
３０が基板１０とリリース層１２の間に形成される。（
この実施例においては、リリース層１２を省いてもかま
わない。）アンダレイヤ３０は感光性層１４よりもかな
り厚いものである。たとえば、基板材料が半導体である
場合、アンダレイヤはポリイミドまたはフォトレジスト
などの絶縁体である。リリース層１２と、第１図ないし
第４図に関連して上述した態様の側壁２４を有する感光
性層１４とで構成されたステンシル先駆物質を形成した
のち、この方法を改変し、アンダレイヤ３０に異方性エ
ツチングを行なって、層１４内の開口１６をアンダレイ
ヤ３０に転写して、開口３２を得る。アンダレイヤがポ
リイミドの場合、このエツチングはｏ２プラズマを使用
して行なわれる。非腐食性マスク３０の画定後、第４図
の説明で詳述したようにリリース層を剥離することによ
って、重畳構造を除去する。このようにして画定された
アンダレイヤ３０は、たとえば基板１０に深く、きわめ
て幅の狭いトレンチをエツチングするための厚い非腐食
性のマスクとして役立つ。このようなトレンチのひとつ
が、第５図に参照番号３４で示されている。トレンチ３
４は非奮食性マスクがきわめて厚いため、はぼ完璧な垂
直壁を有している。FIG. 5 shows another method of producing a non-corrosive stencil with smaller openings than is possible with lithography alone. In this method, an underlayer 30 is formed between the substrate 10 and the release layer 12. (
In this embodiment, the release layer 12 may be omitted. ) Underlayer 30 is significantly thicker than photosensitive layer 14. For example, if the substrate material is a semiconductor, the underlayer is an insulator such as polyimide or photoresist. After forming a stencil precursor comprising a release layer 12 and a photosensitive layer 14 having sidewalls 24 in the manner described above in connection with FIGS. 1-4, this method is modified to form an underlayer 30. Anisotropic etching is performed to transfer openings 16 in layer 14 to underlayer 30, resulting in openings 32. If the underlayer is polyimide, this etch is done using an O2 plasma. After definition of the non-corrosive mask 30, the overlapping structure is removed by peeling off the release layer as detailed in the description of FIG. The underlayer 30 thus defined serves as a thick, non-corrosive mask for etching deep, very narrow trenches in the substrate 10, for example. One such trench is shown at 34 in FIG. trench 3
No. 4, the non-aspirational mask is so thick that it has almost perfect vertical walls.

それ故、この発明によれば、上述の目的および利点を完
全に満たすことのできる、リソグラフィ画像の大きさを
縮小する方法が提供される。この方法によって、リソグ
ラフィ画像の大きさを、リソグラフィ・ツールの改善に
よってもたらされる改善されたりソグラフイの解像度を
超えたところまで縮小することが可能となる。換言すれ
ば、この方法を広く、しかも将来にわたって適用して、
リソグラフィの画像の解像度を、ツールの改善によって
もたらされるものよりもはるかに進歩させることが可能
となる。Therefore, in accordance with the present invention, there is provided a method for reducing the size of a lithographic image, which fully satisfies the above-mentioned objects and advantages. This method allows the size of lithographic images to be reduced beyond the improved and lithographic resolution provided by improvements in lithographic tools. In other words, by applying this method widely and into the future,
It will be possible to advance the resolution of lithographic images far beyond that provided by improved tools.

Ｆ０発明の効果 この発明はりソグラフイによって可能な大きさよりも小
さなものまで、リソグラフィの解像度を拡張することに
よって、リソグラフィの画像の大きさを削減するという
要望を十分に満たすものである。Effects of the F0 Invention This invention satisfies the need to reduce the size of lithographic images by extending the resolution of lithography to smaller sizes than are possible with lithography.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ないし第４図は、リソグラフィの限界によって決
定されるものよりも小さい開口を有するマスク／ステン
シルを形成するための方法の一実施例を段階的に示す断
面図である。 第５図は、上記の図面で示した処理工程を延長したもの
の断面図である。 １０・・・・基板、１２・・・・リリース層、１４・・
・・結像層、１６．３２・・・・開口、１８・・・・水
平な表面、２０・・・・垂直な表面、２２・・・・コン
フォーマル居、２４・・・・側壁、２６・・・・注入領
域、３０・・・・フンダレイヤ、３４・・・・トレンチ
。 出願人　　インターナショナル・ビジネス・マシーンズ
・コーポレーションFIGS. 1-4 are cross-sectional views step-by-step through one embodiment of a method for forming a mask/stencil with an opening smaller than that dictated by lithography limitations. FIG. 5 is an extended cross-sectional view of the processing steps shown in the above drawings. 10...Substrate, 12...Release layer, 14...
...Imaging layer, 16.32...Aperture, 18...Horizontal surface, 20...Vertical surface, 22...Conformal layer, 24...Side wall, 26 ... Injection region, 30 ... Funder layer, 34 ... Trench. Applicant International Business Machines Corporation

Claims (2)

【特許請求の範囲】[Claims] （１）リソグラフィで得られるよりも小さな開口を有す
るマスクを形成する方法であつて、 感光材料で被覆された基板を用意し、 実質的に垂直な壁と、リソグラフィの解像度の限界によ
って決定される最小の寸法とを有する開口を形成するた
めに上記感光材料にパターンを形成し、 上記の垂直な壁を含む結果構造体上にコンフォーマル層
を形成し、 上記垂直な壁上に上記コンフォーマル層の材料を残存さ
せるように上記コンフォーマル層に異方性エッチングを
施すこと、を特徴とするマスク形成方法。(1) A method of forming a mask with an aperture smaller than that obtained by lithography, the method comprising providing a substrate coated with a photosensitive material, with substantially vertical walls, and determined by the resolution limits of lithography. forming a pattern in the photosensitive material to form an opening having a minimum dimension, forming a conformal layer on the resulting structure including the vertical walls, and forming a conformal layer on the vertical walls; A method for forming a mask, comprising performing anisotropic etching on the conformal layer so that the material remains. （２）上記コンフォーマル層の材料は二酸化シリコン、
Ｓｉ＿ｘＯ＿ｙ、チッ化シリコン、オキシチッ化シリコ
ン、又はポリシリコンであることを特徴とする特許請求
の範囲第（１）項記載のマスク形成方法。(2) The material of the conformal layer is silicon dioxide,
The method for forming a mask according to claim 1, wherein the material is Si_xO_y, silicon nitride, silicon oxynitride, or polysilicon.
JP62117263A 1986-10-28 1987-05-15 Mask formation method Expired - Lifetime JP2553078B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/924,223 US4707218A (en) 1986-10-28 1986-10-28 Lithographic image size reduction
US924223 1986-10-28

Publications (2)

Publication Number Publication Date
JPS63116430A true JPS63116430A (en) 1988-05-20
JP2553078B2 JP2553078B2 (en) 1996-11-13

Family

ID=25449914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62117263A Expired - Lifetime JP2553078B2 (en) 1986-10-28 1987-05-15 Mask formation method

Country Status (4)

Country Link
US (1) US4707218A (en)
EP (1) EP0265638A3 (en)
JP (1) JP2553078B2 (en)
CA (1) CA1250669A (en)

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