JPH03184334A - Manufacture of multistage recessed-gate fet - Google Patents

Abstract

PURPOSE:To manufacture recess grooves in a self-alignment manner with high yield even if multistage recess structure of 3 stages or more is formed by forming assists on the sidewalls of the etched groove formed on a region to be formed with a gate, and repeating recess etching with the assists as etching masks. CONSTITUTION:When an MESFET having a recess structure of a plurality of stages is manufactured, assists 7 are formed on the sidewalls of etched grooves forced on a region to be formed with a gate, and recess etching with the assists 7 as etching masks is repeated to form a multistage recess in a self-alignment manner. For example, after source.drain ohmic electrodes 3 are formed on a GaAs active layer 2, an insulating film 7A made of SiN, SiON, SiO, etc., is laminated on the entire surface, the film 7A is anisotropically etched to form a sidewall assist 7a. Then, with the assist 7a as an etching mask the exposed layer 2 is etched. Further, a similar step is repeated to obtain a multistage recess structure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a multi-stage recess gate FET.

[Conventional technology]

FIGS. 2(a) to 2(O) show conventional multi-stage recess type FETs with two-stage recesses and a GaAs FET as an example.

In the figure, 1 is a semi-insulating GaAs substrate, 2 is a GaAs active layer, 3 is a source/drain ohmic electrode, 4a and 4b are resists, 5a and 5b are first and second recesses, respectively, and 6 is a gate electrode. It's metal.

Next, the manufacturing method will be explained.

As shown in FIG. 2(a), after forming source/drain ohmic electrodes 3 on a semi-insulating GaAs substrate 1 having an active layer 2 on the surface, a first recess having an opening between the ohmic electrodes 3 is formed. A resist pattern 4a for etching is formed. Using this resist pattern 4a as a mask, G
The aAs active layer 2 is etched using an etchant such as CC1t Ft /He mixed gas using, for example, RIE (reactive ion etching) to obtain a structure as shown in FIG. 2(b). Subsequently, when the resist 4a is removed, a one-stage recess structure as shown in FIG. 2(C) is obtained.

Next, resist pattern 4 for second stage recess etching
2(e) by etching GaAs in the same manner as in FIG. 2(b). For example, a recess structure of 5,000 depth as shown in FIG.

Next, as shown in FIG. 2(f), a gate electrode metal 6 is deposited on the entire surface of the wafer using, for example, a vacuum evaporation method to deposit T i / P t /
After laminating Au, the unnecessary metal is removed by removing the resist 4b using a suitable resist removal method, such as immersion in a resist stripping solution, thereby creating a two-stage recessed structure as shown in FIG. 2(g). A FET is obtained.

By using such a recessed structure, the flow of carriers can be made smoother than in a normal FET, and the power efficiency of the FET η η - (microwave power taken out from the drain - input to the gate) Microwave power)/(DC voltage applied to the drain x DC current flowing to the drain side) can be improved.

[Problem to be solved by the invention]

The conventional two-stage recess FET was manufactured as described above, but in Figure 2(d), the first stage recess width was 2 μm.
or less, and even further miniaturized, for example, 2 μm wide
Accurate mask alignment of the step recesses into this was very difficult.

For this reason, a second stage recess is formed outside the first stage recess, resulting in a significant reduction in manufacturing yield.

This invention was made to solve the above-mentioned problems, and in addition to the two-stage recess structure, it also provides smoother flow of carriers and further improves power efficiency.
Even when configuring a multi-stage recess structure of three or more stages,
It is an object of the present invention to provide a method for manufacturing a multi-stage recess gate FET in which each recess groove can be formed in a self-aligned manner with a high yield.

[Means to solve the problem]

The method for manufacturing a multi-stage recess gate (FET) according to the present invention is as follows:
As a mask for recess etching in the second, third, and fourth stages, a side wall assist is formed on the side surface of the existing etching groove, and by using this as an etching mask, multiple recess etching grooves can be formed in a self-aligned manner. It was designed so that it could be formed.

[Function] In this invention, the side wall assist for the etching mask is formed by adding SiN, 5
By repeatedly forming insulating films such as iON and SiO, a multi-stage recess structure is realized.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a multi-stage recess game (FE) according to an embodiment of the present invention.
1(a) to (j), 1 is a semi-insulating GaAs substrate, 2 is a Gaps active layer, 3 is a source/drain ohmic electrode, 5a, 5b
, 5d are the first, second and fourth stage recesses, 6 is the gate electrode metal, 7A and 7B are insulating films layered over the entire area to form sidewall assists, and 7a, 7b, 7c and 7d are each one stage. Side wall assist for eye recess etching, 2nd stage.

This is a side wall assist for third and fourth stage recess etching. 8 is a lift-off resist for forming a gate electrode.

Next, the manufacturing method will be explained.

FIG. 1(a) shows that after forming source/drain ohmic electrodes 3 on GaAs active N2, an insulating film 7A, such as SiN, 5iON, or SiO film, is laminated on the entire surface using the P-CVD method or the like. It is a diagram. In this state, when the insulating film 7A is etched using anisotropic etching, for example, RIE (reactive ion etching), as shown in FIG. An assist 7a is formed.

Next, using this sidewall assist as an etching mask, the exposed GaAs active N2 is etched using an appropriate etching method, such as H
Wet etching is performed using a mixed solution of gSO4 and HtOt aqueous solution to obtain the image shown in FIG. 1(C). Next, as shown in FIG. 1(d), after forming an insulating film 7B on the entire surface as in FIG. 1(a), sidewall assist 7b is formed using RIE method as in FIG. Give form. Subsequently, using the side wall assists 7a and 7b as an etching mask, the exposed GaAs active N2 is etched by the wet etching method as described above, thereby obtaining the second stage recess portion 5b. By repeating these steps, a depth of 5
A multi-stage recess structure (FIG. 1 (8)) of 0.000 mm is obtained.

Next, a resist pattern 8 for forming a gate electrode is applied to the first resist pattern 8.
The metal 6 for the gate electrode, for example, Ti/Pt/Au, is layered over the entire area by vacuum evaporation as shown in Figure 1(i), and then the resist is removed to eliminate unnecessary resist. (Fig. 1 (j)).

In the above embodiments, a GaAs MESFET is used as an example, but the substrate does not have to be GaAs.
It may also be made of nP, InGaAs, Si, or the like.

Furthermore, in the above embodiment, a sidewall assist was also formed on the source/drain ohmic electrode in the first stage recess, and this was used as an etching mask. The pattern may also be used as an etching mask, with the same effect as described above.

In addition, in the above embodiment, Ti/
Although Pt/Au is mentioned above, it goes without saying that this is not limited to this, and the depth of the recess is not limited to 5000 people either.

Further, in the above embodiments, only MESFETs have been described, but it goes without saying that the invention can also be applied to HEMTs.

FIG. 3 shows a method of manufacturing a HEMT having a multi-stage recess structure according to another embodiment of the present invention, in which 11 is a semi-insulating GaAs substrate, 12 is a GaAs active layer, 13 is a source/drain ohmic electrode, 15a, 15b, 15
c and 15d are the first, second, third and fourth recesses, 16 is the gate electrode metal, 17A and 17B are the insulating films layered over the entire area for sidewall assist, 17a and 17
b, 17c, and 17d are side wall assists for the first stage recess etching, and side wall assists for the second, third, and fourth stage recess etching, respectively. 18 is a lift-off resist for forming a gate electrode. 19 is a doped GaAfAs epitaxial layer, and 20 is a secondary electron gas.

Next, the manufacturing method will be explained.

FIG. 3(a) shows that after forming source/drain ohmic electrodes 13 on the GaAs active layer 12, the entire surface is covered with, for example, Si.
P-CVD insulating film 17A such as N, 5iON, SiO film, etc.
FIG. In this state, the insulating film 17A is subjected to anisotropic etching, for example, RIE.
It is known that when etching is performed using the (reactive ion etching) method, a sidewall assist 17a is formed on the sidewall of the ohmic electrode 13, as shown in FIG. 3(b). Using the sidewall assist as an etching mask, the exposed GaAs active layer is etched using a suitable etching method, such as Hz S04. H! Wet etching is performed using a mixed solution with an Oz aqueous solution to obtain the image shown in FIG. 3(C).

Next, as shown in FIG. 3(d), similar to FIG. 3(a),
After forming the insulating film 17B on the entire surface, sidewall assists are formed using the RIE method or the like as in the case of FIG. 3(b) (FIG. 3(e)), and then sidewall assists 17a, 1
Use 7b as an etching mask to remove the exposed G.
By etching the aAs active layer using the wet etching method as described above, the second stage recess portion 15b is obtained (FIG. 3(f)). By repeating these steps, a multi-stage recess structure (FIG. 3 (8)) is obtained. At this time, the depth of the recess etching is set to the inside of the GaAs active layer 12, and for example, about 1000 recesses are formed.

Next, a resist pattern 18 for forming a gate electrode is shaped as shown in FIG.
For example, by layering T i / P t / Au over the entire area by vacuum evaporation (Fig. 3 (i)), then removing the resist and removing unnecessary metal, the desired multi-stage recessed structure can be created. HEMT can be obtained (Fig. 3 (j
)).

〔Effect of the invention〕

As described above, the multi-stage recess gate FET according to the present invention
According to the manufacturing method, since the sidewall assist formed on the recess sidewall is used as an etching mask for forming the multi-stage recess structure, the multi-stage recess structure can be obtained in a self-aligned manner with a high yield.

[Brief explanation of drawings]

FIGS. 1(a) to (j) are process flow diagrams of a method for manufacturing a multi-stage recessed gate FET according to an embodiment of the present invention, and FIGS. 2(a) to (8) are FETs having a conventional two-stage recessed structure. FIGS. 3(a) to 3(j) are process flow diagrams of a method for manufacturing a HEMT with a multi-stage recess structure according to another embodiment of the present invention. In the figure, 1.11 is a semi-insulating GaAs substrate, 2.1
2 is a GaAs active layer, 3.13 is a source/drain ohmic electrode, 4a and 4b are resists, 5a and 5b are recessed portions, 6 and 16 are gate electrode metals, 7A, 7B, 17
A and 17B are insulating films 7a and 7b layered over the entire area to form sidewall assist. 7c, 7d, 17a, 17b, 17c, and 17d are formed side wall assists, and 8.18 is a resist. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) MESF employing a recessed structure with multiple stages
In the ET manufacturing method, an assist is formed on the side wall of an etching groove provided in a region where a gate is to be formed, and multi-stage recesses are formed in a self-aligned manner by repeating recess etching using the side wall assist as an etching mask. A method for manufacturing a multi-stage recessed gate FET, characterized by: