JPH0982725A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method capable of forming a high- performance power GaAs MESFET with a high yield at a low cost. SOLUTION: In a gate electrode forming process of an MESFET, a photoresist film 20 with an opening for a gate forming region is formed on an insulating film 21 deposited over an active layer 2. An opening is provided in the insulating film 21 with the photoresist film 20 as a mask, and a small recess region 31 is formed by performing a first recess etching for the active layer 2 with the insulating film 21 as a mask. Thereafter, the opening width of the insulating film 21 is widened leaving the photoresist film 20 as it is, a second recess etching is performed for the active layer 2, and a large recess region 30 is formed. Since a multistage region of more than 2 steps is formed by using one photomask, the production cost can be reduced. Also, each recess region and gate electrode 33 are formed in a self-matching form, both the yield and performance can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field effect transistor such as a high frequency MESFET formed on a compound semiconductor substrate and a manufacturing method thereof.

[0002]

2. Description of the Related Art A metal-semiconductor contact field effect transistor (hereinafter
The MESFET) is in high demand in the high frequency band as a high gain, high efficiency power device such as a transmission device for mobile communication equipment. This ME
The SFET has a structure in which a gate electrode in Schottky contact is formed on an active region of a compound semiconductor substrate, and a source / drain is formed on both sides of the gate electrode. This MESF
The ET manufacturing method is roughly classified into a method of forming an active layer by epitaxial growth and a method of forming an active layer by implanting impurity ions in a compound semiconductor substrate.

By the way, in order to improve the high frequency characteristics and efficiency of the high output MESFET, it is necessary to improve the characteristics of the MESFET (for example, the transfer conductance gm and K value), and for that purpose, the channel layer is highly concentrated. , It is important to form a thin film. Furthermore, in a power FET, a high gate-drain breakdown voltage (hereinafter B
Vgd) is required to be maintained. However,
The improvement in the breakdown voltage characteristic between the gate and the drain has a trade-off relationship with the improvement in the gm and K values.

In particular, a power FET handling a large signal requires a high gate-drain breakdown voltage.
A structure (hereinafter, referred to as a recess structure) in which the active layer just below the gate electrode is etched and slightly dug from the surface is usually used. In order to solve the above-mentioned trade-off relationship, a high power MESFET often uses a structure in which recess etching is performed twice (hereinafter referred to as a two-step recess structure) as shown in the following conventional example.

A conventional manufacturing method of a high-power MESFET having a two-step recess structure using active layer formation by selective ion implantation will be described below.

First, as shown in FIG. 11A, a photoresist film 103 is formed on one main surface of a semi-insulating GaAs substrate 101 by using a photolithography process, and the photoresist film 103 is used as a mask. As GaAs
Accelerating voltage of 80 k for Si ions in a predetermined area of the substrate 101
Implantation is performed by eV to form the active layer 102.

Next, as shown in FIG. 11B, a photoresist film 10 having openings above both ends of the active layer 102 is formed.
4 as a mask, a high concentration of S is formed on both ends of the active layer 102.
i-ion is injected at an acceleration voltage of 150 keV to
A drain n + layer 105 (high concentration layer) is formed.

Next, as shown in FIG. 11C, a silicon oxide film 106 is deposited on the entire surface of the GaAs substrate 101, annealed at 820 ° C. for 15 minutes with this film as a cap, and implanted. Activated Si.

Next, as shown in FIG. 11D, after removing the silicon oxide film 106, an opening region is formed above the central portion of the active layer 102 except for both ends near the source / drain n + layer 105. Then, a photoresist film 107 is formed.

Then, as shown in FIG. 11E, the first recess etching is performed using the photoresist film 107 as a mask to remove only the vicinity of the surface of the GaAs substrate 101 to remove the large recess region in the first stage. After forming 111
The photoresist film 107 is removed.

Next, as shown in FIGS. 12 (a) to 12 (c), a silicon oxide film 121 is deposited on the entire surface of the GaAs substrate 101, and an opening above the source / drain regions 105 is formed on the silicon oxide film 121. Region photoresist film 120
Is formed, and Au is formed from above the photoresist film 120.
After vacuum deposition of Ge / Ni / Au, sintering is performed in an Ar gas atmosphere at 450 ° C. for 3 minutes to form the source electrode 1.
22 and the drain electrode 123 are formed.

Next, as shown in FIG. 13A, a photolithography process is performed on the silicon oxide film 121 and the electrodes 122 and 123 by opening a gate electrode formation region which is a part of the recess region 111 of the first stage. A resist film 125 is formed.

Then, as shown in FIG. 13B, reactive dry etching (hereinafter abbreviated as RIE) using CF4 gas is performed using the photoresist film 125 as a mask to expose the photoresist film 125 below the opening. The silicon oxide film 121 is removed. In this step, an opening having the same shape as the opening shape of the photoresist film 125 is formed in the silicon oxide film 121 by anisotropic etching.

Next, as shown in FIG. 13C, the photoresist film 125 is directly used as a mask, and a mixed solution of sulfuric acid, hydrogen peroxide, and water is used as an etchant, and the second recess of the active layer 102 is performed. Etching is performed, and the small recess area 13 of the second step is formed in the large recess area 111 of the first step.
Form one.

Finally, as shown in FIG. 13D, a gate electrode 132 that contacts the active layer 102 is formed in the opening of the silicon oxide film 111 in the small recess region 131 of the second stage.

From the above, the FE having a two-step recess structure
T is formed.

[0017]

However, the above-mentioned conventional method of manufacturing an FET having a two-step recess structure has the following problems.

First, the FE formed by the above method
Although T has an effect of improving the breakdown voltage characteristic, the number of steps and the number of photomasks used increase as compared with the manufacturing steps of the FET having the one-step recess structure, and the manufacturing cost rises.

Second, the large recess regions 111 and 2 of the first stage
The alignment accuracy with the small recess area 131 of the tier depends on the accuracy of the photolithography process, but since the relative positions of the two recess areas vary due to mask misalignment or the like in the photolithography process, the FET characteristic Fluctuation occurs.

The present invention has been made in view of the above problems, and an object thereof is to provide an FET having a two-step recess structure.
High-performance power GaAs can be obtained by taking steps to form the FET with the stepped recess structure in the same number of mask steps.
It is to facilitate the manufacture of semiconductor devices such as MESFETs, reduce the cost, and improve the yield.
By improving the shape of the recess area, the power GaA
It is to further improve the breakdown voltage characteristics of a semiconductor device such as an sMESFET.

[0021]

In order to achieve the above object, in the present invention, means relating to the method for manufacturing a semiconductor device according to claims 1 to 6 and semiconductor according to claims 7 to 10 are provided. And means relating to the device.

According to a first method of manufacturing a semiconductor device of the present invention, as described in claim 1, a semiconductor device having a recess structure of at least two stages in a part of a compound semiconductor substrate and functioning as an FET. A first step of forming an active layer to be a channel region on a part of the compound semiconductor substrate, a second step of depositing an insulating film on the active layer, and A third step of forming a photoresist film having an opening in a gate formation region on the insulating film, and etching the insulating film using the photoresist film as a mask to form an opening reaching the active layer, A fourth step of forming a small recess region in the gate formation region by performing etching on the active layer using the insulating film as a mask, and the insulating film with the photoresist film left as it is. Fifth step of laterally etching to widen the opening of the insulating film and then etching the active layer using the insulating film as a mask to form a large recess region including the small recess region And a sixth step of forming a gate electrode on the small recess region.

According to this method, the recess shape of at least two steps can be realized by forming the photoresist film serving as a mask at the time of recess etching only once, so that the number of steps and the number of photomasks can be reduced. Further, since the photoresist film is formed only once, the gate electrode and the small recess region are formed in the center of the large recess region in a self-aligned manner, so that the characteristics can be stabilized. In addition, when the opening of the insulating film is widened after forming the small recess region or when the second recess etching is performed, the peripheral portion of the already formed small recess region is subjected to the etching action from both sides of the upper surface and the side surface. , Its edges are blunted. Therefore, the concentration of the electric field between the active layer and the gate electrode is relaxed, and a highly reliable semiconductor device is formed.

As described in claim 2, in claim 1, anisotropic etching such as dry etching is used in the fourth step, and isotropic etching such as wet etching is used in the fifth step. It is preferred to use reactive etching.

According to this method, the width of the small recess region becomes substantially equal to the width of the gate electrode, a fine recess structure is formed, and variations in the width of the opening of the insulating film and the size of the recess region are reduced. . In addition, when performing the etching for expanding the insulating film and the etching for forming the large recess region, the edge of the peripheral portion of the small recess region is blunted by the isotropic etching, so that the action of claim 1 can be reliably obtained. To be

As described in claim 3, in claim 2, in the second step, it is preferable that a silicon oxide film is formed as the insulating film.

According to a fourth aspect of the present invention, in the first aspect, in the fifth step, the step of etching the insulating film and the active layer is alternately repeated a plurality of times, and 3
It is possible to form a multi-step recess structure having more steps.

By this method, the concentration of the electric field between the active layer and the gate electrode is further alleviated, so that a more reliable semiconductor device is formed.

A second method for manufacturing a semiconductor device according to the present invention is, as described in claim 5, a method for manufacturing a semiconductor device having a plurality of recess regions and functioning as an FET. In this method, a narrowest recess region of the plurality of recess regions is formed on a part of the compound semiconductor substrate, and then a wide recess region is sequentially formed.

By this method, a recess region having a blunted edge is formed in the outermost recess region, so that a highly reliable semiconductor due to relaxation of electric field concentration between the active layer and the gate electrode. The device can be formed. In addition, since the width of the outermost recess region and the final opening width of the insulating film match, when forming the gate electrode on the innermost recess region, the portion where the gate electrode is deposited and the insulating film A sufficient space is secured between the opening wall and the shape of the gate electrode when depositing the gate electrode.

A third method for manufacturing a semiconductor device according to the present invention is, as described in claim 6, a method for manufacturing a semiconductor device having at least one recess region and functioning as a FET. A first step of forming an active layer to be a channel region on a part of the semiconductor substrate, a second step of depositing an insulating film on the active layer, and a gate in the gate forming region on the insulating film. A third step of forming a photoresist film having an opening narrower than the formation region, and etching the insulating film using the photoresist film as a mask to form an opening reaching the active layer, and then performing the photolithography. While the resist film is left, the etching of the active layer and the etching of the insulating film are alternately repeated to widen the opening width of the insulating film and A fourth step of forming an arcuate recess region having a substantially arcuate bottom in a cross section parallel to the channel direction in the conductive layer, and etching the photoresist film to change the opening width of the photoresist film to the gate length. And a sixth step of forming a gate electrode on the arc-shaped recess region.

By this method, the concentration of the electric field at the gate edge is alleviated, so that a highly reliable semiconductor device is formed.

According to a seventh aspect of the present invention, in a semiconductor device which is mounted on a compound semiconductor substrate and functions as an FET, a first semiconductor device according to the seventh aspect is a channel formed in a part of the compound semiconductor substrate. An active layer that functions as a region and a source connected to both ends of the active layer.
A drain layer, a large recess region formed by digging a part of the active layer from the upper end surface of the active layer by a predetermined depth, and a part of the active layer in the large recess region is further digged downward. And a gate electrode contacting the active layer in the small recess region, and the peripheral portion of the small recess region has an edge that is blunted by chemical etching.

With this structure, since the edge of the small recess portion is blunted, the concentration of the electric field between the active layer and the gate electrode is relieved, so that the reliability is improved.

As described in claim 8, in claim 7, the insulating film may be configured to have the same width as the width of the large recess region.

With this structure, it is easy to adopt a step of forming the large recess region formed after the small recess region by etching using the insulating film on the active layer as a mask in the manufacturing process of the semiconductor device. It becomes a structure. Then, since the space between the gate electrode and the insulating film, which is usually formed by lift-off after forming the large recess region, is large, the lift-off can be easily performed. Therefore, the shape of the gate electrode is good, and there is almost no broken portion or high resistance portion and the reliability is high.

According to a ninth aspect of the present invention, in the seventh aspect, the large recess region is made up of a plurality of step portions, and a peripheral edge portion of each step portion is chemically etched to form a blunt edge. Can be configured to have.

With this structure, the concentration of the electric field between the active layer and the gate electrode is further reduced, so that higher reliability can be obtained.

According to a tenth aspect of the present invention, in a semiconductor device mounted on a compound semiconductor substrate and functioning as an FET, the second semiconductor device according to the tenth aspect includes a channel formed in a part of the compound semiconductor substrate. An active layer functioning as a region, source / drain layers connected to both ends of the active layer, and a part of the active layer having a substantially arc-shaped bottom in a cross section parallel to the channel direction. An arc-shaped recess region formed by engraving and a gate electrode contacting the active layer in the arc-shaped recess region are provided.

With this structure, the concentration of the electric field at the gate edge is relaxed, so that extremely high reliability can be obtained.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, a first embodiment will be described. 1A to 1E, 2A to 2D, and 3A and 3B are cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment. .

First, as shown in FIG. 1A, a photoresist film 3 is formed on one main surface of a semi-insulating GaAs substrate 1 using a photolithography process, and the photoresist film 3 is used as a mask. , Si ions are implanted into a predetermined region of the GaAs substrate 1 at an acceleration voltage of 80 keV to form an active layer 2.

Next, a photoresist film 4 having openings above both ends of the active layer 2 is formed, and Si ions are implanted into both ends of the active layer 2 at an accelerating voltage of 150 keV using the photoresist film 4 as a mask. Source / drain n +
A layer 5 (high concentration layer) is formed.

Next, as shown in FIG. 1C, after removing the photoresist film 4, a relatively thin silicon oxide film 6 is deposited on the GaAs substrate 1, and this silicon oxide film 6 is used as a cap. Annealing treatment is performed at 820 ° C. for 15 minutes to activate the implanted Si.

Next, as shown in FIG. 1D, after the thin silicon oxide film 6 is removed, a thick silicon oxide film 21 is deposited on the GaAs substrate 1 and a source / source layer is formed on the silicon oxide film 21. A photoresist film 7 having an opening above the drain n + layer 5 is formed. .

Next, using the photoresist film 7 as a mask, a part of the silicon oxide film 21 is removed by etching to form an opening above the source / drain n + layer 5. Then, AuGe / Ni / Au is vacuum-deposited in this opening, and sintering is performed at 450 ° C. for 3 minutes in an Ar gas atmosphere to form the source electrode 22 and the drain electrode 23.

Next, as shown in FIG. 2A, the active layer 2 is formed on the silicon oxide film 21 and the electrodes 22 and 23.
A photoresist film 20 having an opening above the gate electrode formation region near the center of is formed. At this time, the width of the opening of the photoresist film 20 has the same dimension as the gate length of the gate electrode to be formed, and is 1 μm in this embodiment, for example.
It is a degree.

Next, as shown in FIG. 2B, an opening is formed in the silicon oxide film 21 by reactive dry etching (hereinafter abbreviated as RIE) using CF4 gas using the photoresist film 20 as a mask. This opening is formed with a width substantially the same as the opening width of the photoresist film 20, and has a substantially vertical side wall.

Next, as shown in FIG. 2C, the photoresist film 20 is directly used as a mask, and a mixed solution of sulfuric acid, hydrogen peroxide and water is used as an etchant, and the first recess etching of the active layer 2 is performed. Then, the small recess region 31 is formed in the gate electrode formation region of the active layer 2. The depth of the small recess region 31 is, for example, about 20 to 30 nm.

After that, as shown in FIG. 2D, the photoresist film 20 is used as it is as a mask and wet etching is performed with an HF solution to widen the opening of the silicon oxide film 21.

Next, as shown in FIG. 3A, recess etching is performed again using the mixed solution of sulfuric acid or the like as an etchant, and the large recess region 3 is formed around the small recess region 31.
Form 0. As a result, the small recess region 31 is formed in the large recess region 30. This large recess area 30
Is about 50 nm in this embodiment. Further, the thickness of the active layer 2 is 1 at the portion where the recess region is not formed.
It is about 50 nm. That is, the thickness of the active layer immediately below the gate electrode 32 is about 70 to 80 nm.

Since the edge of the peripheral portion of the small recess region 31 is subjected to the etching action from both the side surface and the upper surface during the etching when the opening of the insulating film 21 is widened and when the large recess region is formed, the edge is sharp. It has been slowed down and has become gentle.

Finally, as shown in FIG. 3B, the gate electrode 33 that contacts the active layer 2 is formed by the lift-off method. The length of the gate electrode 33 is substantially equal to the opening dimension of the photoresist film 20, for example, 1 μm.
It is a degree. As a result, FE with a two-step recess structure
T is formed.

As described above, in the present embodiment, the mask for forming the two recess regions 30 and 31 is 1
Since there are only one photoresist film 20, the number of masks required for manufacturing a semiconductor device having a one-step recess structure is the same. On the other hand, in the conventional manufacturing process described above, FIG.
Two masks are required, the photoresist film 107 shown in (d) and the photoresist film 125 shown in FIG. 13 (c). Therefore, the method of the present embodiment can reduce the number of mask steps and the manufacturing cost as compared with the conventional method. Further, in the conventional manufacturing process, a mask (photoresist film 107) used to form the first-stage large recess region and a mask (photoresist film 12) used to form the second-stage small recess region.
Due to the misalignment with 5), the relative position of each recess region varies. On the other hand, in the method of the present embodiment, since the recess regions 30 and 31 are formed by one mask (photoresist film 20), there is almost no variation in the relative positions of the two. Therefore,
FE due to variation in relative position of each recess area
It is possible to effectively prevent fluctuations in the characteristics of T.

Further, in the above-mentioned conventional manufacturing process, FIG.
As shown in (c), when the second-stage small recess region 131 is formed in the first-stage large recess region 111, the silicon oxide film 121 is formed on the sidewall of the second-stage small recess region 131.
Has been deposited, the small recess area 13
The peripheral portion of 1 has a sharp edge. For it,
In this embodiment, when the small recess region 31 is formed and then the large recess region 30 is formed, the silicon oxide film does not exist above the peripheral portion of the small recess region 31 (see FIG. 3). (See (a)), the etchant removes the edge of the peripheral portion of the small recess region 31 from the side surface and the upper surface, so that the peripheral portion of the small recess region 31 has a blunted gentle edge. Therefore, the concentration of the electric field between the gate electrode 33 and the active layer 2 is relaxed, and the reliability is improved. In addition, each recess area 3
The corners at the bottom of 0 and 31 are not so steep even in the conventional example and the present embodiment,
The present embodiment has a gentler corner portion.

Further, in this embodiment, the silicon oxide film 2 is used.
The side wall of the first opening is at the same position as the peripheral portion of the large recess region 30. On the other hand, as shown in FIG. 13C, in the conventional method, the sidewall of the silicon oxide film 121 is located at the same position as the peripheral portion of the small recess region 131. In other words,
In this embodiment, as compared with the conventional method (see FIGS. 3B and 13D), the gate electrode 33 and the silicon oxide film 2 are formed.
The space between 1 and becomes large. As a result, in the present embodiment, when the gate electrode 33 is formed by the lift-off method, the gate electrode having a good shape can be easily formed, and the disconnection of the gate electrode 33 and the local increase in resistance can be effectively prevented. Can be done.

In this embodiment, the wet etching method is used when the first recess etching is performed.
A dry etching method using Cl2 gas or the like may be used. By adopting the dry etching method, it is possible to easily realize the miniaturization of the width of the gate formation region and the reduction of the variation in the pattern dimension.

(Second Embodiment) Next, a second embodiment will be described with reference to FIG.

Also in this embodiment, FIGS. 1 (a) to 1 (e) and 2 (a) to 2 in the first embodiment described above are used.
The same process as the process shown in (c) is performed. However, in this embodiment, the recess amount in the first recess etching step shown in FIG. 2C is extremely small. Then, in the present embodiment, thereafter, the silicon oxide film 2 shown in FIG.
1 and the step of increasing the opening width of the active layer 2 shown in FIG.
And the step of recess etching are repeatedly performed a predetermined number of times with a small etching amount.

Then, by forming the gate electrode 33 thereafter, the structure shown in FIG. 4, that is, the multi-step recess portion 35 is formed.
Is formed. In this embodiment,
The gate electrode 33 is offset to the source side to improve the drain breakdown voltage and reduce the source side resistance. Note that, in FIG. 4, the depth of the multi-step recess region 35 is exaggerated in order to represent the structural feature, but in reality, the total depth is the total depth of the recess regions in the first embodiment. It may be about the same level (about 70 to 80 nm).

In the multi-step recess structure formed according to the present embodiment, each of the small step portions of the multi-step recess portion 35 has a smooth edge due to repeated etching.
The portion where the electric field is concentrated (the substrate surface having an acute angle) between the gate electrode 33 and the active layer 2 can be particularly effectively reduced, and the reliability can be improved.

(Third Embodiment) Next, a third embodiment will be described.

FIGS. 5 (a) to 5 (e), 6 (a) to 6 (d) and 7 (a) to 7 (d) show the manufacturing process of the semiconductor device in this embodiment. It is sectional drawing shown.

First, in the steps shown in FIGS. 5A to 5E, FIGS. 1A to 1C in the first embodiment described above are used.
The same process as the process shown in (e) is performed. The details thereof have already been described in the first embodiment, and thus redundant description will be omitted.

Further, in the steps shown in FIGS. 6 (a) to 6 (c), FIGS. 2 (a) to 2 (c) in the first embodiment are used.
Perform the same process as. Since the details thereof have already been described, duplicate description will be omitted.

Next, in this embodiment, as shown in FIG. 6D, the photoresist film 20 is once removed.

Next, as shown in FIG.
A photoresist film 40 having an opening at a portion where a recess region of the step is to be formed is formed.

Next, as shown in FIG. 7B, RIE using CF4 gas with the photoresist film 40 as a mask.
By (anisotropic etching), an opening having a width wider than the opening provided in the first recess etching is formed in the silicon oxide film 21. .

Next, as shown in FIG. 7 (c), recess etching is performed again using the mixed solution of sulfuric acid or the like as an etchant to form the second large recess region 30.

Finally, as shown in FIG. 7 (d), a gate electrode 33 is formed, whereby an FET having a two-step recess structure is formed.

In the manufacturing process of this embodiment, two mask processes are required to form the two recess regions 30 and 31, so that the number of mask processes is larger than that in the manufacturing process of the semiconductor device having the one-step recess structure. Will increase,
The portion where the electric field is concentrated (the substrate surface having an acute angle) between the gate electrode 33 and the active layer can be reduced, and the reliability can be improved. Further, since the side wall of the opening of the silicon oxide film 21 is located at the same position as the peripheral portion of the large recess region 30, the gap between the gate electrode 33 and the side wall of the opening of the silicon oxide film 21 becomes large, and the gate electrode 33 formed by the lift-off method. Can be facilitated.

(Fourth Embodiment) Next, a fourth embodiment will be described.

FIGS. 8 (a) to 8 (e), 9 (a) to 9 (a) to (d), and 10 (a) to 10 (c) show manufacturing of the semiconductor device according to this embodiment. It is sectional drawing which shows a process.

First, in the steps shown in FIGS. 5A to 5E, FIGS. 1A to 1C in the first embodiment described above are used.
The same process as the process shown in (e) is performed. The details thereof have already been described in the first embodiment, and thus redundant description will be omitted.

Next, as shown in FIG. 9A, a photoresist film 20 having an opening above the gate formation region is formed on the silicon oxide film 21 and the electrodes 22 and 23.
Here, as a feature of this embodiment, the photoresist film 2
The width dimension of the zero opening 20a is smaller than the gate length dimension of the gate electrode to be formed. For example, while the gate length of the gate electrode is about 1 μm,
The width of the opening 20a is set to about 0.2 μm.

Next, as shown in FIG. 9B, RIE using CF 4 gas with the photoresist film 20 as a mask.
Then, an opening is formed in the silicon oxide film 21. The width of the opening 21a of the silicon oxide film 21 is almost the same as the width of the opening 20a of the photoresist film 20,
It is narrower than the gate length of the gate electrode to be formed.

Next, as shown in FIG. 9C, the first recess etching of the active layer 2 is performed with a mixed solution of sulfuric acid, hydrogen peroxide and water, and then silicon oxide is oxidized by wet etching with an HF solution. Expand the open area of the membrane. By performing this recess etching and the etching for widening the opening of the silicon oxide film 21 for an extremely short period of time, an arc-shaped recess region 36 having a substantially arc-shaped bottom in the cross section shown in FIG. 9C is formed. To be done. The arc-shaped recess region 36 can be regarded as the one in which each step of the multi-step recess region 35 in the second embodiment is smoothed.

After that, as shown in FIG. 9D, the opening width of the photoresist film 20 is expanded to a dimension equal to the gate length of the gate electrode by oxygen plasma. In this embodiment, the width is expanded to about 1 μm.

Next, as shown in FIG. 10 (a), recess etching is performed again with the mixed solution of sulfuric acid or the like,
The flat recess region 37 of the first step is formed.

Next, as shown in FIG. 10B, the silicon oxide film 21 is etched again to form a wider opening 2.
After forming 1c, recess etching is performed to form a second flat recess region 38. Note that FIG. 10 (b)
In FIG. 2, the depth of each recess region is exaggerated in order to represent the structural characteristics. However, in reality, the total depth of the recess region is the same as the total depth of the recess region in the first embodiment. It may be about (70 to 80 nm).

Finally, as shown in FIG. 10C, a gate electrode 33 is formed, and a FET having an arc-shaped recess region is formed in addition to the two-step recess structure.

FET formed as in this embodiment
Then, since the portion directly below the gate electrode 33 can be formed in an arc shape, the electric field concentration at the gate edge portion can be alleviated and the reliability can be improved.

In the present embodiment, wet etching was adopted when performing the first recess etching, but if dry etching using Cl 2 gas or the like is used, the gate formation region width can be reduced and the pattern size can be reduced. Variations can be easily realized.

Further, in this embodiment, two flat recess regions 37 and 38 are formed in addition to the arc-shaped recess region 36, but one flat recess region may be used, or the arc-shaped recess region may be omitted. It may not be present when it is big enough and deep.

(Other Embodiments) In each of the above embodiments, the MES in which the active layer and the like are formed by using ion implantation.
The case of the FET has been described, but the MESFE in which the substrate region, the active layer, and the like are formed by using epitaxial crystal growth.
The present invention can be applied to the case of T as well.

In each of the above-described embodiments, the case where only the n-type region is provided as the active layer has been described, but a depletion layer formed as a pn junction by embedding a p-type layer under the n-type active layer. Alternatively, a p-layer embedded structure in which the n-type active layer is effectively thinned may be employed. It is also possible to adopt a structure in which a p-type active layer is used instead of the n-type active layer.

[0087]

According to the first aspect of the present invention, as a method of manufacturing a semiconductor device that functions as an FET on a part of a compound semiconductor substrate, an opening is formed in an insulating film formed on an active layer using a photoresist film as a mask. After that, a small recess region is formed in the active layer by using the insulating film as a mask, then the width of the opening of the insulating film is widened, and a large recess region including the small recess region is formed in the active layer, and then on the small recess region. Since the gate electrode is formed, at least two steps of recess shapes can be realized by using one photomask, the number of steps and the number of photomasks can be reduced, and the large recess area and small recess area can be achieved. By forming the recess region and the gate electrode in a self-aligned manner, a semiconductor device having stable characteristics can be manufactured. In addition, by blunting the edge of the small recess region, the concentration of the electric field between the activation layer and the gate electrode is alleviated, and a highly reliable semiconductor device can be manufactured.

According to a second aspect, in the first aspect, anisotropic etching is used when forming the opening in the insulating film and forming the small recess region, and isotropic when expanding the opening of the insulating film. Since the characteristic etching is used, it is possible to improve the dimensional accuracy of each part.

According to a fourth aspect of the present invention, the step of etching the insulating film and the active layer is alternately repeated a plurality of times to form a multi-step recess structure of three or more steps. By further relaxing the concentration of the electric field between the gate electrode and the gate electrode, a more reliable semiconductor device can be manufactured.

According to a fifth aspect of the present invention, as a method of manufacturing a semiconductor device having a plurality of recessed regions in a part of a compound semiconductor substrate and functioning as an FET, the recessed region having the narrowest width among the recessed regions is formed. After the formation, since the recess regions having a wider width are sequentially formed, a small recess region having a blunted edge is formed in the recess region serving as the outermost region, thereby forming the active layer and the gate electrode. It is possible to manufacture a highly reliable semiconductor device by relaxing electric field concentration during the period.

According to a sixth aspect of the present invention, as a method of manufacturing a semiconductor device which functions as an FET on a part of a compound semiconductor substrate, a photoresist having an opening width narrower than a gate length is formed in an insulating film formed on an active layer. After the opening is formed using the film as a mask, recess etching of the active layer and etching to widen the opening of the insulating film are alternately repeated using the insulating film as a mask to form an arc-shaped recess region, and then the opening width of the photoresist film is formed. Since the gate electrode is formed so as to be equal to the gate length, and then the gate electrode is formed on the arc-shaped recess region, the concentration of the electric field at the gate edge can be relaxed, and thus the semiconductor device with extremely high reliability can be obtained. Can be manufactured.

According to a seventh aspect, in a semiconductor device mounted on a compound semiconductor substrate and functioning as an FET, an active layer functioning as a channel region, a source / drain layer, and a large part of the active layer are dug. A recess region, a small recess region formed by further engraving a part of the large recess region, and a gate electrode contacting the active layer in the small recess region are provided, and the peripheral portion of the small recess region is chemically etched to be dulled. Since the edge is provided, the concentration of the electric field between the active layer and the gate electrode is alleviated, so that the reliability can be improved.

According to the eighth aspect, since the width of the insulating film is the same as the width of the large recess region in the seventh aspect, the shape of the gate electrode and the reliability can be improved. it can.

According to the ninth aspect, in the seventh aspect, the large recess region is constituted by a plurality of steps having chemical-etched and blunted edges. Therefore, the active layer and the gate electrode are formed. It is possible to further reduce the concentration of the electric field during the period, and it is possible to exhibit higher reliability.

According to the tenth aspect, in a semiconductor device mounted on a compound semiconductor substrate and functioning as an FET,
Since the active layer, the source / drain layer, the arc-shaped recess region formed by digging a part of the active layer, and the gate electrode contacting the active layer in the arc-shaped recess region are provided, The reliability can be improved by relaxing the concentration of the electric field at the edge.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an FET showing steps of forming a source electrode and a drain electrode in a manufacturing process of an FET according to a first embodiment.

FIG. 2F is a view showing a process up to forming a first-stage small recess region in the FET manufacturing process according to the first embodiment;
It is sectional drawing of ET.

FIG. 3 is a cross-sectional view of the FET showing the steps up to forming the gate electrode in the step of manufacturing the FET according to the first embodiment.

FIG. 4 is a cross-sectional view showing the structure of the FET according to the second embodiment.

FIG. 5 is a cross-sectional view of the FET showing a step of forming a source electrode and a drain electrode in a step of manufacturing the FET according to the third embodiment.

FIG. 6 is a cross-sectional view of the FET showing a step of removing the photoresist film for forming the small recess region in the step of manufacturing the FET according to the third embodiment.

FIG. 7 is a cross-sectional view of the FET showing a step up to forming a gate electrode in the step of manufacturing the FET according to the third embodiment.

FIG. 8 is a cross-sectional view of the FET showing a step of forming a source electrode and a drain electrode in a step of manufacturing the FET according to the fourth embodiment.

FIG. 9 is a cross-sectional view of the FET showing a step of forming an arc-shaped recess region in the step of manufacturing the FET according to the fourth embodiment.

FIG. 10 is a cross-sectional view of the FET showing a step up to forming a gate electrode in the step of manufacturing the FET according to the fourth embodiment.

FIG. 11 is a cross-sectional view of the FET, showing the steps up to forming the first-stage large recess region in the conventional FET manufacturing process.

FIG. 12 shows a source electrode in a conventional FET manufacturing process,
It is sectional drawing of FET which shows the process until a drain electrode is formed.

FIG. 13 is a cross-sectional view of the FET showing the steps up to forming the gate electrode in the conventional FET manufacturing steps.

[Explanation of symbols]

 1 GaAs substrate 2 active layer 3 photoresist film 4 photoresist film 5 source / drain n + layer 6 silicon oxide film 7 photoresist film 8 drain electrode 20 photoresist film 21 silicon oxide film 22 source electrode 23 drain electrode 30 large recess area 31 Small Recess Area 33 Gate Electrode 35 Stepped Recess Area 36 Arc Recess Area

Claims (10)

[Claims] 1. An FE having a recess structure of at least two stages.
A method of manufacturing a semiconductor device functioning as T, comprising: a first step of forming an active layer to be a channel region in a part of a compound semiconductor substrate; and a second step of depositing an insulating film on the active layer. And a third step of forming a photoresist film in which a gate formation region is opened on the insulating film, and an opening reaching the active layer by etching the insulating film using the photoresist film as a mask. After the formation, a fourth step of forming a small recess region in the gate formation region by etching the active layer using the insulating film as a mask, and the insulating film in the lateral direction while leaving the photoresist film left After etching to widen the width of the opening of the insulating film, the active layer is etched using the insulating film as a mask to cover the small recess region. A fifth step of forming a recess region, a method of manufacturing a semiconductor device characterized by and a sixth step of forming a gate electrode on the small recess area. 2. The method of manufacturing a semiconductor device according to claim 1, wherein anisotropic etching such as dry etching is used in the fourth step, and isotropicity such as wet etching is used in the fifth step. A method of manufacturing a semiconductor device, characterized by using etching. 3. The method for manufacturing a semiconductor device according to claim 2, wherein in the second step, a silicon oxide film is formed as the insulating film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the fifth step, a step of etching the insulating film and the active layer is alternately repeated a plurality of times to form a multi-step recess structure of three steps or more. A method of manufacturing a semiconductor device, comprising: 5. A method of manufacturing a semiconductor device having a plurality of recessed regions and functioning as an FET, wherein a narrowest recessed region among the plurality of recessed regions is formed on a part of a compound semiconductor substrate. After the formation, a method of manufacturing a semiconductor device is characterized in that a recess region having a wider width is sequentially formed. 6. An FE having at least one recess region
A method of manufacturing a semiconductor device functioning as T, comprising: a first step of forming an active layer to be a channel region in a part of a compound semiconductor substrate; and a second step of depositing an insulating film on the active layer. And the step of forming a photoresist film on the insulating film, in which a region narrower than the gate formation region is opened in the gate formation region.
And the etching of the insulating film using the photoresist film as a mask to form an opening reaching the active layer, and then etching the active layer and the insulating film with the photoresist film left. A fourth step of alternately repeating etching and expanding the opening width of the insulating film and forming an arc-shaped recess region having a substantially arc-shaped bottom in a cross section parallel to the channel direction in the active layer; A fifth step of etching the photoresist film to expand the opening width of the photoresist film until it becomes equal to the gate length, and a sixth step of forming a gate electrode on the arc-shaped recess region.
And a method for manufacturing a semiconductor device. 7. A semiconductor device mounted on a compound semiconductor substrate and functioning as an FET, wherein an active layer formed in a part of the compound semiconductor substrate and functioning as a channel region, and a source connected to both ends of the active layer. A drain layer, a large recess region formed by digging a part of the active layer from the upper end surface of the active layer to a predetermined depth, and a part of the active layer in the large recess region further digging downward And a gate electrode in contact with the active layer in the small recess region, wherein a peripheral portion of the small recess region has an edge that is blunted by chemical etching. Semiconductor device. 8. The semiconductor device according to claim 7, wherein the insulating film has the same width as the width of the large recess region. 9. The semiconductor device according to claim 7, wherein the large recess region is composed of a plurality of step portions, and a peripheral portion of each step portion has an edge which is blunted by chemical etching. Semiconductor device. 10. A FET mounted on a compound semiconductor substrate
In the semiconductor device functioning as a device, an active layer formed on a part of the compound semiconductor substrate and functioning as a channel region, source / drain layers connected to both ends of the active layer, and a part of the active layer. An arc-shaped recess region formed by digging so as to have a substantially arc-shaped bottom portion in a cross section parallel to the channel direction, and a gate electrode contacting the active layer in the arc-shaped recess region. Characteristic semiconductor device.