JP3381694B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device suitable for use in a FET having a recess structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art MESFET (Metal-Semiconductor Fiel) using a compound semiconductor such as gallium arsenide (GaAs)
d Effect Transistor) is used as a low noise, high frequency FET. This type of device is an n ⁺ GaA formed for the purpose of reducing the parasitic resistance between the source and the gate.
The s layer and the gate electrode are provided separately from each other to form a so-called recess structure.

A conventional recess structure FET is shown in FIG.
And FIG. 7 will be described. FIG. 6 shows a two-step recess structure FET, which is formed by anisotropic etching using citric acid.
A stepped recess is formed and then a gate electrode is buried therein. FIG. 7 shows the invention disclosed in Japanese Patent Laid-Open No. 9-232336, in order to avoid the influence of a surface depletion layer.
The structure is such that the gate electrode is embedded.

[0004]

The conventional FET having such a recess structure has the following problems. First, FIG.
In the conventional example shown in (1), since the recess structure is formed by overetching with citric acid, the recess structure has an inverse taper shape, and the gate formation surface (GaAs substrate surface) next to the gate electrode 9 is formed. Exposed. In this portion, the surface depletion layer spreads to the channel, so that there is a problem that the effective cross-sectional area of the current path between the gate and the source and between the gate and the drain is confined by the surface depletion layer and the on-resistance increases. .

Further, in the conventional example shown in FIG. 7, there are GaAs layers on both sides of the buried gate electrode 9 and
Although it is possible to reduce the on-state resistance because the gate electrode 9 is buried deeply, there is a problem that the GaAs layer having a large relative permittivity is located next to the gate electrode 9 and the gate capacitance becomes large.

The present invention has been made in view of the above problems, and its main purpose is to provide a semiconductor device in which the surface depletion layer does not increase the on-resistance and does not increase the gate capacitance. And to provide a manufacturing method thereof.

[0007]

In order to achieve the above object, according to a first aspect of the present invention, at least a gate recess embedding layer having a predetermined opening is formed on a GaAs substrate, and the gate recess embedding layer is formed. In the semiconductor device having a recess structure in which a gate electrode is formed in the opening of the layer,
The gate recess cross-section of the opening side wall of the buried layer, forms a concave shape pushed out toward the center of the opening at the bottom and the surface layer portion of the gate recess buried layer, said gate
Gate recess exposed from the opening of the recess buried layer
The gate electrode is arranged so as to cover the entire bottom surface of the portion and to form a gap between the gate recess burying layer and a part of the side surface of the gate electrode.

The present invention, in a second aspect, comprises GaAs
At least a first AlGaAs stopper layer, a second AlGaAs stopper layer having an Al composition ratio smaller than that of the first AlGaAs stopper layer, and a gate recess burying layer are laminated in this order on the substrate, and the gate recess burying layer is formed. A semiconductor device having a recess structure, in which a gate electrode is formed in a predetermined opening provided in the second AlGaAs stopper layer, wherein a cross section of a side wall of the opening of the gate recess filling layer is the gate recess filling. The bottom and surface layers of the layer have a concave shape protruding toward the center of the opening, and the gate recess embedded layer and the second AlGaAs are formed.
Of the gate recess portion exposed from the opening of the stopper layer
The gate electrode is arranged so as to cover the entire bottom surface and to form a gap between the gate recess burying layer and a part of the side surface of the gate electrode.

According to a third aspect, the present invention provides a method for manufacturing a semiconductor device. The method comprises: (a) A for etching at least a channel layer and a buried layer on a GaAs substrate.
lGaAs stopper layer, gate recess buried layer, cap layer etching AlGaAs stopper layer, and n ⁺ GaAs
A step of laminating a cap layer in this order, and (b) using the AlGaAs stopper layer for etching the cap layer as an etching stopper, forming a predetermined opening in the n ⁺ GaAs cap layer to form a first-stage recess portion. And (c) a predetermined opening is formed in the gate recess buried layer inside the opening of the n ⁺ GaAs cap layer using the AlGaAs stopper layer for etching the buried layer as an etching stopper to form two steps. A step of forming an eye recess portion, (d) a step of forming a gate electrode in the opening of the gate recess burying layer, and (e) a step of forming the n ⁺ Ga.
A method of manufacturing a semiconductor device having a recess structure, which comprises at least a step of forming a source / drain electrode on an upper layer of an As cap layer, the method comprising: forming an opening in the gate recess embedded layer in the step (c). Etching is performed using an etching solution containing citric acid under predetermined conditions such that the cross-sectional shape of the side surface of the opening is a concave surface, and when forming the gate electrode in the step (d), the gate recess embedded layer is formed.
The entire bottom surface of the gate recess exposed from the opening
The gate electrode is disposed so as to cover the gate electrode and to form a gap between the gate recess and the buried layer in a part of the side surface of the gate electrode.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Recessed structure FET according to the present invention
In a preferred embodiment thereof, when forming an opening in a gate recess embedding layer (14 in FIG. 1) formed on a GaAs substrate, the cross-sectional shape of the side surface of the opening is such that the bottom and surface layer portions of the gate recess embedding layer are At the center of the opening, the shape of the V- shaped
The bottom surface of the gate recess exposed from the opening in the buried layer.
The gate electrode (9 in FIG. 1) while covering the surface
On the side surface of the gate recess embedded layer (Fig. 1
By disposing the gate electrode so as to form No. 10), the on-resistance is reduced and the increase of the gate capacitance is prevented.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the embodiment of the present invention described above in more detail, an embodiment of the present invention will be described below with reference to the drawings.

[Embodiment 1] An FET having a recess structure according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 shows the F of the recess structure according to the first embodiment.
FIG. 4 is a cross-sectional view schematically showing the structure of ET, and FIG.
FIG. 7A is a process sectional view showing the manufacturing process. Note that FIG.
3 and FIG. 3 show a series of manufacturing steps, which are divided for convenience of drawing.

First, the ON resistance and high frequency characteristics of the FET will be described. Considering the parts other than directly under the gate and under the ohmic electrode among the components constituting the on-resistance of the FET, the influence of the surface depletion layer can be cited as a factor that increases the on-resistance. The semiconductor surface is exposed between the gate and the source and between the gate and the drain, but in this case, since the potential of the semiconductor surface rises to the vacuum level,
Carrier depletion occurs within a depth range of about 100 to 300 nm from the surface. When this depletion occurs, no current flows in that region, so the cross-sectional area of the current path between the source and drain becomes smaller.

Therefore, considering the reduction of the on-resistance, it is one means of reducing the on-resistance that the FET structure is not affected by the surface depletion layer. That is, the gate is deeply buried and the channel of the FET is reduced. It is important to have a depth that is not affected by the surface depletion layer.

On the other hand, the high frequency characteristics of the FET (for example, FE
Cutoff frequency when T is used as an amplifier, FET
It is important to reduce the gate capacitance, because the gate capacitance affects the frequency characteristics of the pass loss when is used as a switch. Here, in the gate capacitance of the FET, the FE other than the parasitic capacitance component due to the electrode or the like is used.
Considering the capacitance due to the T intrinsic portion as the capacitance of the capacitor formed by the gate electrode and the channel layer that is not depleted, embedding the gate to reduce the on-resistance is FE.
The surface area of the gate electrode in the T intrinsic part is increased,
As a result, the gate capacitance increases.

When considering the gate capacitance as the capacitance of the capacitor formed by the gate electrode and the channel layer, the gate electrode area is reduced or the distance between the gate electrode and the channel is increased in order to reduce the capacitance. Alternatively, the relative dielectric constant between the gate electrode and the channel layer may be lowered. However, in order to reduce the area of the gate electrode, the gate length is shortened, and increasing the distance between the gate electrode and the channel layer has a great influence on the DC characteristics such as the pinch-off property of the FET and the threshold voltage. Therefore, it cannot be easily changed only for the purpose of reducing the gate capacitance.
Therefore, the method of lowering the relative dielectric constant between the gate electrode and the channel layer is most effective for reducing the gate capacitance.

Here, the relative permittivity of GaAs is about 13, and by making this into a vacuum (air) having a relative permittivity of 1,
A large reduction in gate capacitance can be expected. Since the bottom of the gate electrode is formed on the GaAs substrate, the Ga
Although As cannot be replaced with a vacuum, it is possible to create a vacuum on the side surface of the gate electrode. That is, by removing GaAs on the side surface of the gate electrode, it is possible to reduce the gate capacitance without significantly changing other characteristics of the FET.

As a specific method thereof, selective etching using citric acid is adopted when forming a gate recess of an FET having a buried gate structure, and a gate electrode is formed by sputtering or vapor deposition after the recess is formed. In this way, by using low-temperature citric acid and controlling the etching time, the etching shape on the side surface of the gate recess becomes a V-shape, and voids can be formed here, and a V-shape can be formed. By doing so, since the side etching does not proceed to the bottom surface of the gate recess portion, the gate electrode can be formed on the entire gate formation surface without exposing the GaAs substrate on the gate formation surface beside the gate electrode.

The structure of the FET formed by the above selective etching using citric acid will be described with reference to FIG. First, as shown in FIG. 1, on the semi-insulating GaAs substrate 1, a buffer layer 2, a channel layer 3, and AlGaA are formed.
s stopper layer 4, gate recess burying layer 14, AlGaA
The s stopper layer 5 and the n ⁺ GaAs cap layer 6 are sequentially formed, and the AlGaAs stopper layer 5 and the n ⁺ GaAs cap layer 6 are processed into a predetermined shape to form the first-stage recess portion 1
3 is formed.

The gate recess burying layer 14 is selectively etched using citric acid to form a gate recess portion. This selective etching using citric acid is performed by using a mixture of citric acid, hydrogen peroxide solution and water cooled to about 5 ° C. as an etchant. When the etchant is used to etch a (100) GaAs substrate, The side surface of the etched portion has a V-shape formed by the (111) plane.

Further, GaAs and Al of this etchant
_{Since the} etching rate ratio to _0.7 Ga _0.3 As is 1:20 or more, the AlGaAs layer 4 acts as an etching stopper layer in the GaAs substrate 1 in which the AlGaAs layer 4 is arranged at a desired depth. In this case, the side surface of the etched portion remains in a V shape when overetching is not performed, but when overetching is performed for a long time, the shape of the side surface becomes an inverse taper shape formed by the (111) plane. .

That is, as shown in FIG. 1, the AlGaAs layer 4 is provided to the depth at which the gate is to be buried, and the GaAs substrate 1 is etched using the above-described etchant for a predetermined etching time that does not result in overetching. As a result, the shape of the side surface of the gate recess portion becomes a V shape surrounded by the (111) plane as shown in FIG. At this time, if over-etching is performed, the side surface of the gate recess portion becomes an inverse taper type, and the bottom surface of the etching portion expands, so it is necessary to control the etching time.

The formation of the gate recess portion 12 does not have to be limited to etching with citric acid, and may be any etching so that the side surface of the gate recess portion does not spread and side etching proceeds only on the side surface. Further, the depth of the gate recess portion 12 is appropriately set to a depth at which the influence of the surface depletion layer does not reach the channel layer 3, and its optimum value varies depending on the impurity concentration and the like.
It is set to about 0 to 300 nm.

Then, a gate electrode such as TiAl or WSi is formed in the gate recess portion by a vapor deposition method or a sputtering method. The gate electrode 9 is the gate recess portion 1
Make sure to cover the entire bottom surface of 2.

Here, it should be noted that the bottom surface of the etched portion does not spread when the gate recess 12 is formed. If the bottom surface spreads, it becomes difficult to cover the entire bottom surface of the gate recess portion 12 with the gate electrode when forming the gate electrode. Therefore, if there is a portion of the bottom surface of the gate recess 12 that is not covered with metal, even if the gate 9 is buried to avoid the influence of the surface depletion layer, the surface depletion occurs in the exposed portion of the GaAs surface beside the gate. This is because the layer spreads to the channel and the effect of filling the gate is lost.

Next, a method of manufacturing the FET of this embodiment will be described with reference to FIGS. The first embodiment relates to a technique of forming MESFET on a GaAs substrate.

First, as shown in FIG. 2A, a buffer layer 2, a channel layer 3 and an A layer are formed on a semi-insulating GaAs substrate 1.
lGaAs stopper layer 4, gate recess burying layer 14, A
lGaAs stopper layer 5 and n ⁺ GaAs cap layer 6
Are sequentially formed using a known technique. After that, the AlGaAs stopper layer 5 and the n ⁺ GaAs are formed by a patterning technique and an etching technique using a photoresist or the like.
The cap layer 6 is processed into a predetermined shape, and the first-stage recess portion 1
3 is formed.

The selective dry etching technique using SF ₆ + BCl ₃ gas or the like can be used by arranging the AlGaAs layer 5 at a desired depth where the first-step recess 13 is to be dug. Yes, at this time, etching stops at the AlGaAs layer 5. This AlGaAs
The Al composition ratio of the layer 5 is preferably about 0.2,
Any composition ratio that can serve as a stopper layer for selective etching may be used. Further, the etching gas is not limited to the SF ₆ + BCl ₃ gas, and any etching gas can be used. Further, the method is not limited to the selective etching, and any method capable of forming the first-stage recess portion 13 may be used.

Next, as shown in FIG. 2B, the photoresist 11 is patterned according to the opening width of the gate recess portion 12, and thereafter, selective anisotropic etching using citric acid is performed. Here, a mixed solution of citric acid, hydrogen peroxide and water is used as an etching solution at 5 ° C.
Cool down to a certain degree. When etching is performed using this solution as an etchant, the etching is anisotropic etching that reflects the crystal orientation, and the side surface shape of the etched portion is (11
1) It becomes a V shape formed by the surface.

Further, by arranging the AlGaAs layer 4 at a desired depth where the gate recess portion 12 is desired to be dug, the etching can be stopped at the AlGaAs layer 4. The Al composition ratio of the AlGaAs layer 4 is 0.
About 7 is preferable, but the composition ratio is not limited to 0.7 as long as it is a composition ratio that can serve as a stopper for the selective etching by the etchant, and the shape of the side surface of the gate recess is (111) plane when overetching is performed for a long time. Since it will be an inverse taper type manufactured by, it is necessary to avoid overetching.

Incidentally, what is necessary in forming the gate recess 12 is that the bottom of the gate recess 12 does not expand beyond the opening size of the photoresist 11 and side etching is performed. ,
If it is a method that satisfies this condition, it is not necessary to limit it to an etchant using citric acid, and it is not necessary for the side surface shape to be a V shape.

After that, as shown in FIG. 3C, after forming the gate recess portion 12, a metal capable of forming a Schottky junction with GaAs, such as Ti, is formed by vapor deposition or a sputtering method, and the metal other than the gate electrode portion is formed. The metal is removed together with the photoresist by the lift-off method. After that, FIG.
As shown in (d), the source electrode 7 and the drain electrode 8
To complete the FET.

As described above, in the FET of this embodiment, when the gate recess portion 12 is formed, etching is performed under a predetermined condition using an etching solution containing citric acid, so that the void 10 is formed only on the side surface of the gate electrode 9. Therefore, the gate capacitance can be reduced without increasing the on-resistance due to the surface depletion layer.

In this embodiment, M on the GaAs substrate is used.
Although the ESFET has been described, the present invention is not limited to the above embodiments, other semiconductor materials can be used as the substrate material, and the MESF can be used as the element structure.
It can be applied not only to ET but also to FETs of other structures such as HEMT.

[Second Embodiment] Next, an FET according to a second embodiment of the present invention will be described with reference to FIGS. 4 and 5. 4 and 5 show an FE according to the second embodiment of the present invention.
It is a process cross-sectional view schematically showing a manufacturing method of T, and is a diagram for convenience of drawing. The difference between this embodiment and the first embodiment described above is that in this embodiment, after the citric acid etching, further etching is performed to further reduce the gate capacitance. The structure of the part, the manufacturing method and the like are the same as those in the first embodiment.

First, as shown in FIG. 4A, on the semi-insulating GaAs substrate 1, a buffer layer 2, a channel layer 3 and an A layer are formed.
lGaAs stopper layer 4, gate recess burying layer 14, A
lGaAs stopper layer 4 and AlGaAs stopper layer 15
And n ⁺ GaAs cap layer 6 are sequentially formed by using a known technique. After that, the patterning technology and etching technology using photoresist etc.
The stopper layer 5 and the n ⁺ GaAs cap layer 6 are processed into a predetermined shape to form the first-stage recess portion 13.

The selective dry etching technique using SF ₆ + BCl ₃ gas or the like can be used by arranging the AlGaAs layer 5 at a desired depth where the first-step recess 13 is to be dug. Yes, at this time, etching stops at the AlGaAs layer 5. In addition, AlGaA
Similar to the first embodiment, the Al composition ratio of the s layer 5 and the etching gas may have other conditions.

Next, as shown in FIG. 4B, the photoresist 11 is patterned according to the opening width of the gate recess 12, and selective anisotropic etching using citric acid is performed. As the etching liquid, a mixed liquid of citric acid, hydrogen peroxide water and water was added in the same manner as in the first embodiment.
When the one cooled to about 0 ° C. is used, the etching is anisotropic etching that reflects the crystal orientation, and the side surface shape of the etched portion is a V-shape formed by the (111) plane.

Further, by disposing the AlGaAs layer 4 at a desired depth where the gate recess 12 is desired to be dug, the etching can be stopped at the AlGaAs layer 4. At this time, the Al composition ratio of the AlGaAs layer 15 is set to 0.
If it is set to 2, the AlGaAs layer 15 cannot be a stopper layer for citric acid etching, and is therefore etched with citric acid.

The Al composition ratio of the AlGaAs layer 4 is preferably about 0.7, but the composition ratio is not limited to 0.7 as long as it can serve as a stopper for selective etching with this etchant. If overetching is performed for a long time, the shape of the side surface of the gate recess becomes an inverse taper type formed by the (111) plane as described above.
It is similar to the embodiment of.

Here, in this embodiment, as shown in FIG. 4C, side etching is performed by using selective dry etching using SF ₆ + BCl ₃ gas or the like. That is, since selective dry etching using SF ₆ + BCl ₃ gas or the like can serve as a stopper layer when the Al composition ratio of AlGaAs is 0.2 or more, AlGaA
Neither the s layer 4 nor the AlGaAs layer 15 is etched, and the side etching is performed only on the gate-embedded GaAs layer 16.

Next, as shown in FIG. 5D, after forming the gate recess 12, a metal capable of forming a Schottky junction with GaAs, such as Ti, is formed by vapor deposition, sputtering, or the like, and a portion other than the gate electrode portion is formed. The metal shown in FIG. 5E is formed by removing the metal together with the photoresist by the lift-off method, and then forming the source electrode 7 and the drain electrode 8.
Is completed.

In this embodiment, the ME on the GaAs substrate is also used.
Although the SFET has been described, the present invention is not limited to the above-described embodiment, and other semiconductor materials are used as the substrate material, and the present invention can be applied to FETs having other structures such as HEMT.

By thus forming the gate in the buried structure, the influence of the surface depletion layer does not affect the channel between the gate and the source and between the gate and the drain, and the current path is not confined by the surface depletion layer. ON resistance can be reduced, and since the relative permittivity of the void 10 beside the gate buried portion is 1, the gate capacitance can be made smaller than that of the structure having no void beside the gate buried portion. be able to.

Further, in comparison with the above-mentioned first embodiment,
Although the process becomes a little complicated, the gap beside the gate electrode can be widened, so that the gate capacitance can be further reduced.

[0046]

As described above, according to the structure of the present invention, the on-resistance of the FET can be reduced, and
This has the effect of reducing the gate capacitance.

The reason is that the buried structure of the gate prevents the influence of the surface depletion layer from affecting the channel between the gate and the source and between the gate and the drain, and the current path is not confined by the surface depletion layer. Also, since the relative permittivity of the air gap beside the gate embedding portion is 1, the gate capacitance can be made smaller than that of the structure having no air gap beside the gate embedding portion.

[Brief description of drawings]

FIG. 1 is an FE having a recess structure according to a first embodiment of the present invention.
It is sectional drawing which shows the structure of T typically.

FIG. 2 is an FE having a recess structure according to the first embodiment of the present invention.
FIG. 6 is a process cross-sectional view showing the method of manufacturing T in the order of processes.

FIG. 3 is an FE having a recess structure according to the first embodiment of the present invention.
FIG. 6 is a process cross-sectional view showing the method of manufacturing T in the order of processes.

FIG. 4 is an FE having a recess structure according to a second embodiment of the present invention.
FIG. 6 is a process cross-sectional view showing the method of manufacturing T in the order of processes.

FIG. 5 is an FE having a recess structure according to a second embodiment of the present invention.
FIG. 6 is a process cross-sectional view showing the method of manufacturing T in the order of processes.

FIG. 6 is a cross-sectional view schematically showing the structure of a conventional FET having a recess structure.

FIG. 7 is a cross-sectional view schematically showing the structure of a conventional FET having a recess structure.

[Explanation of symbols]

1 Semi-Insulating GaAs Substrate 2 Buffer Layer 3 Channel Layer 4 AlGaAs Stopper Layer 5 AlGaAs Stopper Layer 6 n ⁺ GaAs Cap Layer 7 Source Electrode 8 Drain Electrode 9 Gate Electrode 10 Gate Electrode 10 Side Gap 11 Photoresist 12 Gate Recess 13 First stage recess 14 Gate recess burying layer 15 AlGaAs stopper layer 16 Gate recess burying GaAs layer 17 Relaxation layer 18 Gate contact layer 19 Spacer layer 20 Low concentration region

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 21/3065 H01L 21/308 H01L 29/812

Claims (11)

(57) [Claims] 1. A semiconductor device having a recess structure in which at least a gate recess buried layer having a predetermined opening is formed on a GaAs substrate, and a gate electrode is formed in the opening of the gate recess buried layer. A cross section of the side wall of the opening of the buried layer has a concave shape protruding toward the center of the opening at the bottom and surface layers of the gate recess buried layer, and is exposed from the opening of the gate recess buried layer.
The gate electrode is arranged so as to cover the entire bottom surface of the recess portion and to form a gap between the gate recess embedded layer and a part of the side surface of the gate electrode. Semiconductor device. 2. At least a first Al layer on a GaAs substrate.
A GaAs stopper layer, a second AlGaAs stopper layer having an Al composition ratio smaller than that of the first AlGaAs stopper layer, and a gate recess buried layer are stacked in this order, and the gate recess buried layer and the second AlGaAs stopper layer are stacked. A semiconductor device having a recess structure in which a gate electrode is formed in a predetermined opening provided in the gate recess buried layer, wherein a cross section of the opening sidewall of the gate recess buried layer is the bottom portion and the surface layer portion of the gate recess buried layer. It has a concave shape protruding toward the center of the opening, and has the gate recess buried layer and the second AlGaAs strike layer.
Bottom surface of the gate recess exposed from the opening of the upper layer
A semiconductor device, wherein the gate electrode is provided so as to cover the entire surface and to form a gap between the gate recess burying layer and a part of a side surface of the gate electrode. 3. The Al of the first AlGaAs stopper layer
3. The semiconductor device according to claim 2, wherein the composition ratio is set to 0.7 and the Al composition ratio of the second AlGaAs stopper layer is set to 0.2 . 4. The semiconductor device according to claim 1, wherein a side surface of the opening of the gate recess burying layer has a V-shaped concave surface shape. 5. The opening of the gate recess burying layer comprises:
The semiconductor device according to claim 1, wherein the opening is formed by an etching solution containing citric acid. 6. The semiconductor device is a MESFET or HE.
The semiconductor device according to claim 1, wherein the semiconductor device is MT. 7. (a) At least a channel layer, a buried layer etching AlGaAs stopper layer, a gate recess buried layer, and a cap layer etching AlGa on a GaAs substrate.
A step of stacking an As stopper layer and an n ⁺ GaAs cap layer in this order, and (b) forming a predetermined opening in the n ⁺ GaAs cap layer using the AlGaAs stopper layer for etching the cap layer as an etching stopper, A step of forming an eye recess portion, and (c) a predetermined opening is formed in the gate recess embedded layer inside the opening portion of the n ⁺ GaAs cap layer using the embedded layer etching AlGaAs stopper layer as an etching stopper. And forming a second recess portion, (d) forming a gate electrode in the opening of the gate recess buried layer, and (e) an upper layer of the n ⁺ GaAs cap layer. And a step of forming source / drain electrodes on the substrate, the method comprising the steps of: (c) When forming an opening in the gate recess buried layer, using an etching liquid containing citric acid,
Etched at a predetermined condition sectional shape of the opening portion side becomes a concave surface, upon the gate electrode forming step (d), the gate
Gate recess exposed from the opening of the recess buried layer
The semiconductor device is characterized in that the gate electrode is arranged so as to cover the entire bottom surface of the portion and form a gap with the gate recess burying layer in a part of the side surface of the gate electrode. Manufacturing method. 8. (a) A first AlGaAs stopper layer for etching at least a channel layer and a buried layer on a GaAs substrate, and a second AlGaAs stopper layer having an Al composition ratio smaller than that of the first AlGaAs stopper layer. A step of laminating a gate recess burying layer, a cap layer etching AlGaAs stopper layer, and an n ⁺ GaAs cap layer in this order; and (b) the n ⁺ GaAs cap layer using the cap layer etching AlGaAs stopper layer as an etching stopper. A step of forming a predetermined opening in the first recess, and (c) forming the first AlGaAs stopper layer as an etching stopper inside the opening of the n ⁺ GaAs cap layer. A predetermined opening is formed in the gate recess buried layer and the second AlGaAs stopper layer. And a step of forming a recessed portion of the second stage, (d) the gate recess buried layer and said second AlGa
Method of manufacturing a semiconductor device having a recess structure, which comprises at least a step of forming a gate electrode in the opening of the As stopper layer, and (e) a step of forming source / drain electrodes in an upper layer of the n ⁺ GaAs cap layer. And the gate recess burying layer and the second layer in the step (c).
When forming an opening in the AlGaAs stopper layer of
Etching is performed using an etching solution containing citric acid under predetermined conditions such that the cross-sectional shape of the side surface of the opening of the gate recess embedding layer is concave, and then dry etching using SF ₆ + BCl ₃ gas is performed to selectively etching the gate recess buried layer only, upon the gate electrode forming step (d), the gate
Of the recessed buried layer and the second AlGaAs stopper layer.
Cover the entire bottom surface of the gate recess exposed from the opening.
As well as to Migihitsuji, a gap is formed between the gate recess buried layer in some aspects of the gate electrode, a method of manufacturing a semiconductor device, characterized in that. 9. The Al of the first AlGaAs stopper layer
9. The method of manufacturing a semiconductor device according to claim 8, wherein the composition ratio is set to 0.7 and the Al composition ratio of the second AlGaAs stopper layer is set to 0.2 . 10. The method of manufacturing a semiconductor device according to claim 7, wherein a side surface of the opening of the gate recess burying layer has a V-shaped concave surface shape. 11. The semiconductor device is a MESFET or H
The method of manufacturing a semiconductor device according to claim 7, wherein the method is an EMT.