JP2888993B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a field effect transistor (hereinafter sometimes referred to as an FET), and more particularly to a method of manufacturing an FET having a feature in a step of forming a source region and a drain region. Things.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor integrated circuits, FETs mounted thereon have become increasingly finer.

However, when the gate length of the FET is 1 μm or less, there arises a problem that device characteristics deteriorate due to a short channel effect.

As one means for preventing this, an FET having a structure in which the source region and the drain region have different impurity concentrations and depths is disclosed in, for example, the literature (IEICE Technical Report ED88-85, p. 47-5
It is disclosed in 2). An FET having such a structure (hereinafter, abbreviated as “asymmetric FET”) is
According to the technology disclosed in this document, it was manufactured by the method described below. 4 (A) to 4 (C) and FIG. 5 (A) to
(C) is a process drawing for explaining the same, and schematically shows the state of the element in a main process in the manufacturing process disclosed in the literature by a schematic cross section.

In this manufacturing method, first, an n-type impurity such as silicon (Si) is ion-implanted into a predetermined region of a semi-insulating GaAs (gallium arsenide) substrate 11 as a semiconductor substrate, and an active layer (channel layer) 13 is formed. Is formed.
Next, a gate electrode 15 is formed on a predetermined portion of the active layer 13 by a known technique (FIG. 4A). The material for forming the gate electrode 15 is tungsten aluminum (WA).
l) is used. This is because heat resistance is required in the self-aligned gate process. For example, W or WSi (tungsten silicide) can be used instead of W-Al.

Next, a germanium thin film 17 is formed on the entire surface of the substrate 11 on which the gate electrode has been formed by a film forming technique having anisotropy such as a normal vacuum deposition method.
(B)).

Next, a resist 19 is applied on the sample on which the germanium thin film has been formed, and thereafter, a portion of the resist 19 corresponding to one side of the gate electrode 15 of the germanium thin film 17 is formed by a known photolithography technique. An opening 19a exposing the portion is formed (FIG. 4C).

Next, the germanium thin film 17 is etched using the resist 19 as a mask. This etching is performed under the condition that the selectivity to W—Al is high and the germanium thin film 17 can be isotropically etched. Specifically, RIE (Reactive Ion Etc) using SF6 gas
hing). By this etching,
An opening 17a is formed in the germanium thin film 17 to expose the active layer on one side of the gate electrode 15 (FIG. 5A).

Next, the resist 19 is removed.
With the germanium thin film 17 used as a mask, an n-type impurity is ion-implanted into this sample. In this ion implantation, an impurity is implanted in a self-aligned manner only into the active layer on one side of the gate electrode. As a result, the source region 21
Is formed (FIG. 5B).

Next, the germanium thin film 17 is removed. Next, a resist 23 is formed on portions of the substrate 11 other than where the active layer 13 is formed. Thereafter, the resist 23 and the gate electrode 15 are used as a mask, and a second ion implantation is performed on the sample with, for example, an energy smaller than the first ion implantation energy. As a result, the impurity is also implanted into a portion of the active layer 13 other than the source region 21, and this region becomes the drain region 25.

In the above method, the impurity concentration and the depth of each of the source region and the drain region can be made different. Therefore, the impurity concentration can be increased in the source region and decreased in the drain region. For this reason, the mutual conductance gm of the FET can be increased by reducing the source resistance. In addition, since the electric field concentration in the drain region is reduced, the short channel effect of the FET can be suppressed.

[0012]

However, in the conventional manufacturing method, the gate electrode 15 is used as an ion implantation blocking mask for defining the gate electrode side end when forming the drain region (FIG. C), there is a problem that the drain region 25 is formed in a state where the end on the gate side is in contact with the gate electrode 15 (a state in which the drain region is arranged in a plane with the gate electrode). For this reason, the short channel effect cannot be sufficiently suppressed, and the disadvantage is that the Schottky reverse breakdown voltage is improved.

SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and it is therefore an object of the present invention to provide a method for fabricating a FET in which one or both of the impurity concentration and the depth of the source region and the drain region are different. It is an object of the present invention to provide a method in which only the gate electrode is formed apart from the gate electrode.

[0014]

According to the present invention, there is provided a field effect transistor in which one or both of an impurity concentration and a depth of a source region and a drain region are asymmetric. It is characterized in that the source region and the drain region are formed by steps including the following steps (a) to (e).

(A) A step of forming a thin film on the entire surface of a semiconductor substrate on which a gate electrode has been formed by an isotropic film forming technique.

(B) forming, in the thin film, an opening for exposing a portion of the active layer where a source region is to be formed, the opening being partially in contact with the gate electrode;

(C) a first impurity introducing step of introducing an impurity into the active layer portion using the thin film on which the opening has been formed as a mask;

(D) a step of forming the side wall film made of a part of the thin film on the side wall on the drain region side of the gate electrode by etching the thin film by anisotropic etching after forming the source region.

(E) a second impurity introducing step of introducing an impurity into the active layer after the formation of the side wall film.

Here, the term "isotropic film forming technique" means a technique in which, when a substrate or the like on which a film is formed has irregularities, a film can be formed with good step coverage on the irregularities. Specifically, a CVD method, a sputtering method, or the like can be given.

[0021]

According to the structure of the present invention, a thin film is formed on the entire surface of a semiconductor substrate on which a gate electrode has been formed by a film forming technique having isotropic properties. Since a film forming technique having an isotropic property is used, this thin film is well formed on the side surface of the gate electrode.
Therefore, when this thin film is later etched by the anisotropic etching means, a desired side wall film is formed on the side surface of the gate electrode on the side where the drain is to be formed (the thin film on the side surface on the source region is removed when the opening is formed). .

Further, a source region is formed in a predetermined portion of the active layer by performing the first impurity introduction step.
The source region is formed in a state in which the gate electrode side end is in contact with the gate electrode (a state in which the source region is planarly aligned with the gate electrode).

Further, a drain region is formed in a predetermined portion of the active layer by performing the second impurity introducing step. At this time, the gate electrode used as a part of the impurity introduction blocking mask has a configuration in which a sidewall film is provided on the side surface on the drain side, and thus, the drain region provided with the sidewall film has its gate electrode side end separated from the gate electrode. Formed in a state.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment, an example in which an asymmetric FET is formed on a semi-insulating GaAs substrate by the method of the present invention will be described below. FIGS. 2A to 2C, 3A to 3C, and FIG. 1 are diagrams for explanation thereof. Here, FIGS. 2 and 3 are process diagrams schematically showing the state of the element in the main steps of the process of the embodiment by a schematic cross-sectional view, and FIG. 1 shows the structure of the FET obtained after the process of the embodiment. FIG. 4 is a schematic cross-sectional view. In FIG. 1, 31 is a semi-insulating GaAs substrate as a semiconductor substrate, 33 is a channel layer, 35 is a gate electrode,
37 is a source region, 39 is a drain region, and 41 is a side wall film provided on the side surface on the drain region 39 side of the side surface of the gate electrode. In this FET, the source region 37 has a higher impurity concentration and a greater depth than the drain region 39. The source region 37 is formed in a state of being in contact with the gate electrode 35 (in a state of being arranged in a plane), and the drain region 39 has an end on the gate electrode side as a side wall film 41.
Are formed so as to be separated from the gate electrode 35 by the amount provided.

First, as shown in FIG. 2A, an n-type such as silicon is formed on a predetermined region of a GaAs substrate 31 (sometimes abbreviated as substrate 31) by a known method by a conventionally known method. Impurity is ion-implanted to form a channel layer 33, and a gate electrode 35 is formed on a predetermined portion of the channel layer 33. Here, in this embodiment, a heat-resistant metal such as tungsten aluminum (W—Al), W, or WSi (tungsten silicide) is used as a material for forming the gate electrode 35. This is because the gate electrode forming material needs to have heat resistance for the sake of using the self-aligned gate process.

Next, a thin film 41a is formed on the entire surface of the substrate 31 on which the gate electrode has been formed by using a film forming technique having good step coverage (FIG. 2A). This thin film 41a
Needs to be able to obtain a function as a mask layer for preventing impurities from being introduced into a region other than a predetermined region of the channel layer when forming the source region, and to be a material for forming the side wall film 41 (see FIG. 1). is there. In this embodiment, the thin film 41 is used.
a is composed of a SiO2 (silicon dioxide) film, and a CVD method is used as a film forming technique with good step coverage. However, the film forming method and the constituent material of the thin film are not limited thereto. As a film forming technique, a plasma CVD method, a sputtering method, or the like may be used, and a thin film forming material may be another insulating film as long as the above function can be obtained. For example, SixNY (silicon nitride) may be used. The reason for using the insulating film is that it is suitable for forming the side wall film, and if the side wall film is an insulating film, the gate electrode 35 and the drain region 39 can be left as it is (see FIG. 1). Is not short-circuited. However, when it is assumed that the sidewall film is removed after the formation of the source region and the drain region, the thin film 41 is used.
a need not be an insulating film, but may be, for example, a metal film as long as the above-mentioned purpose such as impurity introduction prevention can be achieved.

Next, a resist 43 is applied on the sample on which the thin film 41a has been formed, and thereafter, a part of the thin film 41a is exposed to a portion of the resist 43 corresponding to one side of the gate electrode 35 by a known photolithography technique. Opening 43a
Is formed (FIG. 2C).

Next, using the resist 43 as a mask, the thin film 41 is used.
Etch a. This etching is preferably performed under the condition that the selectivity to the material forming the gate electrode is high and the thin film 41a can be etched isotropically. For example, an RIE (Reactive Ion Etching) method under a predetermined condition is suitable. By this etching, an opening 41x that exposes the channel layer portion on one side of the gate electrode 35 and a part of the edge of which is in contact with the gate electrode 35 is formed in the thin film 41a (FIG. 3 ( A)).

Next, after removing the resist 43, an impurity, for example, an n-type impurity such as Si is introduced into the channel layer using the thin film 41a having the opening 41x formed thereon as a mask. By this step, impurities are implanted in a self-aligned manner in a portion of the channel layer 33 exposed from the opening 41x, and a source region 37 is formed in this portion (FIG. 3B).

Next, for example, an etching method (ECR) using plasma by RIE or electron cyclotron resonance.
The thin film 41a is etched by an anisotropic etching technique such as a method. At this time, the portion of the thin film 41a on the side surface of the gate electrode 35 remains, but there is no thin film on the side surface of the gate electrode 35 on the source region side.
The side wall film 41 composed of a part of the thin film 41a is formed only on the side surface of the drain region 5 on the drain region side. This also exposes a portion of the channel region 33 where a drain region is to be formed (FIG. 3C).

Next, a resist film 45 is formed on the portion of the substrate 31 other than where the source region 37 and the channel layer 33 are formed (FIG. 3C).
5. Using the gate electrode 35 and the side wall film 41 as a mask, a second impurity introduction is performed on this sample.

As a result, as shown in FIG. 1, impurities can be introduced in a portion other than the source region 37 of the channel layer 33 in a self-aligned manner, and this region becomes a drain region 39.

The drain region 39 is formed such that its gate electrode side end is separated from the gate electrode 35 by the side wall film 41. Further, since the source region 37 is doped with impurities even when the drain region is formed, the source region 37 has a larger impurity concentration depth than the drain region. As described above, according to the method of this embodiment, an asymmetrical FET in which only the drain region is separated from the gate electrode
Can be formed.

Thereafter, although not shown, an FET is obtained by forming an interlayer insulating film, forming an ohmic electrode, and the like by a conventionally known method.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and the following modifications can be made.

For example, in the above-described embodiment, the channel layer 33
Was formed by introducing impurities into the substrate 31, but this layer may be formed on the substrate by a crystal growth technique.

In the above embodiment, the GaAs-FET
However, it is clear that the present invention can also be used, for example, when manufacturing a Si-FET. In this case, the channel layer does not always need to be formed.

[0038]

As is clear from the above description, according to the method for manufacturing a field effect transistor of the present invention, the impurity concentration and depth of each of the source region and the drain region are made asymmetric, and the source region is made Needless to say, the gate electrode can be formed in a state where the end portion on the side of the gate electrode is in contact with the gate electrode (the source region is arranged in a plane with the gate electrode).
The drain region can be formed with its gate electrode side end separated from the gate electrode by a predetermined distance. Therefore, the short channel effect can be suppressed and the Schottky reverse breakdown voltage can be improved as compared with the conventional asymmetric FET. In addition, the distance between the drain region and the gate electrode can be easily controlled by changing the thickness of the side wall film, which is also advantageous in this respect.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing an FET obtained by a manufacturing method of the present invention.

FIGS. 2 (A) to 2 (C) are process diagrams for explaining an example.

FIGS. 3 (A) to 3 (C) are process diagrams following FIG. 2 for describing an example.

FIGS. 4A to 4C are process diagrams for explaining a conventional technique.

FIGS. 5 (A) to 5 (C) show FIGS.
FIG.

[Explanation of symbols]

 31: Semiconductor substrate (for example, semi-insulating GaAs substrate) 33: Channel layer 35: Gate electrode 37: Source region 39: Drain region 41: Side wall film 41a: Thin film (for example, SiO2 film) 41x: Thin film opening 43: Resist 43a : Resist opening 45: Resist film

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095-27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (1)

(57) [Claims] When manufacturing a field effect transistor in which one or both of an impurity concentration and a depth of each of a source region and a drain region are asymmetric, the source region and the drain region are subjected to the following steps (a) to (e). A method for manufacturing a field-effect transistor, comprising: (A) A step of forming a thin film on the entire surface of a semiconductor substrate on which a gate electrode has been formed by a film forming technique having isotropic properties. (B) forming, in the thin film, an opening that exposes a portion of the active layer where a source region is to be formed, and has a part of its edge in contact with the gate electrode; (C) a first impurity introduction step of introducing an impurity into the active layer portion using the thin film on which the opening has been formed as a mask. And (d) forming a side wall film made of a part of the thin film on the side wall on the drain region side of the gate electrode by etching the thin film by anisotropic etching after forming the source region. (E) a second impurity introduction step of introducing an impurity into the active layer after the formation of the sidewall film.