JP2005175007A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a trench with a deep groove where a state of a wall face is sufficient while width of the groove is suppressed to become larger. <P>SOLUTION: In a semiconductor device where the groove is formed on a main face of a semiconductor substrate, the groove is constituted of a surface layer part which continues from the main face of the semiconductor substrate, an intermediate part which continues from the surface layer part and a deep layer part which continues from the intermediate part. Side walls of the surface layer part, the intermediate part and the deep layer part are formed in forward taper shapes whose upper parts are wider than lower parts. A manufacturing method has a process for forming a first mask where a center part of a region in which a prescribed groove is formed is opened, a process for forming an intermediate groove on the main face of the semiconductor substrate by anisotropic etching using the first mask, a process for forming a second mask where the region in which the prescribed groove is formed is opened and a process for etching the main face of the semiconductor substrate and the first groove by anisotropic etching using the second mask and forming the prescribed groove. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique effective when applied to a semiconductor device having a trench structure.

  A pin diode in which a thin intrinsic semiconductor i-type semiconductor layer is sandwiched between pn junctions of a pn junction diode is used, for example, as an antenna switch for a mobile phone terminal. Due to the rapid advancement of power, high frequency, and multiband, pin diodes used as antenna switches have a smaller semiconductor device shape, lower operating current, lower loss of transmission / reception power, and signal leakage. There are demands for reducing the capacitance between terminals in order to reduce the impedance and preventing impedance fluctuation due to high frequency.

  In order to reduce the loss of the low-current operation and transmission / reception power, it is conceivable to reduce the resistance value of the i-type semiconductor layer by thinning the pin junction i-type semiconductor layer. However, since the resistance value of the i-type semiconductor layer and the junction capacitance of the i-type semiconductor layer are inversely proportional, a depletion layer spreads in the i-type semiconductor layer as the i-type semiconductor layer is thinned. The junction capacity increases.

  Further, the inter-terminal capacitance and impedance are greatly influenced by increase / decrease in the junction capacitance of the i-type semiconductor layer. That is, in order to reduce the inter-terminal capacitance and the impedance variation, it is required to reduce the junction capacitance of the i-type semiconductor layer.

  For this reason, in order to achieve both the reduction of the resistance value of the i-type semiconductor layer and the reduction of the junction capacitance of the i-type semiconductor layer, a groove-shaped isolation region called a trench is formed around the pin junction of the main surface of the semiconductor substrate. Then, the depletion layer is blocked by the trench, and the junction area between the i-type semiconductor layer and the p-type semiconductor layer and the junction area between the i-type semiconductor layer and the n-type semiconductor layer when the depletion layer spreads are reduced. Therefore, a technique for reducing the junction capacitance of the i-type semiconductor layer is used.

  In this trench, the pin junction exposed on the inner wall surface is covered with a protective film. However, when the shape of the inner wall surface of the trench is vertical or the width of the bottom portion of the trench is larger than the upper width, the taper is reverse tapered. In the case of the shape, since the coverage of the protective film covering the sidewall of the trench is lowered and a sufficient film thickness cannot be obtained, the semiconductor substrate is contaminated from the trench forming portion, and the breakdown voltage of the diode is deteriorated. May occur.

  For this reason, the following Patent Document 1 describes a technique for preventing the overhang by forming the trench groove of the pin diode into a forward tapered shape whose bottom is thinner than the top by isotropic etching. Yes.

JP 2002-124686 A

  Previously, it was possible to cope with a trench depth of the pin diode of about 18 μm. However, in recent years, it is necessary to form a deep groove of 20 μm or more in order to satisfy the characteristics required by the customer. In some cases, it is necessary to form a deep groove of about 33 μm. When such a deep groove of 20 μm or more is formed by isotropic etching, the width of the groove is widened by side etching, and the occupied area of the trench is increased. It becomes difficult.

  In order to prevent the width of the groove from expanding, when the groove is formed by using anisotropic dry etching, the wall surface of the trench is formed substantially vertically, so that a protective film or wiring formed on the wall surface is formed. Will cause problems in coverage. In addition, since the state of the trench wall surface deteriorates, a problem occurs in the adhesion of the protective film.

An object of the present invention is to solve these problems and provide a technique capable of forming a deep trench having a good wall surface state while suppressing an increase in the width of the groove. .
The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
In the semiconductor device in which the groove is formed on the main surface of the semiconductor substrate, the groove includes a surface layer portion continuous from the semiconductor substrate main surface, an intermediate portion continuous from the surface layer portion, and a deep layer portion continuous from the intermediate portion, Side walls of the surface layer portion, the intermediate portion, and the deep layer portion are each formed in a forward tapered shape whose upper portion is wider than the lower portion.

  Further, in the manufacturing method, a step of forming a first mask having an opening in a central portion of a region where the predetermined groove is formed, and an anisotropy using the first mask on a main surface of a semiconductor substrate Etching to form an intermediate groove, forming a second mask having a region where the predetermined groove is formed, using the second mask on the main surface of the semiconductor substrate, etc. Etching the semiconductor substrate main surface and the intermediate groove by isotropic etching, comprising a surface layer portion continuous from the semiconductor substrate main surface, an intermediate portion continuous from the surface layer portion, and a deep layer portion continuous from the intermediate portion, The side wall of the surface layer portion, the intermediate portion, and the deep layer portion includes a step of forming a predetermined groove having a forward tapered shape having a wider upper portion than the lower portion.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, there is an effect that the groove shape of the trench can be formed in a forward taper shape that expands from the lower part toward the upper part.
(2) According to the present invention, due to the effect (1), the sidewall of the trench is prevented from being overhanged, and a thin film such as a protective film or a metal film on the sidewall is formed with a sufficient thickness. There is an effect that it becomes possible.
(3) According to the present invention, the effect (2) has an effect that the film thickness of the protective film can be secured and contamination of the semiconductor substrate from the side wall can be prevented.
(4) According to the present invention, the effect (2) has an effect that the film thickness of the protective film can be secured and the breakdown voltage of the semiconductor device can be prevented from deteriorating.
(5) According to the present invention, the effect (2) has an effect that the film thickness of the metal film can be ensured to prevent the wiring formed on the side wall from being defective or disconnected.

Embodiments of the present invention will be described below.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a plan view showing a pin diode of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a partial longitudinal sectional view taken along line aa in FIG.

  This pin diode 1 is formed by forming a p-type semiconductor layer 4 on the main surface of a semiconductor substrate obtained by epitaxially forming an i-type semiconductor layer 3 on a semiconductor substrate 2 such as an n + -type single crystal silicon to be an n-type semiconductor layer, thereby forming an n + type. A pin junction is formed by laminating the semiconductor substrate 2, the i-type semiconductor layer 3, and the p-type semiconductor layer 4 in this order.

  The main surface of the semiconductor substrate is covered with a surface protective film 5, and an anode electrode 6 mainly composed of aluminum, for example, is connected to the connection region of the p-type semiconductor layer 4 opened through the surface protective film 5. For example, a cathode electrode 7 mainly composed of gold is formed on the n-type semiconductor layer 2.

  In order to block the depletion layer, this pin junction is surrounded by a trench 8 that is a groove-shaped isolation region. The trench 8 is covered with a surface protective film 5 to prevent contamination of the pin junction from the side wall.

  In trench 8 of the present embodiment, the cross-sectional shape of the groove is composed of surface layer portion 8a continuous from the main surface of the semiconductor substrate, intermediate portion 8b continuous from surface layer portion 8a, and deep layer portion 8c continuous from intermediate portion 8b. The sidewalls of the surface layer portion 8a, the intermediate portion 8b, and the deep layer portion 8c are each formed in a forward tapered shape whose upper portion is wider than the lower portion.

  Since the pin diode 1 of the present embodiment can block the depletion layer extending to the i-type semiconductor layer 3 by the trench 8, the junction area between the i-type semiconductor layer 3 and the n + -type semiconductor substrate 2, and the i-type semiconductor By reducing the junction area between the layer 3 and the p-type semiconductor layer 4, the junction capacitance of the i-type semiconductor layer 3 can be reduced.

  The anode electrode 6 connected to the p-type semiconductor layer 4 is desirably formed small in order to improve the electrical characteristics of the pin diode 1. For this reason, when the diameter of the anode electrode 6 is reduced to 50 μm or less, it is difficult to connect the bonding wire directly to the anode electrode 6 because a sufficient space is not secured.

  For this reason, in the pin diode 1 of the present embodiment, a bonding electrode 9 for wire bonding is formed separately from the anode electrode 6, and the bonding electrode 9 and the anode electrode 6 are electrically connected by the connection wiring 10. It is. The anode electrode 6, the bonding electrode 9, and the connection wiring 10 are composed of the same metal film, and the anode electrode 6 and the connection wiring 10 are covered with a final protective film 11 formed on the entire main surface of the semiconductor substrate. The final protective film 11 located on the bonding electrode 9 is partially opened to form a connection region for the bonding electrode 9.

  In the pin diode 1, as shown in a longitudinal sectional view of the mounted state in FIG. 3, the cathode electrode 7 side of the pin diode 1 is adhesively connected to one lead 12, and the anode electrode 6 and the other lead 13 are made of gold or the like. And the upper surfaces of the pin diode 1, the bonding wire 14, and the leads 12 and 13 are resin-sealed by a sealing body 15 such as a resin, and the leads 12 and 13 are formed on the bottom surface of the sealing body 15. The lower surface of is exposed. When mounted on a mounting board or the like, the lower surfaces of the leads 12 and 13 are connected to wiring of the mounting board. As a product outer shape, for example, it is a plane dimension of 1 mm × 0.6 mm, which is usually called 1006.

Next, a method for manufacturing this semiconductor device will be described for each step with reference to FIGS.
First, an intrinsic semiconductor epitaxial layer to be the i-type semiconductor layer 3 is grown on the n + -type semiconductor substrate 2, for example, PBF serving as a doping material is applied to the surface of the epitaxial layer, and heat is applied in an atmosphere of about 900 ° C. The p-type semiconductor layer 4 is formed by injecting B (boron) into the epitaxial layer and performing annealing by applying a heat treatment of about 1000 ° C. in a nitrogen atmosphere. The p-type semiconductor layer 4, the i-type semiconductor layer 3, and the n + type semiconductor substrate 2 form a pin junction. This state is shown in FIG.

  Next, a silicon oxide film 16 is deposited by high temperature low pressure CVD on the main surface of the semiconductor substrate on which the pin junction is formed, and a resist mask 17 patterned by photolithography is formed on the silicon oxide film 16. As shown in the partial plan view of FIG. 5, the resist mask 17 is formed with an annular opening having a width of about 10 μm at the center of a predetermined trench 8 formation region.

  Next, an intermediate groove 18 having a depth of about 9 μm is formed by anisotropic etching using the resist mask 17 and the silicon oxide film 16 as a mask. A longitudinal sectional view of this state is shown in FIG. This anisotropic etching will be described later in detail.

  Next, the resist mask 17 is removed, and as shown in a partial plan view in FIG. 7, a resist mask 19 having an opening of the trench 8 formation region having a width of about 46 μm is formed in the formation region of the trench 8. The silicon oxide film 16 in the trench 8 formation region is removed by anisotropic etching using the resist mask 19.

  Next, by using the resist mask 19 and the silicon oxide film 16 as a mask, a part of the p-type semiconductor layer 4, the i-type semiconductor layer 3, and the n + -type semiconductor substrate 2 is made into an intermediate groove by dry etching using an isotropic gas. Etching is performed from the bottom surface of 18 to a depth of about 18 μm larger than the intermediate groove 18. A partial longitudinal sectional view of this state is shown in FIG.

  In this isotropic etching, etching proceeds from the main surface of the semiconductor substrate exposed from the resist mask 19 and from the side surface and the bottom surface of the intermediate groove 18, so that the cross-sectional shape of the groove is the surface layer portion 8 a continuous from the main surface of the semiconductor substrate. And an intermediate portion 8b continuous from the surface layer portion 8a and a deep layer portion 8c continuous from the intermediate portion 8b. The side walls of the surface layer portion 8a, the intermediate portion 8b, and the deep layer portion 8c are wider at the upper portion than at the lower portion. Each is formed into a forward tapered shape.

  In the trench 8, the flow rate of the etching gas and the etching time during dry etching are adjusted so that the cross-sectional shape of the groove intersects the semiconductor substrate main surface and the surface layer portion 8 a at an angle of 90 ° or more, and the surface layer portion 8 a and the intermediate portion 8b intersects at an angle of 90 ° or more, the intermediate portion 8b and the deep layer portion 8c intersect at an angle of 90 ° or more, the angle formed by the bottom portion and the side wall of the deep layer portion 8c is 90 ° or more, and the lower portion is higher than the upper portion. A thin, forward tapered shape. That is, in the trench 8 of the present embodiment, all corners formed on the surface of the groove are obtuse.

  Next, after removing the resist mask 19 and the silicon oxide film 16, a PSG (Phospho Silicate Glass) film formed by CVD on a silicon oxide film formed by, for example, thermal oxidation, which becomes the surface protective film 5, is formed on the entire main surface of the semiconductor substrate including the inside of the trench 8. ) A laminated film in which films are laminated is formed, a resist mask 20 having an opening in the connection region of the anode electrode 6 is formed on the laminated film by photolithography, and laminated by dry etching using the resist mask 20. The surface protection film 5 is patterned by selectively removing the silicon oxide film and the PSG film to expose the p-type semiconductor layer 4 on the main surface of the semiconductor substrate that becomes the connection region. This state is shown in FIG.

  Next, after removing the resist mask 20, a metal film mainly composed of aluminum is deposited on the entire main surface of the semiconductor substrate by sputtering or the like, and the resist mask covering the formation region of the anode electrode 6, the bonding electrode 9, and the connection wiring 10. 21 is formed by photolithography, and the metal film is selectively removed and patterned by dry etching using the resist mask 21 to form the anode electrode 6, the bonding electrode 9, and the connection wiring 10. This state is shown in FIG.

  Next, after removing the resist mask 21, a final protective film 11 made of a laminated film in which a silicon nitride film and a silicon oxide film are sequentially deposited is formed on the main surface of the semiconductor substrate, and a resist having an opening in the connection region of the bonding electrode 9 is formed. A mask 22 is formed by photolithography, and the final protective film 11 is selectively removed by dry etching using the resist mask 22, and patterning is performed to expose the connection region of the bonding electrode 9 with a diameter of about 100 μm. This state is shown in FIG.

  Thereafter, the semiconductor substrate is washed, and a metal film, for example, Au (gold) / Sb (antimony) / Au is deposited on the semiconductor substrate 2 on the back surface opposite to the main surface of the semiconductor substrate by vapor deposition or the like. When the metal film is wet etched to form the cathode electrode 7, the state shown in FIG. 2 is obtained. The cathode electrode is made of a multilayer film made of Au / Sb / Au, but Ag (silver) may be used.

  In the conventional etching, as shown in FIG. 12, when a groove having a depth of 20 μm or more is formed by etching, an inverse taper in which the wall surface of the groove is narrower in the upper part than in the lower part in the vicinity of the main surface of the semiconductor substrate. It becomes a shape and is in a so-called overhang state protruding to the inside of the groove. In the reverse tapered portion, it is difficult to form the surface protective film 5 and the final protective film 11 with sufficient film thickness, so that the coverage of the surface protective film 5 and the final protective film 11 is insufficient, resulting in poor film formation. It was. A similar problem occurs with the connection wiring 10.

  In the present embodiment, the sidewalls of the trench 8 are formed by making the sidewalls of the surface layer portion 8a, the intermediate portion 8b, and the deep layer portion 8c of the trench 8 have a forward taper shape whose upper portion is wider than the lower portion by the method described above. In addition, the surface protective film 5 and the final protective film 11 formed in the subsequent steps can be stably deposited on the bottom surface.

  Accordingly, the surface protective film 5 and the final protective film 11 formed inside the trench 8 can be formed with sufficient film thickness, and therefore, the film thickness shortage of the surface protective film 5 and the final protective film 11 can be prevented. Therefore, contamination of the pin junction from the side wall of the trench 8 can be prevented, and at the same time, breakdown voltage degradation of the pin diode can be prevented.

  The connection wiring 10 is disposed on the surface protective film 5 so as to cross the inside of the trench 8. For this reason, the cross-sectional shape of the trench 8 is a forward tapered shape whose lower part is thinner than the upper part, so that the metal film to be the connection wiring 10 can be stably deposited on the side wall and the bottom surface of the trench 8. That is, the connection wiring 10 formed inside the trench 8 can be formed with a sufficient film thickness. For this reason, it is possible to prevent the connection wiring 10 from being defective or disconnected due to insufficient metal film thickness.

  In the anisotropic etching for forming the intermediate groove 18 described above, it is possible to form the intermediate groove 18 by ordinary anisotropic dry etching, but the etching rate is as slow as 0.5 μm / min to 1 μm / min. When a deep groove of 20 μm or more is formed, it takes a lot of time, which causes a delay in the progress of the entire process. For this reason, in this embodiment, anisotropic etching is performed by repeating dry etching using an isotropic gas having an etching rate as high as 3 μm / min.

Therefore, first, from the state shown in FIG. 5, a trench having a depth of about 1 μm is formed by dry etching using SF ₆ as an isotropic gas using the resist mask 17 and the silicon oxide film 16, as shown in FIG. Form. Subsequently, as shown in FIG. 14, the sidewall protective film 23 is deposited on the entire surface including the wall surface of the groove using the Freon gas F134a (CH ₂ F—CH ₃ ), and then SF ₆ is used as the isotropic gas. When dry etching is performed under the etching conditions under which the bottom surface etching proceeds, the semiconductor substrate at the bottom surface of the groove is exposed with the side wall protective film 23 remaining on the side wall of the groove as shown in FIG.

  Etching is further advanced from this state, and as shown in FIG. 16, the exposed semiconductor substrate is etched to a depth of about 1 μm. The formation of the sidewall protective film 23 and the etching using the isotropic gas are repeated to form the intermediate groove 18 having a predetermined depth, and the remaining sidewall protective film 23 is removed by wet etching, as shown in FIG. It becomes a state.

  In this way, the sidewall protective film 23 protects the sidewall of the groove to suppress the progress of the etching in the horizontal direction, and the etching in the vertical direction is advanced, so that the anisotropic etching is performed by dry etching using an isotropic gas. Etching can be performed, and the time required for forming the groove can be shortened.

  Although the present invention has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various changes can be made without departing from the scope of the invention. It is.

  For example, in the above-described embodiment, the case where one diode is formed on a single semiconductor chip is illustrated. However, when a plurality of diodes are formed on a single semiconductor chip, each element is electrically connected. The trench described above may be used for isolation.

  The above-described method for manufacturing a semiconductor device is not limited to the manufacture of a pin diode having a trench structure, and can also be used for manufacturing another semiconductor device having a trench structure.

It is a top view which shows the pin diode which is one embodiment of this invention. It is a fragmentary longitudinal cross-sectional view along the aa line in FIG. It is a longitudinal cross-sectional view which shows the mounting state of the semiconductor device which is one embodiment of this invention. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary top view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary top view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a longitudinal cross-sectional view which shows the trench by the conventional etching. It is a fragmentary longitudinal cross-section which shows the anisotropic etching used for the manufacturing method which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-section which shows the anisotropic etching used for the manufacturing method which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-section which shows the anisotropic etching used for the manufacturing method which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-section which shows the anisotropic etching used for the manufacturing method which is one embodiment of this invention for every process.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Pin diode, 2 ... Semiconductor substrate, 3 ... i-type semiconductor layer, 4 ... p-type semiconductor layer, 5 ... Surface protective film, 6 ... Anode electrode, 7 ... Cathode electrode, 8 ... Trench, 8a ... Surface layer part, 8b ... Intermediate part, 8c ... Deep layer part, 9 ... Bonding electrode, 10 ... Connection wiring, 11 ... Final protective film, 12, 13 ... Lead, 14 ... Bonding wire, 15 ... Sealed body, 16 ... Silicon oxide film, 17, 19, 20, 21, 22 ... resist mask, 18 ... intermediate groove, 23 ... sidewall protective film.

Claims (5)

In the semiconductor device in which the groove is formed in the semiconductor substrate main surface,
The groove is composed of a surface layer portion that is continuous from the main surface of the semiconductor substrate, an intermediate portion that is continuous from the surface layer portion, and a deep layer portion that is continuous from the intermediate portion, and the sidewalls of the surface layer portion, the intermediate portion, and the deep layer portion are A semiconductor device, wherein the upper part is formed in a forward tapered shape having a width wider than that of the lower part. In a manufacturing method of a semiconductor device in which a predetermined groove is formed in a semiconductor substrate main surface,
Forming a first mask having an opening at a central portion of a region where the predetermined groove is formed;
Forming an intermediate groove on the main surface of the semiconductor substrate by anisotropic etching using the first mask;
Forming a second mask having an opening in a region where the predetermined groove is formed;
The semiconductor substrate main surface and the intermediate groove are etched by isotropic etching using the second mask on the semiconductor substrate main surface, and a surface layer portion continuous from the semiconductor substrate main surface and an intermediate portion continuous from the surface layer portion And a side wall of the surface layer portion, the intermediate portion, and the deep layer portion each form a predetermined groove having a forward taper shape with a wider upper portion than the lower portion. And a method of manufacturing a semiconductor device.   In the anisotropic etching for forming the intermediate groove, the side wall of the groove is covered with a side wall protective film, dry etching using an isotropic reaction gas is performed, and this side wall protective film formation and etching using an isotropic gas are performed. The method of manufacturing a semiconductor device according to claim 2, wherein the intermediate groove is formed by repeating.   4. The method of manufacturing a semiconductor device according to claim 2, wherein the predetermined groove is a trench of a pin diode.   The method of manufacturing a semiconductor device according to claim 2, wherein a protective film or a metal film is formed inside the predetermined groove.

Images