JP2005340484A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a semiconductor chip without varying the characteristics of a pin diode. <P>SOLUTION: In a semiconductor device where a connection surface is separated by a recess obtained by partially removing the main surface of the semiconductor substrate, the recess is formed so as to oppose respective edges of the semiconductor substrate respectively in parallel, and so that distances between the respective edges of the semiconductor substrate may be equal, respectively. This manufacturing method forms a first mask obtained by opening the center part of an area where the prescribed recess is formed, forms an intermediate groove on the main surface of the semiconductor substrate by anisotropic etching using a first mask, forms a second mask obtained by opening an area in which the prescribed groove is formed, and etches the main surface of the semiconductor substrate and the intermediate groove on the main surface of the semiconductor substrate by isotropic etching using the second mask to form a surface layer connected from the main surface of the semiconductor substrate, an intermediate part connected from the surface layer, and a prescribed recess where the side wall of a deep layer connected from the intermediate part is tapered regularly. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique effective when applied to a semiconductor device having a trench structure.

  A pin diode sandwiching a thin intrinsic semiconductor i-type semiconductor layer (epitaxial layer) between pn junctions of a pn junction diode is used as an antenna switch of a mobile phone terminal, for example. In a digital mobile phone terminal, Due to the rapid progress of miniaturization, low power consumption, high frequency, and multi-band, pin diodes used as antenna switches have a smaller semiconductor device profile, lower operating current, and lower transmission / reception power loss. In order to reduce signal leakage, reduction of inter-terminal capacitance, prevention of impedance fluctuation due to high frequency, etc. are demanded.

  In order to reduce the loss of the low-current operation and transmission / reception power, it is conceivable to reduce the resistance value of the i-type semiconductor layer by thinning the pin junction i-type semiconductor layer. However, since the resistance value of the i-type semiconductor layer and the junction capacitance of the i-type semiconductor layer are inversely proportional, a depletion layer spreads in the i-type semiconductor layer in the horizontal direction as the i-type semiconductor layer is made thinner. The junction capacity of the semiconductor layer increases.

  Further, the inter-terminal capacitance and impedance are greatly influenced by increase / decrease in the junction capacitance of the i-type semiconductor layer. That is, in order to reduce the inter-terminal capacitance and the impedance variation, it is required to reduce the junction capacitance of the i-type semiconductor layer.

  For this reason, in order to achieve both the reduction of the resistance value of the i-type semiconductor layer and the reduction of the junction capacitance of the i-type semiconductor layer, a groove-shaped isolation region called a trench is formed around the pin junction of the main surface of the semiconductor substrate. The depletion layer is blocked by the trench, and the junction area between the i-type semiconductor layer and the p-type semiconductor layer and the junction area between the i-type semiconductor layer and the n-type semiconductor layer when the depletion layer spreads in the horizontal direction are obtained. A technique for reducing the junction capacitance of the i-type semiconductor layer by reducing the size is used.

  The pin diode having a trench structure is described in, for example, Patent Documents 1 and 2 below.

JP 2002-124686 A

Japanese Patent Application No. 2003-409196

  Electronic devices are being made smaller and thinner, and electronic components used there are also required to be smaller and thinner. For example, a pin diode having a 1 mm × 0.6 mm planar dimension, which is generally called 1006, is used, but a 0.8 mm × 0.5 mm planar dimension called 0805, or There is a need for further miniaturization to a plane size of 0.6 mm × 0.3 mm called 0603.

  At present, since the semiconductor chip to be mounted has a planar dimension of about 0.24 mm × 0.24 mm, it is difficult to make a 0603 size product outer shape. In order to cope with further miniaturization, the size of the semiconductor chip Need to be reduced. However, simply reducing the size of the semiconductor chip reduces the junction area and changes the characteristics of the pin diode.

  An object of the present invention is to provide a technique capable of downsizing a semiconductor chip.

Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor chip.
The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
In the semiconductor device in which the bonding surfaces are separated by the concave portion obtained by partially removing the main surface of the semiconductor substrate, the concave portion is formed at an equal distance from the outer edge of the semiconductor substrate over the entire circumference.

  More specifically, a main surface, a back surface opposite to the main surface, a recess formed in a ring shape in a part of the main surface, and formed on the main surface and formed inside the recess. A semiconductor substrate including a junction, the semiconductor substrate is formed in a quadrangular shape with a plane intersecting the thickness, and the recesses face each side of the semiconductor substrate in parallel, and the semiconductor substrate The plurality of sides are formed at equal distances from each side.

  Further, in the manufacturing method, a step of forming a first mask in which a central portion of the region where the predetermined recess is formed is formed, and an anisotropic method using the first mask on the main surface of the semiconductor substrate. A step of forming an intermediate groove by etching, a step of forming a second mask in which a region where the predetermined groove is formed is opened, and the second mask is used for a main surface of the semiconductor substrate. The main surface of the semiconductor substrate and the intermediate groove are etched by isotropic etching to form a surface layer portion continuous from the semiconductor substrate main surface, an intermediate portion continuous from the surface layer portion, and a deep layer portion continuous from the intermediate portion. Forming sidewalls of the surface layer portion, the intermediate portion, and the deep layer portion with a predetermined recess having a forward tapered shape having a wider upper portion than the lower portion.

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.
(1) According to the present invention, the recess for separating the joint portion of the semiconductor substrate main surface faces each side of the rectangular main surface of the semiconductor substrate in parallel with each other, and the distance from each side is By forming so as to have a plurality of sides that are equidistant, a useless portion is not generated at the corner of the outer peripheral portion, so that there is an effect that the chip size can be reduced.
(2) According to the present invention, there is an effect that the shape of the concave portion can be formed into a forward tapered shape that expands from the lower portion toward the upper portion.
(3) According to the present invention, the protective film formed at the corner of the taper can be prevented from being overhanged by the above effect (2), so the protective film formed at the corner of the taper, etc. There is an effect that it is possible to form a protective film on the side wall with a sufficient film thickness.
(4) According to the present invention, due to the effect (3), it is possible to secure the film thickness of the protective film, suppress contamination of the semiconductor substrate from the corners and side walls of the taper, and improve the reliability. effective.
(5) According to the present invention, due to the effect (3), there is an effect that the film thickness of the protective film can be secured, the breakdown voltage degradation of the semiconductor device can be suppressed, and the reliability can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  FIG. 1 is a plan view showing a pin diode which is a semiconductor device according to an embodiment of the present invention, FIG. 2 is a longitudinal sectional view taken along line aa in FIG. 1, and FIG. It is a fragmentary longitudinal cross-sectional view which expands and shows the inside a part.

  As shown in FIG. 1, the semiconductor substrate used for the pin diode 1 in the present embodiment has a rectangular planar shape that intersects the thickness direction. As shown in FIG. 2, this pin diode 1 is a semiconductor substrate in which an i-type semiconductor layer (epitaxial layer) 3 of an intrinsic semiconductor layer is formed by epitaxial growth on a semiconductor substrate 2 such as n + type single crystal silicon that becomes an n-type semiconductor layer. A p-type semiconductor layer 4 is formed on the main surface of the substrate, and a junction surface of a pin junction in which the n + type semiconductor substrate 2, the i-type semiconductor layer 3, and the p-type semiconductor layer 4 are sequentially stacked is formed along the main surface of the semiconductor substrate. doing.

  The main surface of the semiconductor substrate is covered with a protective insulating film 5, and an anode electrode 6 mainly composed of aluminum, for example, is connected to the connection region of the p-type semiconductor layer 4 opened through the protective insulating film 5. For example, a cathode electrode 7 mainly composed of gold (Au) is formed on the n-type semiconductor substrate 2 on the back surface of the semiconductor substrate opposite to the semiconductor substrate.

  In order to block the depletion layer of the pin junction, a trench 8 which is a groove-like recess from which the semiconductor substrate main surface is partially removed is formed in the semiconductor substrate main surface. The main surface of the semiconductor substrate is separated into a junction 9 (anode electrode 6) and an outer peripheral portion 10 (protective insulating film 5) by the trench 8. The trench 8 suppresses contamination of the pin junction from the side wall. Further, it is covered with a protective insulating film 5.

  Thereby, the pin diode 1 according to the present embodiment can block the depletion layer that spreads in the horizontal direction (direction intersecting the thickness direction of the semiconductor substrate) in the i-type semiconductor layer 3 at the junction. As described above, by reducing the junction area between the i-type semiconductor layer 3 and the n + -type semiconductor substrate 2 and the junction area between the i-type semiconductor layer 3 and the p-type semiconductor layer 4, the junction capacitance of the i-type semiconductor layer 3 can be reduced. Can be reduced.

  In trench 8 of the present embodiment, as shown in FIG. 3, the cross-sectional shape of the groove has a surface layer portion (first portion) 8a continuous from the main surface of the semiconductor substrate and an intermediate portion (continuous from surface layer portion 8a). (Second part) 8b and a deep layer part (third part) 8c continuous from the intermediate part 8b. The side walls of the surface layer part 8a, the intermediate part 8b and the deep layer part 8c are on the upper side (semiconductor substrate main surface side). Compared to the above, each is formed in a forward tapered shape which is wider. For this reason, the protective insulating film 5 can be stably deposited on the side wall and the bottom surface of the trench 8 so that the film thickness is uniform.

  In the semiconductor device of the present embodiment, as shown in FIG. 1, the trench 8 is formed in a rectangular ring shape (frame shape) according to the outer shape of the rectangular semiconductor chip. More specifically, each of the trenches 8 has a plurality of sides that face each side of the quadrangle-shaped main surface of the semiconductor substrate in parallel, and that the distances from the sides of the semiconductor substrate are equal. Have. In addition to the plurality of sides of the rectangular ring, that is, in the vicinity of the corners of the semiconductor substrate, the curved shape is chamfered in consideration of the coverage of the protective insulating film 5.

Since the semiconductor substrate used for the pin diode 1 is separated into pieces by, for example, dicing, the planar shape intersecting with the thickness direction is often rectangular. When the trench 8 is formed in this rectangular semiconductor substrate, the trench 8 is easily processed and the cross-sectional shape is uniformly formed. As shown in FIG. 4, a plan view and a vertical cross-sectional view in FIG. The trench 8 is formed in a circular ring shape. That is, the trench 8 is formed at an equal distance from the center of the semiconductor substrate over the entire circumference. Therefore, when the circular joint 9 of diameter D, the area becomes [pi] D ^2/4. However, when the junction 9 is formed in a circular shape, the area of the main surface of the semiconductor substrate is determined by the diameter of the circular junction 9. Further, as shown in FIG. 4, a useless region remains in the corner portion of the semiconductor substrate larger than the corner region of the semiconductor substrate in FIG. 1, and it is difficult to reduce the size of the semiconductor substrate. On the other hand, as shown in FIG. 1, when the rectangular joint portion 9 has a side length L, the area is L ² , and by making the joint portion 9 rectangular, a useless portion is not generated at the corner of the outer peripheral portion. Therefore, the chip size can be reduced.

  Therefore, if the junction 9 having a junction area equivalent to that of the conventional pin diode 1 having a circular junction 9 is formed on a rectangular semiconductor chip, D / L = √ (π / 4) and the diameter D On the other hand, the side length L can be reduced to 0.886D. That is, when the conventional pin diode 1 having a circular junction 9 has a size of 0.24 mm × 0.24 mm, the junction 9 having the same junction area is formed on a rectangular semiconductor chip. Can be reduced to a chip size of 0.21 mm × 0.21 mm.

  Further, in the pin diode 1 shown in FIGS. 1 and 2, the outer peripheral portion 10 of the main surface of the semiconductor substrate is left with the recess serving as a trench 8. By leaving the outer peripheral portion 10, the semiconductor chip can be easily handled during mounting. In addition, if the thickness of the cut portion is too thin when dicing to divide the wafer into pieces, the wafer is easily broken by dicing. However, when these problems can be solved, the size of the semiconductor chip can be further reduced by eliminating the outer peripheral portion 10 and forming the concave portion with a mesa structure as shown in FIGS. Become.

  In the pin diode 1, as shown in a longitudinal sectional view of the mounted state in FIG. 8, the cathode electrode 7 side of the pin diode 1 is adhesively connected to one lead 11, and the anode electrode 6 and the other lead 12 are made of gold or the like. Are connected by a bonding wire 13, the top surfaces of the pin diode 1, the bonding wire 13 and the leads 11 and 12 are resin-sealed by a sealing body 14 such as a resin, and the leads 11 and 12 are formed on the bottom surface of the sealing body 14. The lower surface of is exposed. When mounted on a mounting board or the like, the lower surfaces of the leads 11 and 12 are connected to the wiring of the mounting board. As described above, by reducing the size of the semiconductor chip to 0.21 mm × 0.21 mm, for example, it is possible to obtain a product outer shape having a planar size of 0.6 mm × 0.3 mm, which is generally called 0603. Become.

Subsequently, a method for manufacturing the semiconductor device will be described for each process with reference to FIGS.
First, an intrinsic semiconductor epitaxial layer to be the i-type semiconductor layer 3 is grown on the n + -type semiconductor substrate 2, and, for example, PBF (polyboron film) to be a doping material is applied to the surface of the epitaxial layer, and the temperature is about 900 ° C. The p-type semiconductor layer 4 is formed by thermally diffusing in an atmosphere, implanting B (boron) into the epitaxial layer, and performing a heat treatment at about 1000 ° C. in a nitrogen atmosphere. The p-type semiconductor layer 4, i-type semiconductor layer 3, and n + type semiconductor substrate 2 form a pin junction. A silicon oxide film 15 is deposited on the entire main surface of the semiconductor substrate on which the pin junction is formed by high-temperature low-pressure CVD, and a photoresist 16 ′ is formed on the entire surface of the silicon oxide film 15. A longitudinal sectional view of this state is shown in FIG.

  Next, the photoresist 16 ′ is exposed and developed to be patterned into a resist mask (first mask) 16 having an annular opening in the central portion of a predetermined trench 8 formation region, and dry etching using the resist mask 16 is performed. The p-type semiconductor layer 4 is exposed by removing the silicon oxide film 15 by etching. A longitudinal sectional view of this state is shown in FIG.

  Next, an intermediate groove 17 reaching the i-type semiconductor layer 3 is formed by anisotropic dry etching using the resist mask 16 and the silicon oxide film 15 as a mask. A longitudinal sectional view of this state is shown in FIG.

  Next, after performing ashing using ozone, the resist mask 16 is removed by a cleaning process, and a photoresist 18 'is formed on the entire surface. A longitudinal sectional view of this state is shown in FIG. Subsequently, the photoresist 18 ′ is exposed and developed and patterned into a resist mask (second mask) 18 in which an annular opening is provided in a predetermined trench 8 formation region, and oxidized by wet etching using the resist mask 18. The silicon film 15 is removed to expose the p-type semiconductor layer 4 and the intermediate groove 17. The opening area of the resist mask (second mask) 18 used for wet etching is larger than the opening area of the resist mask (first mask) 16 used for dry etching. A longitudinal sectional view of this state is shown in FIG.

  Next, by using the resist mask 18 and the silicon oxide film 15 as a mask, the p-type semiconductor layer 4, the i-type semiconductor layer 3, and a part of the n + -type semiconductor substrate 2 are partially etched by dry etching using an isotropic gas. Etching deeper than the intermediate groove 17 from the bottom surface of 17. A longitudinal sectional view of this state is shown in FIG.

  In this isotropic etching, the etching progresses from the main surface of the semiconductor substrate exposed from the resist mask 18 and from the side and bottom surfaces of the intermediate groove 17, so that the cross-sectional shape of the trench 8 continues from the main surface of the semiconductor substrate. 8a, an intermediate portion 8b continuous from the surface layer portion 8a, and a deep layer portion 8c continuous from the intermediate portion 8b. The side walls of the surface layer portion 8a, the intermediate portion 8b, and the deep layer portion 8c are wider at the upper portion than at the lower portion. Each is formed into a wide forward taper shape.

  In the trench 8, the flow rate of the etching gas and the etching time during dry etching are adjusted so that the cross-sectional shape of the groove intersects the semiconductor substrate main surface and the surface layer portion 8 a at an angle of 90 ° or more, and the surface layer portion 8 a and the intermediate portion 8b intersects at an angle of 90 ° or more, the intermediate portion 8b and the deep layer portion 8c intersect at an angle of 90 ° or more, the angle formed by the bottom portion and the side wall of the deep layer portion 8c is 90 ° or more, and the lower portion is higher than the upper portion. A thin, forward tapered shape. That is, in the trench 8 of the present embodiment, all corners formed on the surface of the groove are obtuse.

  Next, ashing using ozone is performed to remove the resist mask 18, and the silicon oxide film 15 is removed by wet etching, resulting in a state shown in FIG. Subsequently, a laminated film in which a PSG (Phospho Silicate Glass) film by CVD, a plasma silicon nitride film, etc. are laminated on a silicon oxide film by thermal oxidation, for example, which becomes the protective insulating film 5 over the entire main surface of the semiconductor substrate including the inside of the trench 8. A resist mask having an opening in the connection region of the anode electrode 6 is formed on the laminated film by photolithography, and the laminated film is selectively removed by dry etching using the resist mask to protect and insulate The film 5 is patterned to expose the p-type semiconductor layer 4 on the main surface of the semiconductor substrate that becomes the connection region. This state is shown in FIG.

  Next, after removing the resist mask for opening, a metal film using aluminum containing silicon is deposited on the entire main surface of the semiconductor substrate by sputtering or the like, and a resist mask covering the formation region of the anode electrode 6 is formed. The anode electrode 6 is formed by performing lithography and performing patterning by selectively removing the metal film by dry etching using the resist mask. This state is shown in FIG.

  Next, after removing the resist mask for electrode formation, the back surface opposite to the main surface of the semiconductor substrate is polished to reduce the thickness of the wafer, and by evaporation or the like on the semiconductor substrate 2 on the back surface, for example, Au A metal film laminated with (gold) / Sb (antimony) / Au is deposited, and the metal film is wet etched to form the cathode electrode 7. Note that Ag (silver) may be used for the cathode electrode. This state is shown in FIG.

  Thereafter, the wafer is cut and separated by dicing to divide each semiconductor chip into individual pieces. However, if dicing is performed at the position of the broken line a in FIG. 18, the trench structure shown in FIGS. When dicing is performed, the mesa structure shown in FIGS. 6 and 7 is obtained.

  In the etching for forming the concave portion, when anisotropic etching is performed, as shown in a perspective view in FIG. 19 (in order to show the internal shape of the concave portion, an example of a mesa structure is illustrated), Since the shape of the inner wall surface of the recess is vertical and a sharp corner is formed at right angles, the coverage of the protective film covering the side wall is lowered and a sufficient film thickness cannot be obtained, so the semiconductor substrate is contaminated from the side wall, There is a problem in that the breakdown voltage of the diode is reduced or the electrostatic breakdown strength is reduced, leading to a characteristic failure.

  Therefore, in the conventional etching, a resist mask 18 having an opening in the trench formation region is formed from the state shown in FIG. 9 as shown in FIG. 20, and isotropic dry etching is performed as shown in FIG. As shown in FIG. 22, the resist mask 18 and the silicon oxide film 15 are removed to form the trench 8. By performing this isotropic etching, the angle of the corners is moderated to suppress a decrease in the coverage of the protective insulating film 5.

  However, when the trench 8 is formed in a rectangular ring shape, in normal isotropic etching, there is a difference in the etching progress rate between the rectangular corner and the central portion of each side, and the etching progresses at the rectangular corner. As shown in FIG. 23, the corner becomes a so-called overhang shape in which the corner has a reverse taper shape in which the width of the bottom of the trench is larger than the width of the upper portion, resulting in poor coverage of the protective insulating film 5 and, in addition, overhang. If it becomes a shape, the strength of the overhanging p-type semiconductor layer 4 is reduced, and cracking is likely to occur in this portion.

  For this reason, in this embodiment, as shown in the perspective view in FIG. 24, the side walls of the surface layer portion 8a, the intermediate portion 8b, and the deep layer portion 8c of the trench 8 are wider than the lower portion by the above-described method. By using a wide forward taper shape, the protective insulating film 5 can be stably deposited on the side wall and bottom surface of the trench 8.

  Accordingly, since the protective insulating film 5 formed inside the trench 8 can be formed with a sufficient thickness, an insufficient film thickness of the protective insulating film 5 can be suppressed. It becomes possible to suppress the contamination of the junction, and at the same time, it is possible to suppress the deterioration of the breakdown voltage of the pin diode.

  Although the present invention has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various changes can be made without departing from the scope of the invention. It is.

It is a top view which shows the pin diode which is one embodiment of this invention. It is a longitudinal cross-sectional view along the aa line in FIG. It is a fragmentary longitudinal cross-sectional view which expands and shows the a part in FIG. It is a top view which shows the conventional pin diode. It is a longitudinal cross-sectional view along the aa line in FIG. It is a top view which shows the modification of the pin diode which is one embodiment of this invention. It is a longitudinal cross-sectional view along the aa line in FIG. It is a longitudinal cross-sectional view which shows the mounting state of the semiconductor device which is one embodiment of this invention. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode which is one embodiment of this invention for every process. It is a perspective view which shows the pin diode by anisotropic etching. It is a fragmentary longitudinal cross-sectional view which shows the pin diode by the conventional isotropic etching for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode by the conventional isotropic etching for every process. It is a fragmentary longitudinal cross-sectional view which shows the pin diode by the conventional isotropic etching for every process. It is a perspective view which shows the pin diode by the conventional isotropic etching. It is a perspective view which shows the pin diode which is one embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Pin diode, 2 ... Semiconductor substrate, 3 ... i-type semiconductor layer, 4 ... p-type semiconductor layer, 5 ... Protective insulating film, 6 ... Anode electrode, 7 ... Cathode electrode, 8 ... Trench, 8a ... Surface layer part, 8b ... Intermediate part, 8c ... Deep layer part, 9 ... Bonding part, 10 ... Outer peripheral part, 11, 12 ... Lead, 13 ... Bonding wire, 14 ... Sealed body, 15 ... Silicon oxide film, 16, 18 ... Resist mask, 17 ... Intermediate groove

Claims (8)

A semiconductor including a main surface, a back surface opposite to the main surface, a recess formed in a ring shape in a part of the main surface, and a joint formed on the main surface and formed inside the recess A main surface of the semiconductor substrate is formed in a square shape,
Further, the recess has a plurality of sides that face each side of the rectangular main surface of the semiconductor substrate in parallel and are formed at equal distances from the sides. A semiconductor device.   The concave portion includes a first part continuous from the main surface of the semiconductor substrate, a second part continuous from the first part, and a third part continuous from the second part, the first part, 2. The semiconductor device according to claim 1, wherein the sidewalls of the second part and the third part are each formed in a forward tapered shape having a wider width as approaching a main surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein a trench structure or a mesa structure is formed by the recess.   The semiconductor device according to claim 1, wherein the shape other than the plurality of sides in the recess is a curved shape. A step of preparing a semiconductor substrate including a main surface and a back surface facing the main surface, wherein a plane intersecting the thickness is formed in a quadrangular shape;
Forming a recess having a plurality of sides facing each side of the semiconductor substrate in parallel and having an equal distance from each side of the semiconductor substrate;
Forming a first mask having an opening in a region where the predetermined recess is formed;
Forming an intermediate groove on the main surface of the semiconductor substrate by anisotropic etching using the first mask;
Forming a second mask having an opening in a region where the predetermined groove is formed;
Etching the main surface of the semiconductor substrate and the intermediate groove by isotropic etching using the second mask on the main surface of the semiconductor substrate; and a first portion continuous from the main surface of the semiconductor substrate; It consists of a second part that continues from one part and a third part that continues from the second part, and the side walls of the first part, the second part, and the third part are respectively on the main surface of the semiconductor substrate. And a step of forming a predetermined recess having a forward taper shape that becomes wider as it approaches the semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 5, wherein a trench structure or a mesa structure is formed by the recess.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the opening area of the second mask is larger than that of the first mask.   6. The method of manufacturing a semiconductor according to claim 5, further comprising a step of removing the first mask by a cleaning process before the step of forming the second mask.

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