JP2009130084A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a resistance in a forward direction characteristic of a PIN diode in a semiconductor device having the PIN diode. <P>SOLUTION: The semiconductor device has a PIN diode 1A which contains: an N type cathode substrate NC of an N type; a P type anode layer PA of a P type; and an N type intrinsic semiconductor layer IL of an N type which is formed while coming into contact with each therebetween, and is an intrinsic semiconductor. The P type anode layer PA is formed ranging over a desired depth from a main face SIL of the N type intrinsic semiconductor layer IL, and an outer periphery of the P type anode layer PA is terminated at a position away inside from an outer periphery of an N type intrinsic conductive portion ID of the N type intrinsic semiconductor layer IL inside the main face SIL of the N type intrinsic semiconductor layer IL. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device technology, and more particularly to a technology effective when applied to a semiconductor device having a PIN junction.

  With the development of an advanced information society in recent years, it is required to improve the performance of mobile communication device terminals. For example, in digital cellular phones and the like, miniaturization, low power consumption, and multibanding are rapidly progressing.

  Here, in a general digital mobile phone, a transmission circuit for transmitting signals, a reception circuit for processing received signals, and an antenna for receiving and transmitting signals to these circuits from the outside are provided. Have. When transmitting, it is necessary to transmit a signal from the transmitting circuit to the antenna and not to the receiving circuit. On receiving, it transmits a signal from the antenna to the receiving circuit and to the transmitting circuit. Must not be communicated. That is, it is necessary to switch the transmission path of the high frequency signal in the signal processing circuit. A PN junction diode (hereinafter referred to as PN diode) is used as an element that satisfies this purpose.

  A two-terminal PN diode allows current to pass in either positive or negative polarity with respect to the bias of the voltage applied to the two terminals (forward direction, on state), and interrupts current for the other polarity. It has so-called rectification characteristics such as (reverse direction, off state). Using this rectification characteristic, when the antenna and the transmission circuit are made conductive at the time of transmission, the antenna and the reception circuit are shut off, and at the time of reception, the antenna and the reception circuit are made conductive. Shut off the transmission circuit.

  As described above, as a characteristic of the PN diode for antenna switching, it is desirable that the forward characteristic (when turned on) has a low resistance. This is because when a signal is passed through the PN diode in the forward direction, it is desirable to reduce the loss of the signal as much as possible, and a lower forward resistance is better. Furthermore, it is desirable that the reverse characteristic (when off) is a low capacity. This is because when the signal is cut off from the PN diode in the reverse direction, it is desirable to shorten the charge / discharge time of the PN diode as a capacitor as much as possible, and a lower reverse capacitance is better.

  As a PN diode that requires the above characteristics, a PIN junction diode (hereinafter referred to as a PIN diode) in which an intrinsic semiconductor region (hereinafter referred to as an intrinsic region) is sandwiched between a P region and an N region that form a PN junction. ) Has been put to practical use. In the intrinsic region, the concentration of exogenous impurities is low, and the depletion layer tends to spread when a reverse voltage is applied. Therefore, the electric capacity is reduced.

For example, an intrinsic region formed on a semiconductor substrate with a high impurity concentration and a PIN diode having a stacked structure of a semiconductor region with a high impurity concentration opposite to the substrate are disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-124686 (Patent Document). 1) or Japanese Patent Laid-Open No. 2005-340484 (Patent Document 2).
JP 2002-124686 A JP 2005-340484 A

  FIG. 12 shows the structure of a PIN diode that the present inventors have studied for introduction into, for example, a mobile phone device. The three-layer structure of the N-type cathode substrate NCx, which is a substrate and an N-type semiconductor region, the intrinsic semiconductor layer ILx, which is an intrinsic semiconductor, and the P-type anode layer PAx, which is a P-type semiconductor region, makes the main of the PIN diode 1x. The part is composed.

  In addition, a cathode electrode ECx and an anode electrode EAx are formed as electrodes on the N-type cathode substrate NCx and the P-type anode layer PAx, respectively. In addition, trenches Tx reaching from the surface to the N-type cathode substrate NCx are formed in the intrinsic semiconductor layer ILx and the P-type anode layer PAx. A protective film PVx is formed around the trench Tx and its periphery.

  Here, as described above, the PIN diode 1x has an intrinsic region between the PN junctions. As described above, when a reverse bias is applied to such a PIN diode 1x, the depletion layer extending in the intrinsic region is wide and the electric capacity is lower than that of a normal PN diode. On the other hand, there is a concern that the PIN diode 1x having an intrinsic region with an extremely low impurity concentration has a high resistance value during forward bias. In view of this, the PIN diode 1x having a reverse low-capacitance characteristic has a technical trend to lower the forward characteristic. In particular, due to the recent multifunctionalization of mobile communication devices, low power consumption is strongly desired, and the need for low resistance is increasing due to such demands.

  However, the present inventors have studied a technique for reducing the forward characteristic of the PIN diode 1x having the above structure, and have found the following problems. That is, in order to reduce the resistance of the forward characteristics, a structure in which more carriers can be injected from the N-type cathode substrate NCx and the P-type anode layer PAx into the intrinsic semiconductor layer ILx having a low extrinsic impurity concentration. The present inventors have conceived that this is effective.

  According to the study by the present inventors, it has been found that the resistance value can be lowered by increasing the junction area between the P-type anode layer PAx and the intrinsic semiconductor layer ILx. However, increasing the junction area between the P-type anode layer PAx and the intrinsic semiconductor layer ILx means that the area of the charge storage portion is increased in the reverse characteristics of the PIN diode 1x, that is, the capacitance is increased. cause. As described above, it has been clarified by the present inventors that the forward resistance value and the reverse capacitance value are in a trade-off relationship in the method of simply expanding the junction area.

  Accordingly, an object of the present invention is to provide a technique for reducing the forward characteristics of a PIN diode in a semiconductor device having the PIN diode.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  In the present application, a plurality of inventions are disclosed. An outline of one embodiment of the inventions will be briefly described as follows.

  That is, a first conductive type first semiconductor layer, a second conductive type second semiconductor layer, and a first conductive type third semiconductor layer that is provided in contact with each other and is an intrinsic semiconductor. The second semiconductor layer is formed to a desired depth from the main surface of the third semiconductor layer, and the outer periphery of the second semiconductor layer is formed in the main surface of the third semiconductor layer. The three semiconductor layers are terminated at positions away from the outer periphery of the diode forming portion.

  Of the plurality of inventions disclosed in the present application, effects obtained by the above-described embodiment will be briefly described as follows.

  That is, in a semiconductor device having a PIN diode, the forward characteristic of the PIN diode can be reduced.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The diode (semiconductor device) of the first embodiment is, for example, a PIN diode for a high frequency switch of a digital mobile phone. In such a PIN diode, a technique for reducing the resistance of the forward characteristics without increasing the capacitance in the reverse characteristics will be exemplified.

  FIG. 1 is a plan view of the PIN diode 1A according to the first embodiment. Here, in particular, only the planar boundary lines of different semiconductor regions are shown, and the insulating film region, the conductor film region, and the like are omitted. Further, FIG. 2 shows a cross-sectional view of the main part when the cross section taken along the line x1-x1 in FIG. 1 is viewed in the direction of the arrow.

  The PIN diode 1A according to the first embodiment includes an N-type cathode substrate (first semiconductor layer) NC as an N-type (first conductivity type) semiconductor substrate and a P-type (second conductivity type) P-type anode layer. (Second semiconductor layer) PA, and an N-type intrinsic semiconductor layer (third semiconductor layer) IL that is an N-type intrinsic semiconductor layer provided in contact with each other. Yes.

  The N-type is a state in which, for example, silicon composed of Group IV elements contains more Group V elements such as phosphorus (P) and arsenic (As) than Group III elements, and majority carriers are electrons. It represents the conductivity type of a certain semiconductor material. The P-type is a semiconductor material in which group III elements such as boron (B) are contained more than group V elements in group IV silicon and the like, and the majority carriers are holes. Represents the conductivity type.

  The N-type cathode substrate NC is formed of, for example, silicon (Si) single crystal, and has a front surface S1 and a back surface S2 located on opposite sides along the thickness direction. The planar shape of the N-type cathode substrate NC is formed, for example, on a quadrangle.

  On the surface S1 of the N-type cathode substrate NC, an N-type intrinsic semiconductor layer IL is formed. The N-type intrinsic semiconductor layer IL is formed of, for example, an N-type silicon single crystal similarly to the N-type cathode substrate NC, but its impurity concentration is an intrinsic semiconductor unlike the N-type cathode substrate NC. It is set to satisfy the conditions.

  Here, the intrinsic semiconductor is assumed to be a semiconductor defined as follows. In a semiconductor material made of a single crystal, electrons having stable energy in a bonded state are excited to energy that becomes conduction electrons (or free electrons) by thermal disturbance at a finite temperature. Since the electrons in the coupled state become free electrons, the same number of holes are generated at this time. Therefore, an intrinsic semiconductor means a semiconductor in which the concentration (impurity concentration) of implanted (or doped) extrinsic impurities is smaller than the concentration of electrons and holes generated thermally. Of course, this does not exclude semiconductors that do not contain impurities.

  The N-type intrinsic semiconductor layer IL extends from the main surface SIL of the N-type intrinsic semiconductor layer IL to the surface S1 of the N-type cathode substrate NC along the outer periphery of the N-type intrinsic conducting portion (diode forming portion) ID. A trench (groove) T is provided. Here, in the N-type intrinsic semiconductor layer IL, a portion surrounded by the trench T is an N-type intrinsic conduction portion ID. In other words, the N-type intrinsic conductive portion ID is isolated from the outer periphery of the N-type cathode substrate NC by the trench T in a plan view. The planar shape of the main surface SIL of the N-type intrinsic conductive portion ID is, for example, a rectangular shape.

  In the N-type intrinsic conductive portion ID, the planar frame-shaped N-type intrinsic semiconductor layer IL is left with the trench T interposed therebetween, but this portion does not function as the element itself.

  As will be described in detail later, in the PIN diode 1A of the first embodiment, the N-type intrinsic conduction portion ID is an element constituting a PIN junction of the diode element. Thus, by isolating the N-type intrinsic conductive portion ID, which is a component of the element, from the outer periphery of the N-type cathode substrate NC by the trench T, the following structure can be obtained.

  The N-type cathode substrate NC is used as a substrate constituting the PIN diode 1A. During the manufacturing process, a similar structure is collectively formed on a planar substantially circular thin plate called a semiconductor wafer. Treated. Then, after a desired configuration is formed by a process that will be described in detail later, it is individually cut (diced) by a cutting machine called a scriber. At this time, according to the study by the present inventors, if the N-type intrinsic semiconductor layer IL used as a component of the element reaches the outer periphery of the N-type cathode substrate NC, mechanical stress during dicing or direct It is said that a defect is caused by a serious contamination. Such a crystal defect becomes a trap level of the injected carriers and hinders carrier transport. As a result, the resistance value in the forward characteristic of the PIN diode is increased.

  Therefore, in the PIN diode 1A of the first embodiment, an N-type intrinsic conduction portion ID is provided, and this region is isolated by the trench T from the outer periphery of the N-type cathode substrate NC to be diced. Then, by forming a PIN junction of the diode element in this N-type intrinsic conduction portion, a structure in which crystal defects due to dicing hardly occur in the intrinsic region that affects the characteristics can be obtained. As a result, the resistance value in the forward characteristic of the PIN diode can be reduced.

  Further, as described above, the trench T formed for the purpose of isolating the N-type intrinsic conductive portion ID from the dicing region is formed by a chemical etching process such as wet etching, dry etching, or a combination thereof. Also good. Thereby, it becomes difficult to produce a crystal defect in the side wall of the N-type intrinsic conduction portion ID. As a result, the resistance value in the forward characteristic of the PIN diode can be further reduced.

  The surface of the N-type intrinsic conductive portion ID of the N-type intrinsic semiconductor layer IL is covered with a protective film PV. Here, the protective film PV is formed so as to completely cover the stepped portion and the inner wall of the trench T so that the N-type intrinsic conductive portion ID is not exposed.

  In the first embodiment, the protective film PV is, for example, a laminated structure of the following three types of films. The first layer is an oxide film mainly composed of a silicon oxide film that can be stably formed on single crystal silicon which is a material constituting the N-type intrinsic semiconductor layer IL. The second layer is a silicate glass film mainly composed of PSG (Phospho-Silicate Glass) having a function of trapping (gettering) external charges such as various ions. The third layer is a nitride film mainly composed of a silicon nitride film having a function of preventing intrusion of moisture and the like. The third silicon nitride film is formed by, for example, a low-pressure chemical vapor deposition (CVD) method in order to improve the coverage (step coverage) of the stepped portion. .

  By covering the main surface SIL of the N-type intrinsic semiconductor layer IL with the protective film PV as described above, the N-type intrinsic conductive portion ID, which is a component of the PIN junction, can enter ions from the outside or moisture can enter. Can prevent from. This makes it difficult for carriers injected into the intrinsic region in the PIN junction to be prevented from being transported by exogenous charges or contamination. As a result, the resistance value in the forward characteristic of the PIN diode can be further reduced.

  Further, according to the technology studied by the present inventors, a diffusion layer having the same conductivity type as that of the substrate (cathode part) is formed on the surface of the intrinsic region for the purpose of preventing the entry of external charges and contamination similar to those described above. There is a method of forming and stabilizing the surface of the intrinsic region. Here, the added diffusion layer is a semiconductor region having an impurity concentration higher than that of the intrinsic semiconductor state. However, when the present inventors verified a PIN diode to which this technology is applied, it was experimentally confirmed that the harmonic distortion characteristics deteriorate.

  Here, the harmonic distortion characteristic is noise (noise) generated when a desired RF signal is passed through a PIN diode that is a nonlinear characteristic, and a frequency signal that is an integral multiple of the RF signal is generated. For example, in the GSM (Global System for Mobile Communications) standard for portable communication terminals, the frequency band of 900 MHz / 1800 MHz may be used. Here, when a double wavelength distortion of 900 MHz occurs (that is, a noise signal of 1800 MHz is generated), it causes interference in another band (1800 MHz). Therefore, this is an important characteristic in a PIN diode for antenna switching use. is there.

  The deterioration of the harmonic distortion characteristic observed in the PIN diode having the diffusion layer on the intrinsic region surface investigated by the present inventors is a phenomenon derived from the signal transmission path according to the present inventors' investigation. I understood that. That is, an RF (Radio Frequency) signal (or a harmonic signal, a high frequency signal) originally flows from the anode part to the cathode part through the intrinsic region, but a diffusion layer having a relatively high impurity concentration exists in the intrinsic region. This is because it flows through this diffusion layer. In the PIN diode 1A of the first embodiment, the protective film PV prevents entry of exogenous charges and contamination without intentionally providing the diffusion region in the N-type intrinsic semiconductor layer IL. As a result, the resistance value in the forward characteristic of the PIN diode can be further reduced without deteriorating the harmonic distortion characteristic.

  Further, the cathode electrode EC is formed on the back surface S2 of the N-type cathode substrate NC, and the anode electrode EA is formed so as to cover the exposed portion of the P-type anode layer PA. The cathode electrode EC and the anode electrode EA are formed of a conductor film such as Al, Ti, TiW, W, or TiN. The above is the main configuration of the PIN diode 1A of the first embodiment.

  Hereinafter, in particular, the shape of the P-type anode layer PA among the PIN diodes of the first embodiment will be described in detail. A P-type anode layer PA is formed in the N-type intrinsic conductive portion ID of the N-type intrinsic semiconductor layer IL as described above. The P-type anode layer PA extends from the main surface SIL of the N-type intrinsic conduction part ID to a desired depth so as not to reach the surface S1 of the N-type cathode substrate NC and leave the N-type intrinsic conduction part ID in the lower part. Is formed.

  Here, in the PIN diode 1A of the first embodiment, the shape of the P-type anode layer PA is different from the PIN diode 1x described with reference to FIG. In the PIN diode 1x examined by the present inventors in FIG. 12, the P-type anode layer PA is formed from end to end so as to cover the entire surface of the N-type intrinsic semiconductor layer IL. On the other hand, in the PIN diode 1A of the first embodiment, the P-type anode layer PA is formed so as to cover a part of the main surface SIL of the N-type intrinsic semiconductor layer IL. Here, when the surface S1 of the N-type cathode substrate NC is viewed in plan, the P-type anode layer PA has an N-type intrinsic semiconductor layer so that its end does not reach the end of the N-type intrinsic semiconductor layer IL. It is formed inside the IL.

  In particular, in the PIN diode 1A of the first embodiment, as described above, the N-type intrinsic semiconductor layer IL is planarly separated from the outer periphery of the N-type cathode substrate NC by the trench T. I have an ID. The P-type anode layer PA is formed in the N-type intrinsic conductive portion ID. Further, here, as viewed in a plan view, the end portion of the P-type anode layer PA is formed inside the N-type intrinsic conduction portion ID so as not to reach the trench T which is the end portion of the N-type intrinsic conduction portion ID. Has been.

  In the PIN diode 1A of the first embodiment, with the above structure, the difference in characteristics appearing with respect to the PIN diode 1x of FIG. 12 examined by the present inventors will be described with reference to FIGS. This will be described in detail.

  FIG. 3A is an explanatory view of a cross section showing a state of injection of holes h from the P-type anode layer PAx into the intrinsic semiconductor layer ILx in the PIN diode 1x having a structure studied by the present inventors. Here, the P-type anode layer PAx is formed so as to cover the entire surface of the intrinsic semiconductor layer ILx. Therefore, the main junction surface Jx where holes h are injected from the P-type anode layer PAx into the intrinsic semiconductor layer ILx is limited to one surface along the surface S1x of the N-type cathode substrate NCx.

  Therefore, in the PIN diode 1x having the above-described structure studied by the present inventors, the main junction surface Jx must be expanded in the direction along the surface S1x of the N-type cathode substrate NCx in order to reduce the resistance of the forward characteristics. I must. However, enlarging the main joint surface Jx as described above simultaneously causes an increase in capacity in reverse characteristics. This causes a deterioration in the performance of the PIN diode for antenna switching use. In addition, the device area is also increased, and the PIN diode for use in mobile communication terminals, which is in the trend of miniaturization and weight reduction, has an element shape opposite to the trend.

  On the other hand, FIG. 3B shows a cross-sectional view showing a state of injection of holes h from the P-type anode layer PA into the N-type intrinsic semiconductor layer IL in the PIN diode 1A of the first embodiment. The figure is shown. As described with reference to FIGS. 1 and 2, the planar end of the P-type anode layer PA does not reach the sidewall of the trench T, which is the planar end of the N-type intrinsic semiconductor layer IL. It has become. Therefore, the main junction plane J into which holes h are injected from the P-type anode layer PA into the N-type intrinsic semiconductor layer IL extends along the side wall of the trench T in addition to the bottom surface Jb along the surface S1 of the N-type cathode substrate NC. It also has a side surface Js.

  Thus, even if the planar area of the main junction surface J of the PIN diode 1A of the first embodiment is approximately the same as that of the main junction surface Jx of the PIN diode 1x studied by the present inventors, As a result of having Js, the injection efficiency of holes h into the N-type intrinsic semiconductor layer IL increases. According to the verification by the present inventors, it has been found that the injection of holes h from the P-type anode layer PA occurs more efficiently on the side surface Js than on the bottom surface Jb in the main junction surface J. Therefore, in the PIN diode 1A of the first embodiment, the resistance can be reduced with a smaller area enlargement ratio than when the area of the main junction surface Jx is increased with the PIN diode 1x studied by the present inventors. Can do. That is, a lower resistance value can be realized even with the same reverse capacitance.

  In order to more specifically explain the above difference in electrical characteristics, FIG. 4 shows forward characteristics of the PIN diode 1x examined by the present inventors and the PIN diode 1A of the first embodiment. ing. Here, a change in resistance value rf (unit: [Ω]) with respect to the forward current value IF (unit: [mA]) is shown. Here, the forward characteristics are shown in both structures in which the capacitance values in the reverse characteristics are approximately the same.

  The characteristic ex of the PIN diode 1A according to the first embodiment is the order in which the resistance value rf is lower at the same forward current value IF than the characteristic ref of the PIN diode 1x studied by the present inventors. Directional characteristics. This is because, in the PIN diode 1A of the first embodiment, the main junction J surface with the P-type anode layer PA that injects holes h into the N-type intrinsic semiconductor layer IL has a side surface Js in addition to the bottom surface Jb. This is because the injection efficiency of holes h is improved. Thus, in the PIN diode 1A of the first embodiment, the forward characteristic can be reduced in resistance without increasing the capacitance value in the reverse characteristic.

  Next, a method of manufacturing the PIN diode 1A having the structure of the first embodiment described with reference to FIGS. 1 and 2 will be described with reference to FIGS. 6 to 9, following the flowchart shown in FIG. FIG. 5 is a flowchart showing the order of the manufacturing process of the PIN diode 1A. Moreover, FIGS. 6-9 shows principal part sectional drawing in a manufacturing process. Further, during the manufacturing process, for example, a silicon single crystal is handled as a thin plate having a substantially circular shape as a semiconductor material. Then, similar elements are formed in a large number of regions by simultaneously or successively performing a similar process on a large number of regions defined by cutting lines called scribe lines. In the following, the manufacturing process will be described using one of the many regions shown as a representative.

  First, as shown in FIG. 6, an N-type intrinsic semiconductor layer IL that is an I layer is formed on a surface S1 of an N-type cathode substrate NC that is an N-type semiconductor substrate and serves as a cathode N layer of a PIN junction. Here, a layer mainly composed of silicon is epitaxially grown by, eg, CVD (step 101 in FIG. 5). Epitaxial growth means that a material to be formed (here, silicon) is deposited in the form of atoms and molecules on a single crystal substrate (here, an N-type cathode substrate NC made of single crystal silicon). This is a technique for growing a deposited layer in a single crystal following the orientation.

  At this time, an impurity material can be mixed at the same time during the growth to obtain an N-type or a P-type. For example, when group IV silicon is grown as a single crystal, it can be made N-type by mixing group V phosphorus (P), arsenic (As), or the like, and group III boron (B) or the like is mixed. Therefore, it can be made P-type. In the first embodiment, the N-type intrinsic semiconductor layer IL formed by epitaxial growth has the same N-type conductivity as that of the N-type cathode substrate NC, and its impurity concentration is lower than that of the N-type cathode substrate NC. . In the first embodiment, in particular, the impurity concentration of the N-type intrinsic semiconductor layer is assumed to be an intrinsic semiconductor.

  Here, normally, an N-type intrinsic semiconductor layer IL is formed by introducing an impurity material that becomes an intrinsic semiconductor during the epitaxial growth. On the other hand, there may be a case where a layer having a P-type or N-type impurity concentration that has conductivity higher than that of the intrinsic semiconductor must be formed at the time of the epitaxial growth because of the manufacturing process. In such a case, the impurity concentration of the intrinsic semiconductor may be obtained by performing, for example, an ion implantation method after the epitaxial growth on the region to be the N-type intrinsic semiconductor layer IL.

  For example, when a layer having an impurity concentration that exhibits P-type conductivity is epitaxially grown, the following is performed. In other words, N-type ions having the same amount as the P-type impurities of the epitaxial growth layer are implanted into the epitaxial growth layer by an ion implantation method or the like, so that the conductive carriers are offset, and the N-type intrinsic semiconductor layer IL is formed. Can be formed. Further, when a layer having an impurity concentration that exhibits N-type conductivity is epitaxially grown, the following is performed. That is, P-type ions having the same amount as the N-type impurities of the epitaxial growth layer are implanted into the epitaxial growth layer by an ion implantation method or the like, so that the conductive carriers are offset, and the N-type intrinsic semiconductor layer IL is formed. Can be formed.

  Subsequently, the surface oxide film 2 made of a silicon oxide film or the like is formed by oxidizing the surface of the N-type intrinsic semiconductor layer IL by, eg, thermal oxidation (step 102 in FIG. 5).

  Next, as shown in FIG. 7, the opening 3 is formed by patterning the surface oxide film 2. Here, first, a series of photolithography processes are performed in which a photoresist film is deposited on the surface of the surface oxide film 2, and the photoresist mask is exposed and developed through an exposure mask having a desired pattern (not shown). ). Then, using the photoresist film in which the desired pattern is developed as an etching mask, the exposed region of the surface oxide film 2 is removed by, for example, anisotropic etching. Thereafter, the opening 3 can be formed by removing the photoresist film (step 103 in FIG. 5).

  Thereafter, ion implantation is performed on the N-type intrinsic semiconductor layer IL using the surface oxide film 2 having the opening 3 as an ion implantation mask (step 104 in FIG. 5). Here, the group 4 or group VI ions 4 are implanted so that the group IV silicon is P-type. Subsequently, by performing heat treatment (annealing), the implanted ions 4 are activated and diffused to form a P-type anode layer PA. Thereafter, the surface oxide film 2 used as the ion implantation mask is removed by an etching method or the like.

  Next, as shown in FIG. 8, a surface oxide film 5 is formed so as to cover the surfaces of the N-type intrinsic semiconductor layer IL and the P-type anode layer PA formed therein, and the openings 6 are formed by patterning. Is formed (step 105 in FIG. 5). Here, as the surface oxide film 5, for example, a silicon oxide film or the like is formed. The opening 6 is formed by, for example, a series of photolithography methods and etching methods. Thereafter, by performing anisotropic etching using the surface oxide film 5 having the opening 6 as an etching mask, the exposed region of the N-type intrinsic semiconductor layer IL is removed, thereby forming a trench T (step 106 in FIG. 5). ). Thereafter, the surface oxide film 5 used for the etching mask is removed.

  At this time, the trench T is formed such that a part of the N-type intrinsic semiconductor layer IL forms an N-type intrinsic conductive portion ID isolated from the end of the N-type cathode substrate NC. The N-type intrinsic conductive portion ID forms a trench T so as to enclose the P-type anode layer PA. Furthermore, the trench T is formed such that the end portion of the P-type anode layer PA does not reach the side wall of the trench T that is the end portion of the N-type intrinsic conduction portion ID. By performing such processing, the main joint surface J between the P-type anode layer PA and the N-type intrinsic semiconductor layer IL has not only the bottom surface Jb but also the side surface Js. As a result, as described with reference to FIG. 3B, a structure in which carriers can be more efficiently injected into the N-type intrinsic semiconductor layer IL, and as a result, the forward characteristics of the PIN diode can be reduced in resistance. Can do.

  Further, according to the above-described steps, the sidewall of the trench T as the end portion of the N-type intrinsic conduction portion ID that is an intrinsic region of the PIN junction is formed by a chemical etching technique. For example, wet etching, dry etching, or a combination thereof. Therefore, unlike a method such as mechanical cutting, for example, a crystal defect due to stress or the like hardly occurs in the N-type intrinsic conductive portion ID. As described above, a structure with few crystal defects serving as carrier trap states can be obtained, and as a result, the forward characteristics of the PIN diode can be further reduced in resistance.

  Next, as shown in FIG. 9, a protective film PV is formed so as to cover the exposed region of the N-type intrinsic semiconductor layer IL (step 107 in FIG. 5). In the first embodiment, the protective film PV has a structure in which three kinds of films of a silicon oxide film, a silicate glass film, and a silicon nitride film are laminated in order from the lower layer as described above with reference to FIG. is there. In addition, the uppermost silicon nitride film can be formed by, for example, a CVD method with a low gas pressure, for example, so that the coverage of a step such as the trench T can be improved.

  Thereafter, an anode electrode EA is formed on the P-type anode layer PA as one terminal of the PIN junction (step 108 in FIG. 5). The anode electrode EA is formed by depositing a metal film by, for example, a sputtering method and patterning it into a desired shape by a series of photolithography methods and etching methods. Then, annealing is performed in a hydrogen atmosphere to terminate the dangling bonds on the surface with hydrogen and stabilize the surface (step 109 in FIG. 5).

  Subsequently, the back surface S2 of the N-type cathode substrate NC is polished with a grindstone containing diamond particles, and the thickness of the N-type cathode substrate NC is ground to a desired thickness (Step 110 in FIG. 5). Thereafter, the processing strain layer and the like formed during grinding are removed by a wet etching method or the like, and then a cathode electrode EC made of a metal film is formed by a sputtering method or a vacuum deposition method (step 111 in FIG. 5). Through the above steps, the structure of the PIN diode 1A of the first embodiment is formed.

  Thereafter, dicing is performed to cut out the PIN diodes 1A having the above structure arranged on the semiconductor wafer into individual semiconductor devices (step 112 in FIG. 5). Then, as individual PIN diodes, packaging is performed by sealing with resin or the like (step 113 in FIG. 5).

  Through the above steps, a semiconductor device having the PIN diode 1A of the first embodiment can be manufactured. According to the PIN diode 1A of the first embodiment, the forward characteristic can be reduced in resistance without increasing the capacitance in the reverse characteristic.

(Embodiment 2)
In the first embodiment, the PIN diode 1A having a structure in which the main junction surface J between the P-type anode layer PA and the N-type intrinsic semiconductor layer IL has the bottom surface Jb and the side surface Js is exemplified. This is a structure in which the N-type intrinsic conductive portion ID where the main junction surface J is formed is isolated from the end of the N-type cathode substrate NC by the trench T. The second embodiment exemplifies a structure in which the N-type intrinsic semiconductor layer IL is isolated from the end portion of the N-type cathode substrate NC by a configuration different from the above.

  FIG. 10 is a plan view of the PIN diode 1B according to the second embodiment. Here, in particular, only the planar boundary lines of different semiconductor regions are shown, and the insulating film region, the conductor film region, and the like are omitted. FIG. 11 is a cross-sectional view of the main part when the cross section taken along line x2-x2 in FIG. 10 is viewed in the direction of the arrow.

  The PIN diode 1B according to the second embodiment is a semiconductor element using a three-layer stacked structure of an N-type cathode substrate NC, an N-type intrinsic semiconductor layer IL, and a P-type anode layer PA as a PIN junction. In particular, like the PIN diode 1A of the first embodiment, the P-type anode layer PA is formed from the main surface SIL of the N-type intrinsic semiconductor layer IL over a region having a desired depth, and the planar The end does not reach the planar end of the N-type intrinsic semiconductor layer IL.

  A protective film PV is formed on the main surface SIL and the side surface WIL of the N-type intrinsic semiconductor layer IL so as to prevent the exposure. The configuration of the protective film PV is the same as that of the PIN diode 1A of the first embodiment. Also, an anode electrode EA made of a metal film or the like is formed so as to cover the surface of the P-type anode layer PA, and a cathode electrode EC made of a metal film or the like is formed on the back surface S2 of the N-type cathode substrate NC. Yes.

  Since the configuration of the PIN diode 1B of the second embodiment described above is the same as the structure of the PIN diode 1A described in the first embodiment, the detailed description thereof is omitted.

  The PIN diode 1B of the second embodiment is different from the PIN diode 1A of the first embodiment in that the N-type intrinsic semiconductor layer IL has a mesa shape (that is, a convex shape) on the surface S1 of the N-type cathode substrate NC. The planar end portion is isolated from the end portion of the N-type cathode substrate NC. Thereby, it is possible to avoid crystal defects in the N-type intrinsic semiconductor layer IL that are likely to occur when the semiconductor wafer is individually cut. For this reason, in the N-type intrinsic semiconductor layer IL, which is the main part of the PIN junction, it is possible to mitigate the generation of crystal defects that become carrier trap levels. As a result, the forward characteristics of the PIN diode can be reduced.

  Furthermore, by using a mesa shape, the planar space can be reduced as compared with the structure shown in FIGS. 1 and 2 that achieves the same purpose using the trench T. This is because, in the PIN diode 1A of the first embodiment, the frame-shaped N-type intrinsic semiconductor layer IL at the outer peripheral portion is not necessary, and this planar space can be omitted. As a result, PIN diodes having the same function can be formed with a small area in a plane. This is advantageous when it is assumed to be mounted on a mobile communication terminal or the like that is trending to be smaller and lighter.

  From another viewpoint, the planar dimension of the N-type intrinsic semiconductor region IL does not reach the end of the N-type cathode substrate without changing the planar dimension of the bottom surface Jb of the main joint surface J. Can be spread within. Thereby, the planar area on the upper surface side of the PIN diode 1B can be increased without significantly affecting the electrical characteristics of the element. For example, after cutting into individual elements by a scribing process, when picking up with a collet or the like, it is desirable that the surface area of the upper surface of the element is large in order to ensure adhesion with a resin or the like. That is, as illustrated in the second embodiment, the PIN diode 1B that can widen the planar area on the upper surface side without changing the characteristics of the element has a structure that can easily avoid a pickup malfunction due to a collet or the like. . As a result, the manufacturing yield and productivity of a semiconductor device having a PIN diode can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the embodiment described above, a PIN junction is formed by forming an N-type intrinsic semiconductor region and a P-type cathode region on an N-type substrate as a cathode, and this is used as a component of the PIN diode. Here, the main junction surface for injecting carriers into the intrinsic semiconductor region has a structure having not only a bottom surface but also a side surface in order to reduce the forward resistance value. Therefore, the P-type region and the N-type region constituting the PIN diode may be reversed.

  For example, as shown in FIG. 1, the planar shape of the trench T formed on the N-type cathode substrate NC, and the N-type intrinsic conductive portion which is a part of the N-type intrinsic semiconductor layer IL separated by the trench T The planar shape of the ID is shown as a substantially square shape. Here, the N-type intrinsic conductive portion ID, which is a part of the N-type intrinsic semiconductor layer IL, is required to be isolated from the end of the N-type cathode substrate NC that is affected by the stress due to the scribe, The shape is not limited to the above. The same applies to the PIN diode 1B having the mesa-shaped N-type intrinsic semiconductor layer IL shown in FIG.

  Further, for example, in the above embodiment, the PIN diode formed on the semiconductor substrate is exemplified as being used as a single semiconductor element (so-called discrete element) mounted on a mobile communication terminal or the like. In addition, it is effective when applied to a power diode having a PIN structure. Further, the PIN diode having the exemplified structure may be integrated with another element on a semiconductor substrate to be a constituent element of an integrated circuit.

  The present invention can be applied to, for example, a semiconductor device manufacturing industry or a semiconductor industry having a PIN diode.

It is a top view of the semiconductor device which is Embodiment 1 of this invention. FIG. 2 is a fragmentary cross-sectional view taken along line x1-x1 of the semiconductor device illustrated in FIG. 1. It is explanatory drawing which shows the injection | pouring condition of a carrier, (a) is explanatory drawing of the cross section of the semiconductor device which the present inventors examined, (b) is the cross section of the semiconductor device which is Embodiment 1 of this invention. It is explanatory drawing. It is a graph which shows the relationship between the forward current and resistance in the electrical property of the semiconductor device which is Embodiment 1 of this invention. It is a flowchart which shows the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; It is a top view of the semiconductor device which is Embodiment 2 of this invention. FIG. 11 is a fragmentary cross-sectional view taken along line x2-x2 of the semiconductor device illustrated in FIG. 10. It is principal part sectional drawing of the semiconductor device which the present inventors examined.

Explanation of symbols

1A, 1B PIN diode 2,5 Surface oxide film 3,6 Opening 4 Ion NC N-type cathode substrate (first semiconductor layer)
PAP type anode layer (second semiconductor layer)
IL N-type intrinsic semiconductor layer (third semiconductor layer)
ID N-type intrinsic conduction part (diode formation part)
S1 surface S2 back surface SIL main surface WIL side surface EC cathode electrode EA anode electrode T trench (groove)
PV protective film h hole J main joint surface Jb bottom surface Js side surface IF forward current value rf resistance value

Claims (5)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type opposite to the first conductivity type;
A third semiconductor layer of a first conductivity type provided between the first semiconductor layer and the second semiconductor layer in contact with each other and set to an impurity concentration so as to be an intrinsic semiconductor; Having a diode,
The second semiconductor layer is formed to a desired depth from the main surface of the diode forming portion of the third semiconductor layer,
In the main surface of the third semiconductor layer, the outer periphery of the second semiconductor layer is formed to terminate at a position away from the outer periphery of the diode forming portion of the third semiconductor layer. Semiconductor device. The semiconductor device according to claim 1,
The diode forming part of the third semiconductor layer is formed on the first semiconductor layer,
The semiconductor device is characterized in that the outer periphery of the diode forming portion of the third semiconductor layer is formed to terminate at a position away from the outer periphery of the first semiconductor layer to the inside. The semiconductor device according to claim 1,
The diode forming portion of the third semiconductor layer is provided by forming a groove extending from the main surface of the third semiconductor layer to the first semiconductor layer along the diode forming portion of the third semiconductor layer. And
The semiconductor device is characterized in that the outer periphery of the diode forming portion of the third semiconductor layer is formed to terminate at a position away from the outer periphery of the first semiconductor layer to the inside. The semiconductor device according to claim 3.
2. The semiconductor device according to claim 1, wherein the groove is formed by chemical etching. The semiconductor device according to any one of claims 1 to 4,
The surface of the diode forming part of the third semiconductor layer is covered with a protective film.

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