JPS5879773A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To eliminate the danger of the generation of undesirable etching by forming a high-concentration region to the source region of an active layer and directly connecting the high-concentation region and an electrode formed to the back of a substrate by a metallic connecting conductor. CONSTITUTION:A concave section 14 reaching the N<+> region 12 of the back of the semi-insulating substrate 1 is shaped at a position corresponding to the N<+> region 12, and an evaporation layer 7, onto which an AuGe alloy layer and an Au layer are laminated, and an Au plated layer 8 are formed onto the back of the substrate 1 containing the bottom 15 and inner wall surface of the concave section 14. Since the source region 12 is shaped as a high concentration region, the region 12 may directly be connected to the back electrode 9, and etching from the back of the substrate for forming the conducting path may be executed up to the region 12, thus resulting in no generation of undesirable etching which has been seen in conventional structure.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a field effect transistor, and particularly to the structure of a source electrode.

(2) Prior Art and Problems In ultra-high frequency field effect transistors made of GaAs, a structure as shown in FIG. 1 has already been proposed as a source electrode. That is,
On an active layer 2 made of n-type GaAs formed on the surface of a semi-insulating substrate 1, a gate electrode 3 making Schottky contact with the active layer 2, and a source electrode 4 and a drain electrode 5 making ohmic contact with the active layer 2 are provided. - A through hole 6 penetrating through the semi-insulating substrate 1 and the active layer 2 is formed in the source electrode 4 forming part on the back side of the completely insulating substrate l, and this through hole 6
On the back side of the semi-insulating substrate 1, including the inner wall surface of the evaporated layer 7, in which an AuGe alloy layer and a gold (^U) layer are laminated, and an Au
It is connected to the outside via a back electrode 9 consisting of a plating layer 8.

In the above conventional structure, the thick Au plating layer 8 (approximately 35 to 5
0 (μm) thickness) acts as a heat sink and has good heat dissipation characteristics. On the other hand, when opening the through hole 6, it is necessary to perform etching until the back surface of the source electrode 4 is exposed, but when the etching reaches the back surface of the source electrode 4, the source electrode 4 and active layer 2 are Since it progresses rapidly along the interface, the source electrode 4 is likely to peel off. Therefore, the amount of etching must be strictly controlled, but this control is difficult in practice, and therefore there is always a risk that undesirable etching will proceed as described above.

(3) Object of the Invention An object of the present invention is to solve the above-mentioned problems and provide a field effect transistor having a structure which is free from the risk of causing the undesirable etching and which is easy to manufacture.

(4) Structure of the Invention The present invention is characterized by a structure in which a high concentration region is provided in the source region of the active layer, and the high concentration region and the back electrode formed on the back surface of the substrate are directly connected by a connecting conductor made of metal. It's what I did.

As an example of the present invention, Ga manufactured according to the present invention will be described below.
Ultra high frequency field effect transistors made of As are connected according to the drawing.

FIG. 2 is a sectional view of a main part showing the above embodiment, and the same parts as in FIG. 1 are designated by the same reference numerals.

In the figure, l is Ga doped with chromium (Cr).
A semi-insulating substrate made of As, 2 an active layer made of n-type GaAs, and a portion 11 directly below the gate electrode 3 into which n-type impurities such as silicon (St) and sulfur (S) were implanted by ion implantation. Concentration approximately 0.5~3 x 10''' (cs
+-3) n-type region, silicon (St) is placed on both sides of the n-type region 11 in an area of 2×10” (cm) or more (
') Consists of three regions, nG51 regions 12 and 13, implanted at i1 degree.

The male region 13 is a drain region, and a metal calanal drain electrode 5 is provided on its surface to form ohmic contact with n-type GaAs. This drain electrode 5 may be made of, for example, an AuGe alloy layer having a thickness of approximately 400 mm and an Au layer having a thickness of approximately 4000 mm laminated thereon.

Another n"l 11112 is a source region, and in the present invention, the source electrode seen in the conventional example can be omitted on this n+ region 12. That is, in this embodiment, the source electrode on the back surface of the semi-insulating substrate l can be omitted. At a position corresponding to n1 area 12,
A recess 14 reaching the n''* area 12 is provided, and the recess 14
A vapor deposited layer 7 in which an AuGe alloy layer (thickness of about 400 cm) and an Au layer (thickness of about 4000 cm) are laminated on the back surface of a semi-insulating substrate l including the bottom surface 15 and inner wall surface of the semi-insulating substrate l; A
U plating layer 8 (thickness approximately 35~50 (,17m)
) is formed.

With the above structure, in this embodiment, n+ type GaAs is exposed on the bottom surface 15 of recess -j4, and AuG
Since the e-alloy is a material that forms ohmic contact with n+ type GaAs, the n region 12, ie, the source region, is directly connected to the back electrode 9 at its bottom. In the device of this embodiment, during operation, carriers are directly supplied to the n'' region 12 from the back electrode 9, flow into the drain region 13 under control of the potential of the gate electrode 3, and are sent out from the drain electrode 5. However, since the n'' region 12 has a low electrical resistance, there is no need to provide an electrode on the surface as in the conventional example.

As described above, in this embodiment, the source region is a high concentration region (n
By forming the n+ region 12), it is sufficient to directly connect the n+ region 12 to the back electrode 9, and etching from the back surface of the substrate for forming the conductive path only needs to be performed until the n'' region 12 is reached. Therefore, the undesirable etching seen in conventional structures does not occur, thereby stabilizing the manufacturing process and improving the manufacturing yield and reliability of the device.

Furthermore, in this embodiment, since there is no need to provide a source electrode on the surface of the active layer 2, the pattern of the gate electrode is not disturbed.
Therefore, it has the great advantage that the corner between the gate electrode and the source electrode can be arbitrarily selected.

In other words, it is desirable that the gate electrode be placed as close as possible to the source region, but if the source electrode is present, a step will occur near the gate electrode pattern in the photoresist test for patterning the gate electrode, and this step and the step of the source electrode will Diffuse reflection of light causes disturbances in the gate electrode pattern. Therefore, it was necessary to leave a gap of at least 1 to 2 [μm] between the gate electrode and the source electrode.

In this embodiment, this problem is also eliminated, the placement position of the gate electrode can be arbitrarily selected in the design, and the patterning accuracy of the gate electrode is improved in the manufacturing process, and the work is facilitated. Therefore, the electrical characteristics and manufacturing yield of the field effect transistor are improved. 'Although the above embodiment has been explained using a planar structure, even if the device to be manufactured has a structure in which the active layer is in a mesa shape, or a recessed structure in which the gate electrode forming part is a recessed part, The invention may be practiced.

Furthermore, the present invention can also be implemented in field effect transistors made of semiconductors other than GaAs.

Furthermore, it goes without saying that there are no particular limitations on the manufacturing method and materials for each part for carrying out the present invention. For example, the ohmic contact to the high concentration region 12 is made of AuGe.
For example, titanium-platinum-gold (Ti-Pt-
It can also be obtained by forming an Au) layer. In addition, the connection conductor that directly connects the high concentration region 12 and the back electrode 9 is
Although it is practical to form them integrally in the same process using the same material as the back electrode 9 as in the above-mentioned embodiment, the two may be formed separately.

Further, although the above-mentioned embodiment shows an example in which the source electrode is removed, this does not prevent the source electrode from being provided on the source region for some reason. For example, in an integrated circuit device manufactured using the present invention, electrodes for connecting the source region and other regions may be provided on both sides.

As explained above, according to the present invention, it is easy to manufacture a field effect transistor, the manufacturing yield is improved, and the electrical characteristics and reliability are improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part for explaining a conventional field effect transistor, and FIG. 2 is a sectional view of a main part showing an embodiment of the present invention. In the figure, 1 is a semi-insulating or insulating substrate, 2 is an active layer, 3 is a gate electrode, 9 is a rear surface Ill, +1 is directly below the gate of the active layer, 12 is a high concentration region, 14 is a recessed part, 15
indicates the bottom of the recess.

Claims (1)

[Claims] an active layer made of a semiconductor having one conductivity type formed on the surface of an insulating or semi-insulating substrate; a gate electrode disposed on the active layer and forming a Schottky contact with the active layer; and the active layer. A field effect transistor having a high concentration region having a higher impurity concentration than directly below the gate electrode in opposing regions sandwiching the region directly below the gate electrode, wherein one of the high concentration regions and the insulating or semi-insulating substrate. A field effect transistor, characterized in that the field effect transistor is connected to a back electrode provided on the back surface of the substrate by a connecting conductor provided through the insulating or semi-insulating substrate.