JPH0580822B2 - - Google Patents
Info
- Publication number
- JPH0580822B2 JPH0580822B2 JP59018543A JP1854384A JPH0580822B2 JP H0580822 B2 JPH0580822 B2 JP H0580822B2 JP 59018543 A JP59018543 A JP 59018543A JP 1854384 A JP1854384 A JP 1854384A JP H0580822 B2 JPH0580822 B2 JP H0580822B2
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- low melting
- metal
- metal film
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002184 metal Substances 0.000 claims description 62
- 229910052751 metal Inorganic materials 0.000 claims description 62
- 238000002844 melting Methods 0.000 claims description 31
- 230000008018 melting Effects 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 25
- 229910045601 alloy Inorganic materials 0.000 claims description 14
- 239000000956 alloy Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 238000009713 electroplating Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 2
- 230000004931 aggregating effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910020658 PbSn Inorganic materials 0.000 description 1
- 101150071746 Pbsn gene Proteins 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体装置の製造方法に関するも
ので、詳しくは半導体基板に形成された凹部を金
属で充てんする方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of filling a recess formed in a semiconductor substrate with metal.
高周波半導体装置においては、半導体チツプの
表面側に形成された電極をできるだけ短距離で接
地する必要がしばしばある。このような場合、半
導体チツプに直接孔をあけて、その孔を通して表
面電極を接地する方法がしばしば用いられる。従
来のこの種の装置は第１図に示すようなものがあ
る。
In high-frequency semiconductor devices, it is often necessary to ground electrodes formed on the front surface of a semiconductor chip over as short a distance as possible. In such cases, a method is often used in which a hole is directly made in the semiconductor chip and a surface electrode is grounded through the hole. A conventional device of this type is shown in FIG.
第１図において、１は、例えばGaAs基板のよ
うな半導体基板、２はこの半導体基板１の表面か
ら形成した孔を充てんしている鍍金金属であり、
３はこの鍍金金属２と導通するように裏面から形
成された孔を覆つている鍍金金属である。 In FIG. 1, 1 is a semiconductor substrate such as a GaAs substrate, and 2 is a plated metal filling a hole formed from the surface of the semiconductor substrate 1.
A plated metal 3 covers a hole formed from the back surface so as to be electrically conductive with the plated metal 2.
次に、従来の製造方法について第２図ａ〜ｆを
用いて説明する。 Next, a conventional manufacturing method will be explained using FIGS. 2a to 2f.
第２図ａにおいて、１は貫通孔を形成すべき半
導体基板で、例えば厚さ450μmのGaAsウエハで
ある。第２図ｂで、電気的にグランドに落す必要
のある部分に表面から、例えば約50μmの深さの
孔４をエツチングにより形成し、第２図ｃのよう
に鍍金金属２を形成する。次に、、第２図ｄのよ
うに半導体基板１の厚さを研摩により、例えば
200μmとし、第２図ｅのように表面側の孔４に対
向させた場所に、裏面から孔４の底部までエツチ
ングを施し裏面孔５を形成する。次いで、第２図
ｆのように、裏面孔５に電界メツキを行い、裏面
孔５の充てんとその周辺部へのメツキを行い鍍金
金属３を形成する。 In FIG. 2a, 1 is a semiconductor substrate in which a through hole is to be formed, and is, for example, a GaAs wafer with a thickness of 450 μm. As shown in FIG. 2b, a hole 4 with a depth of, for example, about 50 μm is formed from the surface in a portion that needs to be electrically grounded by etching, and a plated metal 2 is formed as shown in FIG. 2c. Next, as shown in FIG. 2d, the thickness of the semiconductor substrate 1 is reduced by polishing, for example.
200 μm, and etching is performed from the back side to the bottom of the hole 4 to form a back hole 5 at a location facing the hole 4 on the front side as shown in FIG. 2e. Next, as shown in FIG. 2f, electroplating is performed on the back hole 5, and the back hole 5 is filled and the surrounding area thereof is plated to form the plated metal 3.
しかし、第２図ｆに示すようにメツキにより鍍
金金属３を形成する前記従来方法では、鍍金金属
３は裏面孔５の断面形状に従つてしか形成され
ず、裏面孔５を完全に充てんすることは非常に困
難であつた。そのため、特に高出力半導体の場合
のように発熱を伴う半導体素子においては、裏面
孔５に形成された空間部６が熱放散を困難にし、
十分な電気的特性が得られないなどの欠点があつ
た。 However, in the conventional method of forming the plated metal 3 by plating as shown in FIG. was extremely difficult. Therefore, especially in semiconductor devices that generate heat such as high-output semiconductors, the space 6 formed in the back hole 5 makes it difficult to dissipate heat.
There were drawbacks such as insufficient electrical characteristics.
この発明は、上記のような従来のものの欠点を
除去するためになされたもので、半導体装置に形
成された凹部、特に裏面孔等に低融点金属または
低融点合金を充てんすることにより、放熱特性や
電気特性を向上させた半導体装置を提供するもの
である。
This invention was made in order to eliminate the drawbacks of the conventional devices as described above, and the heat dissipation properties are improved by filling the recesses formed in the semiconductor device, especially the holes on the back surface, with a low melting point metal or a low melting point alloy. The present invention provides a semiconductor device with improved electrical characteristics.
以下、この発明の一実施例を第３図ａ〜ｆによ
つて説明する。
An embodiment of the present invention will be described below with reference to FIGS. 3a to 3f.
第３図ａにおいて、７は無電解鍍金によつて裏
面孔５に形成された電解鍍金用金属膜、例えば
Ni金属膜である。このNi金属膜７を電解鍍金電
極として、Ni金属膜７の上に低融点金属と密着
性のよい鍍金金属膜８、例えば銅を電解鍍金によ
り第３図ｂのように形成する。さらに、第３図ｃ
のように、電解鍍金により形成された鍍金金属膜
８の上に低融点金属、例えばPbSn半田が付着し
にくい材料、例えばTi金属膜９を蒸着あるいはス
パツタにより形成し写真製版を行つた後、第３図
ｄのように裏面孔５およびその周辺部分のTi金属
膜９をエツチングにより除去する。 In FIG. 3a, 7 is a metal film for electrolytic plating formed in the back hole 5 by electroless plating, e.g.
It is a Ni metal film. Using this Ni metal film 7 as an electrolytic plating electrode, a plating metal film 8 having good adhesion to a low melting point metal, such as copper, is formed on the Ni metal film 7 by electrolytic plating as shown in FIG. 3b. Furthermore, Figure 3c
After forming a low melting point metal such as a material to which PbSn solder is difficult to adhere, such as a Ti metal film 9, by vapor deposition or sputtering on the plated metal film 8 formed by electrolytic plating, and performing photolithography, As shown in FIG. 3d, the Ti metal film 9 in the back hole 5 and its surrounding area is removed by etching.
次いで蒸着により低融点金属１０を蒸着する。
次に、第３図ｅのように、写真製版およびエツチ
ングにより裏面孔５およびその周辺部分の低融点
金属１０を凝集させるにたる量とする。次に、低
融点金属１０が融解するような温度に半導体基板
１を加熱し、第３図ｆのように、裏面孔５に低融
点金属１０を凝集させた後、冷却し固化させ裏面
孔５を充てんする。 Next, a low melting point metal 10 is deposited by vapor deposition.
Next, as shown in FIG. 3e, photolithography and etching are performed to obtain an amount sufficient to aggregate the low melting point metal 10 in the back hole 5 and its surrounding area. Next, the semiconductor substrate 1 is heated to a temperature at which the low melting point metal 10 melts, and the low melting point metal 10 is agglomerated in the back hole 5 as shown in FIG. Fill it with.
このように、裏面孔５を充てんした半導体装
置、例えば高出力GaAsFETあるいはICは、従来
のものよりも放熱特性が向上し、また、電気特性
も向上させることができる。 In this way, a semiconductor device with the back hole 5 filled, such as a high-power GaAs FET or IC, has improved heat dissipation characteristics and electrical characteristics compared to conventional devices.
なお、上記実施例では、低融点金属１０を蒸着
により付着させ、半導体基板１を加熱することに
より充てんをしているが、第４図のように低融点
金属１０を粒状にし、孔の中に入れ加熱すること
によつても同様の効果が得られる。または鍍金法
により低融点金属１０を付けても同様な効果が得
られるのは当然である。また、低融点金属１０は
合金であつてもよいことはいうまでもない。さら
に裏面孔５に限らず一般には凹部であればこの発
明を適用することができる。 In the above embodiment, the low melting point metal 10 is deposited by vapor deposition and filling is performed by heating the semiconductor substrate 1, but as shown in FIG. A similar effect can be obtained by heating it. Alternatively, it is a matter of course that the same effect can be obtained even if the low melting point metal 10 is attached by a plating method. Further, it goes without saying that the low melting point metal 10 may be an alloy. Further, the present invention is applicable not only to the back hole 5 but also to any concave portion.
以上説明したように、この発明によれば、凹部
を有する半導体基板の裏面孔に電解鍍金用金属膜
を形成させる工程と、この電解鍍金用金属膜の上
に低融点金属または合金と密着性のよい鍍金金属
膜を形成させる工程と、この鍍金金属膜の上に低
融点金属または合金が付着しにくい金属膜を形成
させる工程と、裏面孔およびその周辺部分の金属
膜を除去させる工程と、鍍金金属膜と金属膜との
上に低融点金属、または合金を付着させる工程
と、半導体基板を低融点金属または合金の融点以
上に加熱し、低融点金属または合金を融解させ凹
部内に凝集させた後冷却し、固化させ凹部内に金
属を充填させる工程とからなるようにしたので、
低融点金属または合金を凹部全体に充填を施すこ
とができるとともに、凹部以外に部分に低融点金
属または合金が広がるのを抑えることができ、そ
のため、凹部における放熱特性、電気的特性を向
上させることができる利点がある。
As explained above, according to the present invention, there is a step of forming a metal film for electrolytic plating in a hole on the back surface of a semiconductor substrate having a concave portion, and a step of forming a metal film for electrolytic plating on the metal film for electrolytic plating with a low melting point metal or alloy. A step of forming a good plating metal film, a step of forming a metal film to which a low melting point metal or alloy is difficult to adhere on the plating metal film, a step of removing the metal film in the back hole and its surrounding area, and plating. A process of attaching a low melting point metal or alloy onto the metal film and the metal film, and heating the semiconductor substrate above the melting point of the low melting point metal or alloy to melt the low melting point metal or alloy and cause it to aggregate in the recess. The process consists of post-cooling, solidifying, and filling the recess with metal.
The entire recess can be filled with the low melting point metal or alloy, and the spread of the low melting point metal or alloy to areas other than the recess can be suppressed, thereby improving the heat dissipation characteristics and electrical characteristics of the recess. It has the advantage of being able to
第１図は従来の半導体装置を示す断面側面図、
第２図ａ〜ｆは従来の半導体装置の製造方法の各
工程を示す断面図、第３図ａ〜ｆはこの発明の半
導体装置の製造方法の一実施例の各工程を示す断
面図、第４図はこの発明の他の実施例の主要工程
を示す断面図である。
図中、１は半導体基板、２は鍍金金属、５は裏
面孔、６は空間部、７はNi金属膜、８は鍍金金
属膜、９はTi金属膜、１０は低融点金属である。
なお、図中の同一符号は同一または相当部分を示
す。
FIG. 1 is a cross-sectional side view showing a conventional semiconductor device.
2a to 2f are cross-sectional views showing each step of a conventional semiconductor device manufacturing method, and FIGS. 3 a to 3f are sectional views showing each step of an embodiment of the semiconductor device manufacturing method of the present invention. FIG. 4 is a sectional view showing the main steps of another embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a plated metal, 5 is a back hole, 6 is a space, 7 is a Ni metal film, 8 is a plated metal film, 9 is a Ti metal film, and 10 is a low melting point metal.
Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
用金属膜を形成させる工程と、この電解鍍金用金
属膜の上に低融点金属または低融点合金と密着性
のよい鍍金金属膜を形成させる工程と、この鍍金
金属膜の上に前記低融点金属または低融点合金が
付着しにくい金属膜を形成させる工程と、前記裏
面孔およびその周辺部分の前記金属膜を除去させ
る工程と、前記鍍金金属膜と前記金属膜との上に
前記低融点金属または低融点合金を付着させる工
程と、前記半導体基板を前記低融点金属または低
融点合金の融点以上に加熱し、前記低融点金属ま
たは低融点合金を融解させ前記凹部内に凝集させ
た後冷却し、固化させ前記凹部内に金属を充填さ
せる工程とを含む半導体装置の製造方法。1. A step of forming a metal film for electrolytic plating in a hole on the back surface of a semiconductor substrate having a concave portion, and a step of forming a plating metal film with good adhesion to a low melting point metal or a low melting point alloy on this metal film for electrolytic plating. , a step of forming a metal film to which the low melting point metal or low melting point alloy is difficult to adhere on the plated metal film; a step of removing the metal film in the back hole and its surrounding area; A step of attaching the low melting point metal or low melting point alloy onto the metal film, and heating the semiconductor substrate to a temperature higher than the melting point of the low melting point metal or low melting point alloy to melt the low melting point metal or low melting point alloy. A method for manufacturing a semiconductor device, comprising the step of aggregating metal into the recess, cooling and solidifying the metal, and filling the recess with metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59018543A JPS60161651A (en) | 1984-02-02 | 1984-02-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59018543A JPS60161651A (en) | 1984-02-02 | 1984-02-02 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60161651A JPS60161651A (en) | 1985-08-23 |
| JPH0580822B2 true JPH0580822B2 (en) | 1993-11-10 |
Family
ID=11974546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59018543A Granted JPS60161651A (en) | 1984-02-02 | 1984-02-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60161651A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2703908B2 (en) * | 1987-11-20 | 1998-01-26 | 日本電気株式会社 | Compound semiconductor device |
| JPH0777224B2 (en) * | 1988-07-18 | 1995-08-16 | 日本電気株式会社 | Method for manufacturing monolithic integrated circuit device |
| JPH0821598B2 (en) * | 1989-09-12 | 1996-03-04 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
| JP2803408B2 (en) * | 1991-10-03 | 1998-09-24 | 三菱電機株式会社 | Semiconductor device |
| JP5228381B2 (en) | 2007-06-25 | 2013-07-03 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
| CN113809030B (en) * | 2021-11-16 | 2022-03-15 | 深圳市时代速信科技有限公司 | Semiconductor device and method for manufacturing semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5092682A (en) * | 1973-12-14 | 1975-07-24 | ||
| JPS5879773A (en) * | 1981-11-06 | 1983-05-13 | Fujitsu Ltd | Field-effect transistor |
-
1984
- 1984-02-02 JP JP59018543A patent/JPS60161651A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5092682A (en) * | 1973-12-14 | 1975-07-24 | ||
| JPS5879773A (en) * | 1981-11-06 | 1983-05-13 | Fujitsu Ltd | Field-effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60161651A (en) | 1985-08-23 |
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