JP2703908B2 - Compound semiconductor device - Google Patents

Compound semiconductor device

Info

Publication number
JP2703908B2
JP2703908B2 JP62293317A JP29331787A JP2703908B2 JP 2703908 B2 JP2703908 B2 JP 2703908B2 JP 62293317 A JP62293317 A JP 62293317A JP 29331787 A JP29331787 A JP 29331787A JP 2703908 B2 JP2703908 B2 JP 2703908B2
Authority
JP
Japan
Prior art keywords
semiconductor device
compound semiconductor
electrode layer
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62293317A
Other languages
Japanese (ja)
Other versions
JPH01135030A (en
Inventor
和良 植田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62293317A priority Critical patent/JP2703908B2/en
Publication of JPH01135030A publication Critical patent/JPH01135030A/en
Application granted granted Critical
Publication of JP2703908B2 publication Critical patent/JP2703908B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Die Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は化合物半導体装置に関する。 〔従来の技術〕 最近の半導体装置の高周波応用の普及に伴い、その信
頼性の向上がますます重要となってきた。 従来のマイクロ波等の高周波用半導体装置としてGaAs
等の化合物半導体を用いた電界効果トランジスタが多く
使用されている。 この種の化合物半導体装置では、従来からその実装基
板にはんだ付などで載置するに際のソース電極と実装基
板側の接地電極との接続において、寄生インダクタンス
による高周波特性の低下をさける構造がとられていた。 すなわち、化合物半導体装置のソース電極層に対応す
る部分に半導体基板の裏面側から貫通穴（以下バイアホ
ールという）を開孔し、このバイアホールを通してソー
ス電極層を実装基板の接地電極層に電気的に接続する構
造を採用していた。 第３図は従来の化合物半導体装置の一例の断面図であ
る。 化合物半導体装置は、半絶縁性GaAs基板１とその上層
の活性層２と、その上のショットキー接合のゲート電極
３とソース及びドレインの各電極４及び５と、それらの
電極4,5に接続するソース及びドレインの各上部電極層
６及び７を含んで構成している。 半絶縁性GaAs基板１の表面のソース上部電極層６に対
応してGaAs基板１の裏面側にバイアホール1aを開孔し、
このバイアホール１の内側面からGaAs基板１の裏面にわ
たって金めっきの裏面電極層９を形成し、内側導電層9a
がソース上部電極層６と裏面電極層９を電気的に接続し
ている。 〔発明が解決しようとする問題点〕 第４図は従来の問題点を説明するために示した実装基
板に載置した化合物半導体装置の断面模式図である。 実装基板11の表面に半絶縁性GaAs基板１の裏面電極層
９をはさんだ層12でろう付して化合物半導体を載置す
る。 この工程で、バイアホール1aの内側面にははんだ付着
部2aに示すようにはんだ材が盛り上り、その冷却と凝縮
時の機械的応力でバイアホールの天床部の近傍のGaAs基
板の薄い場所にクラック部13が生じ化合物半導体装置の
品質が劣化する。 上述した従来の化合物半導体装置は、バイアホールの
内側に導電層が露出して、実装基板に実装する場合のは
んだ付着によりその固化時の機械的応力で半絶縁基板の
表面側の薄い部分が破損するという問題があった。 本発明の目的は、実装基板にはんだ付する際に品質劣
化のない化合物半導体装置を提供する事にある。 〔問題点を解決するための手段〕 本発明の化合物半導体装置は、半絶縁性基板の表面側
に形成した表面電極層と、前記半絶縁性基板の裏面側に
形成した裏面電極層と、前記半絶縁性基板を開孔してそ
の内側面を導電層で覆い前記二つの表面及び裏面電極層
間を電気的に接続するバイアホールとを有する化合物半
導体装置において、前記バイアホールの前記導電層の表
面及び前記裏面電極層の表面のうち前記バイアホールの
前記導電層の表面のみを覆ったはんだ材になじまない絶
縁膜または金属層を設け、前記裏面電極層をはんだ層に
より実装基板に固着した際に前記はんだ材になじまない
絶縁膜または金属層が露出する空洞が前記バイアホール
の内部に形成されるようにしたことを特徴とする。 〔実施例〕 次に、本発明の実施例を図面を参照して説明する。 第１図（ａ）〜（ｃ）は本発明の一実施例を説明する
ための工程順に示した半導体チ４ップの断面図である。 先ず、第１図（ａ）に示すように、半絶縁性GaAs基板
１に活性層２を形成し、この上にシャットキ接合のゲー
ト電極３とオーミック接触のソース及びドレインの各電
極４及び５をそれぞれ形成する。 そして、GaAs基板１上にソース及びドレインの各電極
４及び５に接続してソース及びドレインの上部電極層６
及び７をそれぞれ形成する。 次にゲート電極３を保護膜８で被覆する。 次に、第１図（ｂ）に示すように、ソース上部電極層
６に対応して、GaAs基板１の裏面側から断面テーパ状に
開孔して天床がソース上部電極層６に接するバイアホー
ル1aを設ける。 そして、このバイアホール1aの内側面及びGaAs基板１
の裏面に金めっきの内側薄電層9a及び裏面電極層９を形
成する。 このとき，裏面電極層９はバイアホール1aの内側導電
層9aを介して表面のソース上部電極層６に電気接続され
る。 このように従来と同様の方法で第１図（ｂ）に示す半
導体チップを製造する。 最後に、第１図（ｃ）に示すように、バイアホール1a
の内側導電層9aをはんだ材になじみ難い金属層としてTi
N膜10を形成する。 第２図は本発明の効果を説明するために示した実装基
板に載置した化合物半導体装置の断面模式図である。バ
イアホール1aの内側面の表面のTiN膜は、はんだを付着
しないので、はんだ層12の冷却時に半絶縁性GaAs層１の
上層部に熱による機械的応力がかからず、従ってバイア
ホール1aの天床部近傍にクラックの発生することはな
い。 本実施例では、はんだ材になじみ難い金属層としてTi
Nを用いたがTiでもよく、また金属層の代りにSiO2,SiN
膜等の絶縁膜を用いても良い。 〔発明の効果〕 以上説明したように本発明は、半絶縁性基板内のバイ
アホールの導電層の表面にはんだ付性のよくない物質を
設けることにより、実装基板にはんだ付する際に品質劣
化のない化合物半導体装置が得られる。Description: TECHNICAL FIELD The present invention relates to a compound semiconductor device. [Prior Art] With the recent spread of high frequency applications of semiconductor devices, it has become increasingly important to improve their reliability. G a s as a conventional semiconductor device for high frequencies such as microwaves
Field effect transistors using compound semiconductors such as those described above are widely used. In this type of compound semiconductor device, there has been a conventional structure that prevents a reduction in high-frequency characteristics due to parasitic inductance in connection between a source electrode and a ground electrode on a mounting substrate when the device is mounted on the mounting substrate by soldering or the like. Had been. That is, a through hole (hereinafter, referred to as a via hole) is formed in the portion corresponding to the source electrode layer of the compound semiconductor device from the back surface side of the semiconductor substrate, and the source electrode layer is electrically connected to the ground electrode layer of the mounting substrate through the via hole. The connection structure was adopted. FIG. 3 is a sectional view of an example of a conventional compound semiconductor device. Compound semiconductor device, a semi-insulating G a A s the substrate 1 and the active layer 2 of the upper layer, the Schottky gate electrode 3 and the electrode 4 and 5 of the source and drain of the junction thereon, the electrodes 4, The upper electrode layers 6 and 7 of source and drain connected to 5 are configured. Via holes 1a and opening on the back side of the G a A s the substrate 1 corresponding to the source upper electrode layer 6 of the semi-insulating G a A s the surface of the substrate 1,
G a A s a back electrode layer 9 of the gold plating is formed over the back surface of the substrate 1, the inner conductive layer 9a from the inner surface of the via hole 1
Electrically connects the source upper electrode layer 6 and the back electrode layer 9. [Problems to be Solved by the Invention] FIG. 4 is a schematic cross-sectional view of a compound semiconductor device mounted on a mounting board shown to explain a conventional problem. On the surface of the mounting substrate 11 with brazed semi-insulating G a A s layers 12 sandwiching the rear surface electrode layer 9 of the substrate 1 for mounting a compound semiconductor. In this step, the via hole 1a of the uplink prime solder material as shown in solder attachment portion 2a on the inner surface, G a A s the substrate in the vicinity of the top floor of the via-hole in the mechanical stress at the time of condensation and cooling thereof Cracks 13 occur in places where the thickness is small, and the quality of the compound semiconductor device deteriorates. In the conventional compound semiconductor device described above, the conductive layer is exposed inside the via hole, and the thin portion on the surface side of the semi-insulating substrate is damaged by mechanical stress during solidification due to solder adhesion when mounting on the mounting substrate. There was a problem of doing. An object of the present invention is to provide a compound semiconductor device which does not deteriorate in quality when soldering to a mounting board. [Means for Solving the Problems] The compound semiconductor device of the present invention includes a front electrode layer formed on the front side of the semi-insulating substrate, a back electrode layer formed on the back side of the semi-insulating substrate, A compound semiconductor device having a semi-insulating substrate, a via hole covering the inner side surface of the semi-insulating substrate with a conductive layer, and electrically connecting the two front and back electrode layers. And providing an insulating film or a metal layer that is not compatible with the solder material that covers only the surface of the conductive layer of the via hole on the surface of the back electrode layer, and that the back electrode layer is fixed to a mounting board by a solder layer. A cavity in which an insulating film or a metal layer which does not fit the solder material is exposed is formed inside the via hole. Embodiment Next, an embodiment of the present invention will be described with reference to the drawings. FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. First, as shown in FIG. 1 (a), semi-insulating G a A s the substrate 1 of the active layer 2 is formed on the gate electrode 3 and the source and drain electrodes of the ohmic contact 4 of Shattoki joined onto this And 5 are respectively formed. Then, G a A s on the substrate 1 connected to the electrodes 4 and 5 of the source and drain source and drain of the upper electrode layer 6
And 7 are respectively formed. Next, the gate electrode 3 is covered with a protective film 8. Next, as shown in FIG. 1B, corresponding to the source upper electrode layer 6, a hole is formed in a tapered cross section from the back surface side of the GaAs substrate 1 so that the ceiling becomes the source upper electrode layer 6. Is provided with a via hole 1a. The inner and G a A s the substrate 1 of the via hole 1a
The inner thin layer 9a of gold plating and the back electrode layer 9 are formed on the back of the substrate. At this time, the back electrode layer 9 is electrically connected to the source upper electrode layer 6 on the front surface via the conductive layer 9a inside the via hole 1a. Thus, the semiconductor chip shown in FIG. 1 (b) is manufactured by the same method as the conventional one. Finally, as shown in FIG. 1 (c), the via hole 1a
The inner conductive layer 9a of Ti is used as a metal layer that is difficult to
An N film 10 is formed. FIG. 2 is a schematic cross-sectional view of a compound semiconductor device mounted on a mounting substrate shown for explaining the effect of the present invention. T i N film on the surface of the inner side surface of the via hole 1a is does not adhere to solder, not applied mechanical stress due to heat at the top of the cooling semi-insulating when G a A s layer 1 of the solder layer 12, Therefore, no crack is generated near the ceiling of the via hole 1a. In this embodiment, T i as a familiar hard metal layer to the solder material
S i O 2 in place of was used N well even T i, also metal layers, S i N
An insulating film such as a film may be used. [Effects of the Invention] As described above, the present invention provides a material having poor solderability on the surface of a conductive layer of a via hole in a semi-insulating substrate, thereby deteriorating quality when soldering to a mounting substrate. And a compound semiconductor device free from the problem.

【図面の簡単な説明】 第１図（ａ）〜（ｃ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第２図は本
発明の効果を説明するために示した実装基板に載置した
化合物半導体装置の断面模式図、第３図は従来の化合物
半導体装置の一例の断面図、第４図は従来の問題点を説
明するために示した実装基板に載置した化合物半導体装
置の断面模式図である。 １……半絶縁性GaAs基板、1a……バイアホール、６……
ソース上部電極層、９……裏面電極層、9a……内側導電
層、10……TiN膜。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 explains the effect of the present invention. FIG. 3 is a schematic cross-sectional view of a compound semiconductor device mounted on a mounting board shown in FIG. 3, FIG. 3 is a cross-sectional view of an example of a conventional compound semiconductor device, and FIG. 4 is a mounting board shown to explain a conventional problem. 1 is a schematic cross-sectional view of a compound semiconductor device mounted on a semiconductor device. 1 ...... semi-insulating G a A s substrate, 1a ...... via holes, 6 ......
Source upper electrode layer, 9 ...... back electrode layer, 9a ...... inner conductive layer, 10 ...... T i N film.

Claims (1)

(57)【特許請求の範囲】 １．半絶縁性基板の表面側に形成した表面電極層と、前
記半絶縁性基板の裏面側に形成した裏面電極層と、前記
半絶縁性基板を開口してその内側面を導電層で覆い前記
二つの表面及び裏面電極層間を電気的に接続するバイア
ホールとを有する化合物半導体装置において、前記バイ
アホールの前記導電層の表面及び前記裏面電極層の表面
のうち前記バイアホールの前記導電層の表面のみを覆っ
てはんだ材になじまない絶縁膜または金属層を設け、前
記裏面電極層をはんだ層により実装基板に固着した際に
前記はんだ材になじまない絶縁膜または金属層が露出す
る空洞が前記バイアホールの内部に形成されるようにし
たことを特徴とする化合物半導体装置。(57) [Claims] A front electrode layer formed on the front side of the semi-insulating substrate, a back electrode layer formed on the back side of the semi-insulating substrate, and an opening formed in the semi-insulating substrate to cover an inner surface thereof with a conductive layer; A compound semiconductor device having a via hole that electrically connects the front surface and the back electrode layer, wherein only the surface of the conductive layer of the via hole out of the surface of the conductive layer of the via hole and the surface of the back electrode layer An insulating film or a metal layer which does not fit the solder material is provided so as to cover the insulating film or the metal layer which is not compatible with the solder material when the back electrode layer is fixed to the mounting board by the solder layer. A compound semiconductor device, wherein the compound semiconductor device is formed inside.
JP62293317A 1987-11-20 1987-11-20 Compound semiconductor device Expired - Fee Related JP2703908B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62293317A JP2703908B2 (en) 1987-11-20 1987-11-20 Compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62293317A JP2703908B2 (en) 1987-11-20 1987-11-20 Compound semiconductor device

Publications (2)

Publication Number Publication Date
JPH01135030A JPH01135030A (en) 1989-05-26
JP2703908B2 true JP2703908B2 (en) 1998-01-26

Family

ID=17793268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62293317A Expired - Fee Related JP2703908B2 (en) 1987-11-20 1987-11-20 Compound semiconductor device

Country Status (1)

Country Link
JP (1) JP2703908B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027189A (en) * 1990-01-10 1991-06-25 Hughes Aircraft Company Integrated circuit solder die-attach design and method
DE102009044086A1 (en) * 2009-09-23 2011-03-24 United Monolithic Semiconductors Gmbh Method for producing an electronic component and electronic component produced by this method
JP5621334B2 (en) * 2010-06-10 2014-11-12 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device
JP6173994B2 (en) * 2014-10-16 2017-08-02 ウシオオプトセミコンダクター株式会社 Optical semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60161651A (en) * 1984-02-02 1985-08-23 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS62128179A (en) * 1985-11-29 1987-06-10 Nec Corp Semiconductor device

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