JPS5914906B2 - Method for manufacturing field effect transistors - Google Patents
Method for manufacturing field effect transistorsInfo
- Publication number
- JPS5914906B2 JPS5914906B2 JP13915479A JP13915479A JPS5914906B2 JP S5914906 B2 JPS5914906 B2 JP S5914906B2 JP 13915479 A JP13915479 A JP 13915479A JP 13915479 A JP13915479 A JP 13915479A JP S5914906 B2 JPS5914906 B2 JP S5914906B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- substrate
- layer
- forming
- concave portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 4
- 238000000034 method Methods 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 238000009740 moulding (composite fabrication) Methods 0.000 claims 1
- 239000007772 electrode material Substances 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 241000283707 Capra Species 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electrodes Of Semiconductors (AREA)
- Die Bonding (AREA)
- Junction Field-Effect Transistors (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は電界効果トランジスタの製造方法に係り、特
にその主電極とヒートシンクが電気的に１０接続した構
造の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor, and particularly to a method for forming a structure in which a main electrode and a heat sink are electrically connected.
以下ヒ化ガリウム（ＧａＡｓ）を用いた電極効果トラン
ジスタ（以下「ＧａＡｓＦＥＴ」と略称す匂を例にとつ
て説明する。ＧａＡｓＦＥＴはマイクロ波領域における
低雑音１５増巾器、高出力増巾器、発振器などに利用さ
れている。The following will explain an example of an electrode effect transistor (hereinafter abbreviated as "GaAsFET") using gallium arsenide (GaAs). It is used for such things.
そしてこの性能は主にゲート長を短くした微細パターン
構造及びソース電極抵抗等の寄生要素の低減により向上
させることができる。ゲート長を短くするために電子ビ
ーム露光、Ｘｘ線リングラフィなどの手法が用いられる
。This performance can be improved mainly by a fine pattern structure with a shortened gate length and a reduction in parasitic elements such as source electrode resistance. Techniques such as electron beam exposure and X-ray phosphorography are used to shorten the gate length.
電極抵抗を低減するために電極の金属膜を厚くしたり、
イオン注入法によリソース電極部分にキャリア濃度の高
いＮ形層を設けオージク接触抵抗を低くする方法がある
。ソース電極からパッケージ電極部ク５ へのリード線
のインダクタンスを低減させるためにシートグランドの
方法がある。第１図は従来のＧａＡｓＦＥＴの製造方法
を説明するための各工程段階を示す断面図、第２図は従
来のＧａＡｓＦＥＴのワイヤボンディング方法を示す断
ｎ 面図である。In order to reduce electrode resistance, the metal film of the electrode can be made thicker,
There is a method of lowering the Ozark contact resistance by providing an N-type layer with high carrier concentration in the resource electrode portion by ion implantation. In order to reduce the inductance of the lead wire from the source electrode to the package electrode section 5, there is a sheet ground method. FIG. 1 is a cross-sectional view showing each process step for explaining a conventional GaAsFET manufacturing method, and FIG. 2 is a cross-sectional view showing a conventional GaAsFET wire bonding method.
まず、第１図ａに示すように、半絶縁性基板１と、その
一主面に形成され不純物濃度が約１〜３×１０７／Ｃｄ
のＮ形層２とからなるＧａＡｓウェハの上記Ｎ形層２の
表面上に写真製版とソフトオフ３５法によつてソース電
極３及びドレイン電極４を形成する。First, as shown in FIG.
A source electrode 3 and a drain electrode 4 are formed on the surface of the N-type layer 2 of the GaAs wafer by photolithography and the soft-off method.
つづいて１つのウェハ上に形成される複数のチップ（図
には１チップのみ示す。）の各チツプ間の絶縁を寄生容
量低減のために、第１図ｂに示すようにソース電極３、
ドレイン電極４及びゲート形成領域５″を除いた残余の
部分のＮ形層２をエツチング除去する。次にゲート形成
領域５″のうち真にゲート電極を形成する部分を除いて
全ｈ面をレジストで覆つた上で、レジスト膜全面に金属
膜を蒸着させた後、リフトオフ法でグート電極５を形成
すると、第１図Ｃに示すような所望のＧａＡｓＦＥＴが
得られる。第２図ａは第１図の工程を経て得られた小信
号用ＧａＡｓＦＥＴのワイヤボンデイング方法を示した
ので、各電極からワイヤ８でバツケージへの電気的接続
を行つている。Next, in order to reduce the parasitic capacitance of the insulation between the chips of a plurality of chips (only one chip is shown in the figure) formed on one wafer, as shown in FIG.
The remaining part of the N-type layer 2 except for the drain electrode 4 and the gate formation region 5'' is removed by etching. Next, the entire h-plane of the gate formation region 5'' except for the part where the gate electrode will be formed is etched with resist. A metal film is deposited on the entire surface of the resist film, and then a goat electrode 5 is formed by a lift-off method, thereby obtaining a desired GaAsFET as shown in FIG. 1C. FIG. 2a shows a wire bonding method for the small signal GaAsFET obtained through the process shown in FIG. 1, in which each electrode is electrically connected to the package by wire 8.
第２図ｂのものではソース電極はワイヤを使わずシート
グランド方式によつてバツケージ電極７に電気的接続を
行つている。図中、６はダイボンダ用ハンダである。第
２図ｃは第１図と同様な製造工程により作製された高出
力ＧａＡｓＦＥＴのワイヤボンデイング方法を示したも
のである。In the case of FIG. 2b, the source electrode is electrically connected to the bagage electrode 7 by the sheet ground method without using wires. In the figure, 6 is solder for die bonder. FIG. 2c shows a wire bonding method for a high-power GaAsFET manufactured by the same manufacturing process as in FIG.
ところで、第１図ｃに示したような構造のＦＥＴはソー
ス電極３の電気的接続をワイヤで行うため周波数が高く
なるとリード線のインダクタンスの影響が大きくなり性
能を低下させる。Incidentally, in the FET having the structure as shown in FIG. 1c, the source electrode 3 is electrically connected by a wire, and therefore, as the frequency increases, the influence of the inductance of the lead wire increases and the performance deteriorates.
特に高出力ＦＥＴでは多数のワイヤを使用するためイン
ダクタンスの影響は大である。又、この様な構造では半
絶縁性基板１があるため熱放散が悪くなり、入力が大き
い高出力ＦＥＴでは熱抵抗の低減が重要な問題となつて
いる。この発明はこのような点に鑑みてなされたもので
、半導体ウエ・・表面上に凹部を形成し、この凹部を通
して主電極と電気的に接続する様に半導体裏面に金属厚
膜（プレーテツドヒートシンク）を形成することによつ
て、主電極の電気的接続にワイヤを用いる必要がなくな
るとともに金属厚膜により放熱が改善され性能を大巾に
向上できるＧａＡｓＦＥＴ構造の製造力法を提供せんと
するものである。Particularly in high-output FETs, since a large number of wires are used, the influence of inductance is large. Furthermore, in such a structure, heat dissipation is poor due to the presence of the semi-insulating substrate 1, and reduction of thermal resistance has become an important issue in high-output FETs with large inputs. This invention was made in view of these points. A recess is formed on the surface of the semiconductor wafer, and a thick metal film (plated metal film) is formed on the back surface of the semiconductor so as to be electrically connected to the main electrode through the recess. The present invention aims to provide a manufacturing method for a GaAsFET structure that eliminates the need to use wires for electrical connection of the main electrode by forming a heat sink (heat sink), improves heat dissipation by using a thick metal film, and greatly improves performance. It is something.
第３図はこの発明の方法の一実施例を説明するための各
工程段階を示し、第４図はこの発明に依り製造されたＧ
ａＡｓＦＥＴのワイヤボンデング方法を示したものであ
る。FIG. 3 shows each process step for explaining an embodiment of the method of the present invention, and FIG. 4 shows a G
This figure shows a wire bonding method for aAsFET.
まず、第３図ａに示す様に半導体ウエハのＮ形層２側に
所望の深さの凹部ａを形成し、しかる後第１図と同様の
製造工程でソース電極３、トレーノン電極４、及びグー
ト電極５を第３図ｂに示す様に形成する。First, as shown in FIG. 3a, a recess a of a desired depth is formed on the N-type layer 2 side of a semiconductor wafer, and then a source electrode 3, a trenon electrode 4, and The goat electrode 5 is formed as shown in FIG. 3b.
それから第３図ｃに示すように半導体ウエハ裏面の半絶
縁性基板１を凹部９の底に到達するまでエツチング除去
した後蒸着により金属膜１０を形成する。上記エツチン
グ除去された部分に金属膜１０を用いて所定部分だけ第
３図ｄのように厚メツキしプレーテツドヒートシンク１
２を形成する。この後第３図ｅに示す様にプレーテツド
ヒートシンク１２、Ｎ形層２を電導路に用いてソース電
極３をメツキし、さらにドレイン電極４を所望の厚さだ
けメツキしてメツキ部１４を形成する。図中、１３はレ
ジストである。そして第３図ｆの様なプレテツドヒート
シンク付きＧａＡｓＦＥＴが得られる。第４図ａはこの
発明より製造された小信号用ＧａＡｓＦＥＴのワイヤポ
ンデング方法を示したもので、ソース電極３の電気的接
続はプレーテイツドヒートシンク１２を通してバツケー
ジ電極７へ行われる。Then, as shown in FIG. 3c, the semi-insulating substrate 1 on the back surface of the semiconductor wafer is removed by etching until it reaches the bottom of the recess 9, and then a metal film 10 is formed by vapor deposition. The plated heat sink 1 is formed by thickly plating only a predetermined portion using the metal film 10 on the etched portion as shown in FIG. 3d.
form 2. Thereafter, as shown in FIG. 3e, the source electrode 3 is plated using the plated heat sink 12 and the N-type layer 2 as a conductive path, and the drain electrode 4 is plated to a desired thickness to form the plated part 14. Form. In the figure, 13 is a resist. Then, a GaAsFET with a pre-treaded heat sink as shown in FIG. 3f is obtained. FIG. 4a shows a wire bonding method for a small signal GaAsFET manufactured according to the present invention, in which the source electrode 3 is electrically connected to the bagage electrode 7 through the plated heat sink 12.
第４図ｂはこの発明により製造された高出力ＧａＡｓＦ
ＥＴのワイヤボンデイング方法を示したものでソース電
極３の電気的接続は第４図ａと同様な方法で行われてお
り、従来のソース電極３間をリード線で接続するという
工程が省略されている。FIG. 4b shows a high-power GaAsF fabricated according to the present invention.
This figure shows the wire bonding method of ET, and the electrical connection of the source electrodes 3 is performed in the same manner as shown in Fig. 4a, and the conventional process of connecting the source electrodes 3 with lead wires is omitted. There is.
上記実施例ではＧａＡｓを用いた場合について述べたが
、この発明はＧａＡｓに限定されるものでなく、一般に
半導体に適用できることは自明である。また主電極、即
ちソース電極３とドレイン電極４とを入れ替えて使用し
ても同様の効果がある。以上詳述したように、この発明
の方法ではあらかじめ半導体表面に形成した凹部をブレ
ーテツトヒートシンクとを電気的に接続できるので主電
極のワイヤボンデイング工程が省略され作業時間が大巾
に減少する。更にリード線の配線がなくなつたこと、ブ
レーテイツドヒートシンクにより放熱が改善され、ソー
ス電極及びドレイン電極を厚メツキしたことによりシー
ト抵抗の低減がなされ、高周波領域での特性が大巾に改
善される。Although the above embodiment describes the case where GaAs is used, it is obvious that the present invention is not limited to GaAs and can be applied to semiconductors in general. Further, the same effect can be obtained even if the main electrodes, that is, the source electrode 3 and the drain electrode 4 are used interchangeably. As described in detail above, in the method of the present invention, the concave portion previously formed on the semiconductor surface can be electrically connected to the plated heat sink, so the wire bonding process for the main electrode is omitted, and the working time is greatly reduced. Furthermore, the elimination of lead wires, improved heat dissipation with a bragged heat sink, and thick plating of the source and drain electrodes reduced sheet resistance, greatly improving characteristics in the high frequency range. Ru.
第１図ａ〜第１図ｃは従来の製造方法を説明するための
各工程段階を示す断面図、第２図ａ−ｃは従来の力法で
製造されたＧａＡｓＦＥＴのワイヤボンデイング方法を
示す断面図、第３図ａ−ｆはこの発明の一実施例を説明
するための各工程段階を示す断面図である。
第４図Ａ，ｂはこの発明により製造されたＧａＡｓＦＥ
Ｔのワイヤボンデイング方法を説明するための断面図で
ある。図において、１は半絶縁性基板、２はＮ形層、３
はソース電極、４はドレイン電極、５１はゲート形成領
域、５はゲート電極、６はダイボンダ用・・ンダ、７は
バツケージ電極、８はリード線、９は凹部、１０は電導
路用金属膜、１１，１３はレジスト、１２はブレーテツ
ドヒートシンクである。Figures 1a to 1c are cross-sectional views showing each process step to explain the conventional manufacturing method, and Figures 2a to 2c are cross-sectional views showing the wire bonding method for GaAsFET manufactured by the conventional force method. 3A to 3F are cross-sectional views showing each process step for explaining an embodiment of the present invention. Figures 4A and 4b show GaAsFE manufactured according to the present invention.
FIG. 3 is a cross-sectional view for explaining the wire bonding method of T. In the figure, 1 is a semi-insulating substrate, 2 is an N-type layer, and 3 is a semi-insulating substrate.
1 is a source electrode, 4 is a drain electrode, 51 is a gate formation region, 5 is a gate electrode, 6 is a die bonder, 7 is a baggage electrode, 8 is a lead wire, 9 is a recessed portion, 10 is a metal film for a conductive path, 11 and 13 are resists, and 12 is a braided heat sink.
Claims (1)
半導体層とからなる半導体ウェハの表面から上記基板に
達する深さの凹部を形成する工程、上記凹部と上記半導
体層上に延在した主電極を形成する工程、上記主電極に
ゲート形成領域を介し対向するように上記半導体層上に
他の主電極を形成する工程、上記ゲート形成領域と上記
各主電極と接触する部分を除いた残余の上記半導体層を
エッチング除去する工程、上記ゲート形成領域にゲート
電極を形成する工程、上記半導体ウェハの裏面から上記
半基板を上記凹部の底に到達するまでエッチング除去す
る工程、上記エッチング除去された基板の残部裏面に蒸
着あるいはメッキにより薄い金属膜を形成する工程、上
記薄い金属膜上に厚メッキを形成する工程、及び上記各
主電極を厚メッキする工程を備えた電界効果トランジス
タの製造方法。1. Forming a recess with a depth reaching the substrate from the surface of a semiconductor wafer consisting of a semi-insulating substrate and a semiconductor layer of a predetermined conductivity type formed on the surface, a step of forming a recess extending over the recess and the semiconductor layer. a step of forming a main electrode, a step of forming another main electrode on the semiconductor layer so as to face the main electrode with a gate formation region in between, and a step of forming another main electrode on the semiconductor layer, excluding the portions in contact with the gate formation region and each of the main electrodes. a step of etching away the remaining semiconductor layer; a step of forming a gate electrode in the gate formation region; a step of etching away the half-substrate from the back surface of the semiconductor wafer until it reaches the bottom of the recess; A method for manufacturing a field effect transistor comprising the steps of forming a thin metal film on the remaining back surface of the substrate by vapor deposition or plating, forming thick plating on the thin metal film, and thickly plating each of the main electrodes. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13915479A JPS5914906B2 (en) | 1979-10-25 | 1979-10-25 | Method for manufacturing field effect transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13915479A JPS5914906B2 (en) | 1979-10-25 | 1979-10-25 | Method for manufacturing field effect transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5661170A JPS5661170A (en) | 1981-05-26 |
| JPS5914906B2 true JPS5914906B2 (en) | 1984-04-06 |
Family
ID=15238818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13915479A Expired JPS5914906B2 (en) | 1979-10-25 | 1979-10-25 | Method for manufacturing field effect transistors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5914906B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0520561B2 (en) * | 1985-06-28 | 1993-03-19 | Cummins Engine Co Inc |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5892277A (en) * | 1981-11-28 | 1983-06-01 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
| JPS59117171A (en) * | 1982-12-23 | 1984-07-06 | Nec Corp | High-frequency high-output field-effect transistor |
| JPS59124750A (en) * | 1982-12-29 | 1984-07-18 | Fujitsu Ltd | Semiconductor device |
| JPS6159753A (en) * | 1984-08-30 | 1986-03-27 | Mitsubishi Electric Corp | Via hole type semiconductor device |
| JPS62222656A (en) * | 1986-03-25 | 1987-09-30 | Nec Corp | Semiconductor device |
| JPS62252174A (en) * | 1986-04-24 | 1987-11-02 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
| JPH0821598B2 (en) * | 1989-09-12 | 1996-03-04 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
-
1979
- 1979-10-25 JP JP13915479A patent/JPS5914906B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0520561B2 (en) * | 1985-06-28 | 1993-03-19 | Cummins Engine Co Inc |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5661170A (en) | 1981-05-26 |
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