JPH0491441A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To uniformly open a hole for connecting a source electrode to the other main surface of a semiconductor substrate in a short time by etching by forming a metal electrode connected to the electrode on one main surface of the substrate, and opening a hole for exposing the lower surface of the electrode from the other main surface, etc. CONSTITUTION:A step of forming a gate electrode 5 and a source electrode 3, a drain electrode 4 in ohmic contact on one main surfaces of semiconductor substrates 1, 2 made of compound semiconductor, a step of forming a metal electrode 6 connected to the electrode 3 on one main surfaces of the substrates 1, 2, a step of removing the substrates 1, 2 from the other main surfaces of the substrates 1, 2 by etching to open a hole 7 for exposing the lower surface of the electrode 6, and a step of providing metal 8 in the hole 7 to connect the electrode 3 to the other main surfaces of the substrates 1, 2 are provided. For example, after metal 8 is filled in a viahole 7 opened by reactive ion etching by depositing or plating, it is die bonded to a heat sink 9 to complete an FET.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a power field effect transistor (hereinafter also referred to as FET) using a compound semiconductor such as GaAs.
Relating to a manufacturing method.

[Prior Art] In power FETs, especially those using materials such as GaAs, which have relatively poor thermal conductivity, the source electrode is made of a metal whose via hole is filled in order to dissipate heat and reduce parasitic conductance at high frequencies. Grounding is done through the wire.

FIG. 3 shows a conventional FET having such a via hole structure. An epitaxial layer 2 serving as a channel layer is formed on a semi-insulating GaAS substrate 1 to constitute an epitaxial semiconductor substrate 1.2. On the surface of the epitaxial layer 2, a source electrode 3, a drain electrode 4, which make ohmic contact, and a gate electrode 5, which make Schottky contact, are formed. A via hole 7 is formed from the back surface of the epitaxial semiconductor substrate 1.2 below the source electrode 3 by etching, and the via hole 7 is filled with a metal 8 by vapor deposition or plating. Also, Ga
A human sink 9 is fixed to the back surface of the As substrate 1, and the source electrode 3 is connected to the heat sink 9 via a metal 8 filled in a via hole 7.

[Problems to be solved by the invention] In FETs using compound semiconductors such as GaAs, in order to achieve higher output and higher frequencies, the substrate has been made thinner to lower thermal resistance, and the element shape has also been made smaller. It is being For this reason, the diameter of the via hole needs to be small, and especially in the case of a comb-shaped electrode structure, the width of the source electrode becomes narrow, so the diameter of the via hole needs to be small enough to accommodate this.

By the way, the substrate portion under the source electrode that is in ohmic contact is alloyed, and this alloyed portion has a property that it is difficult to be etched. Furthermore, this alloying varies locally, and as described above, as the substrate becomes thinner, the proportion of the alloyed portion in the overall thickness increases.

However, in conventional FETs, via holes are formed by etching from the back surface of the semiconductor substrate below the source electrode in ohmic contact, which tends to cause variations in the etching completion time across the wafer. As a result, in areas where etching is completed quickly, the etching becomes excessive and the ohmic contact area of the source electrode deteriorates, and in areas where etching is insufficient, the lower surface of the source electrode is not etched sufficiently, resulting in lower yield and performance. There was a problem that it caused deterioration.

Therefore, the present invention aims to manufacture a field effect transistor in which a hole for connecting a source electrode to the other main surface of a semiconductor substrate can be formed uniformly in a short time by etching, thereby improving the yield. The purpose is to provide a method.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides the following steps: (a) forming a gate electrode and a source electrode and a drain electrode in ohmic contact on one main surface of a semiconductor substrate made of a compound semiconductor; (b) forming a metal electrode connected to the source electrode on one main surface of the semiconductor substrate; (c) etching away the semiconductor substrate from the other main surface of the semiconductor substrate to form the metal electrode; the step of drilling a hole through which the lower surface of the
(2) The method further comprises the step of connecting the source electrode to the other main surface of the semiconductor substrate by providing metal in the nine holes.

[Operation] By forming a hole for connecting the source electrode to the other main surface of the semiconductor substrate below the metal electrode that is not alloyed with the semiconductor substrate, etching can be uniformly performed in a short time.

[Example] Hereinafter, an example of the present invention will be described based on FIGS. 1 and 2.

In FIGS. 1 and 2, parts that are the same as or equivalent to those in FIG. 3 are designated by the same reference numerals.

As shown in FIG. 1, a semi-insulating GaAs substrate 1 having a resistivity of 107 Ω·Cm or more and a thickness of about 0.45 mm.
is prepared, and on the GaAs substrate 1, an epitaxial layer 2 having a carrier concentration of about 3.times.10'' cm@-3 is formed as a channel layer to a thickness of about 150 OA to form an epitaxial semiconductor substrate 1.2.

A source electrode 3 and a drain electrode 4 are formed using ohmic metal on the epitaxial layer 2, and heat treatment is performed to obtain ohmic contact. The heat treatment is performed, for example, at 400° C. for 3 minutes using an infrared heat treatment furnace. Next, a gate electrode 5 and a metal electrode 6 for forming a via hole are formed. Metal electrode 6 is formed so that a portion thereof is connected to source electrode 3 . Each of the above electrodes is formed by well-known vapor deposition and patterning techniques.

The upper surface side of the epitaxial semiconductor substrate 1.2 on which each electrode has been formed is mounted or attached to a fixture, and the back surface of the substrate is shaved using a well-known technique to give a total thickness of about 30 μm. A resist mask having an opening only in the area where the Pi7 hole is formed is formed on the back surface of the substrate, and the epitaxial semiconductor substrate 1.2 is etched away by reactive ion etching using 5iC14, C14, and 02 gas, and metal electrodes are removed. 6
A via hole (hole) 7 is bored through which the bottom surface of the hole is exposed.

When the via hole 7 is formed below the metal electrode 6 that is not alloyed with the semiconductor substrate, the etching rate of the area other than the alloyed area for ohmic contact is approximately 5 times that of the alloyed area. Therefore, the etching time becomes shorter and uniform etching becomes possible. The pipe hole 7 is filled with metal 8 by vapor deposition or plating. Gold is suitable as the filling metal 8. Further, in order to facilitate die bonding to the heat sink 9, a thin metal layer may be formed using the same metal as the metal 8 over the entire back surface of the substrate. Thereafter, it is separated into individual chips and die-bonded to a heat sink 9 to complete the FET (FIG. 2). In this state, the source electrode 3 is connected to the heat sink 9 via the metal electrode 6 and the metal 8.

As described above, according to the manufacturing method of this embodiment, by forming the via hole 7 below the metal electrode 6 that is not alloyed with the semiconductor substrate, the etching can be uniformly performed in a short time. . The yield in forming via holes was about 80% in the conventional example described above, but can be improved to about 95% in this embodiment. By forming the metal electrode 6 for forming the via hole 7 at the same time as the gate electrode 5, the manufacturing time does not become particularly long. Furthermore, connecting the source electrode 3 to the heat sink 9 via the metal electrodes 6 and 8 does not particularly affect performance.

[Effects of the Invention] As explained above, according to the present invention, a hole for connecting the source electrode to the other main surface of the semiconductor substrate is formed below the metal electrode that is not alloyed with the semiconductor substrate. As a result, the etching can be performed uniformly in a short time, and the manufacturing yield can be improved.

[Brief explanation of drawings]

FIGS. 1 and 2 are for explaining an embodiment of the method for manufacturing a field effect transistor according to the present invention. FIG. 1 is a vertical cross-sectional view showing the state in the middle of the manufacturing process, and FIG. 2 is a completed FIG. 3 is a vertical cross-sectional view showing a conventional field effect transistor. 1: Semi-insulating GaAs substrate, 2: Epitaxial layer that constitutes an epitaxial semiconductor substrate together with the semi-insulating GaAs substrate, 3: Source electrode, 4 Ni-drain electrode, 5: Gate electrode, 6: Metal electrode, 7: Via hole (hole). ), 8: Metal, 9: Heat sink. Agent Patent Attorney Hidekazu Miyoshi

Claims (1)

[Scope of Claims] (a) A step of forming a gate electrode and a source electrode and a drain electrode in ohmic contact on one main surface of a semiconductor substrate made of a compound semiconductor; (b) Forming a gate electrode on one main surface of a semiconductor substrate; (c) forming a hole through which the lower surface of the metal electrode is exposed by etching away the semiconductor substrate from the other main surface of the semiconductor substrate; (d) forming a metal electrode connected to the source electrode; ) A method for manufacturing a field effect transistor, comprising the step of connecting the source electrode to the other main surface of the semiconductor substrate by providing metal in the hole.