JPS6159753A - Via hole type semiconductor device - Google Patents

Via hole type semiconductor device

Info

Publication number
JPS6159753A
JPS6159753A JP59183001A JP18300184A JPS6159753A JP S6159753 A JPS6159753 A JP S6159753A JP 59183001 A JP59183001 A JP 59183001A JP 18300184 A JP18300184 A JP 18300184A JP S6159753 A JPS6159753 A JP S6159753A
Authority
JP
Japan
Prior art keywords
hole
electrode
layer
semiconductor device
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59183001A
Other languages
Japanese (ja)
Inventor
Tomoko Takebe
武部　朋子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59183001A priority Critical patent/JPS6159753A/en
Publication of JPS6159753A publication Critical patent/JPS6159753A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Abstract

PURPOSE:To improve working efficiency of manufacturing process by embedding GaAs conductive layer and causing it to grow in the area corresponding to a contact hole at the rear side of via hole type semiconductor device and using GaAs substrate of which rear side is flattened. CONSTITUTION:A hole corresponding to a contact hole 5 is bored to a semi- insulated GaAs substrate 1 and GaAs conductive layer 12 is embedded to such hole in order to cause it to grow. Next, the surface of layer 12 is flattened. After grinding it from the side of substrate 1, an active region 11, a source electrode 2, a drain electrode 3 and a gate electrode 4 are provided. Thereafter, a source grounding contact hole 13 is formed in such a manner as reaching the layer 12 at the location of electrode 2 and moreover the electrode 2 and the layer 12 are connected by providing the source grounding contact metal 14 within the hole 13. The surface of layer 12 is covered with an ohmic metal 9 as the soldering material.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、例えば半絶縁性ＧａＡＳ基板上にエビタキ
ンヤル成長あるいはイオン注入等の方法により活性領域
を形成したＧａＡＳ結晶でＧａＡｓＦＥＴ、またはＧａ
ＡｓＩＣをつくる際に、基板を貫通する穴をあけて電極
を形成することによりソース電極を裏面に成長させた結
晶４電層と接続するよプにしたパイ７ホール型半導体装
置に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a GaAs FET or a GaAs crystal in which an active region is formed on a semi-insulating GaAS substrate by a method such as epitaxial growth or ion implantation.
This invention relates to a pi-7-hole type semiconductor device in which a source electrode is connected to a crystalline 4-conductor layer grown on the back surface by forming an electrode through a hole penetrating the substrate when making an AsIC.

〔従来、技術〕[Conventional technology]

イオン注入を用いたパイ１ホール型０２人ｓＦＥでの従
来例を第１図および第２図に示す。A conventional example of a pie-1-hole type 02 sFE using ion implantation is shown in FIGS. 1 and 2.

３１図（ａ）　〜（ｅ）は従来のパイ７ホール型ＧａＡ
ｓＦＥＴの製造工ａを示す断面図である。Figures 31 (a) to (e) are conventional pi-7 hole type GaA
It is a sectional view showing manufacturing process a of sFET.

第１図におい【、１は半絶縁性ＧａＡｓ基板、２はソー
ス電極、３はドレイン電極、４はゲート電極、５は裏面
コンタクトホール、６は裏面コンタクト金属、１１は活
性領域、１３はソース接地用コンタクトホール、１４は
ソース接地用コンタクト金属である。In FIG. 1, 1 is a semi-insulating GaAs substrate, 2 is a source electrode, 3 is a drain electrode, 4 is a gate electrode, 5 is a back contact hole, 6 is a back contact metal, 11 is an active region, and 13 is a source ground. The contact hole 14 is a contact metal for source grounding.

従来のパイ７ホール型ＧａＡｓＦＥＴは第１図＜ａ）に
示すように、半絶縁性ＧａＡｓ基板１の一生面上に、例
えばイオン注入層のような活性領域１１を形成した後、
この活性領域１１に対してａ１図ｔｂ＋に示すようにソ
ース電極２．ドレイン電極３およびゲート電極４′９ｅ
設け、さらに、ソース電極２の位置には第１図（ｃ）　
Ｋ示すように、ソース接地用コンタクトホール１３を形
成し、この穴にたとえばスパッタリング、メッキ等の方
法でソース接地用フンタクト金Ｊｉｉ１４を付着させる
ことにより、ソース電極２とソース接地用コンタクト金
属１４とを接続させる。As shown in FIG. 1<a), a conventional pi-7-hole type GaAsFET is manufactured by forming an active region 11, such as an ion implantation layer, on the entire surface of a semi-insulating GaAs substrate 1;
For this active region 11, as shown in a1 and tb+, a source electrode 2. Drain electrode 3 and gate electrode 4'9e
1(c) at the position of the source electrode 2.
As shown in K, the source electrode 2 and the source grounding contact metal 14 are connected by forming a contact hole 13 for source grounding and attaching pure gold JII 14 for source grounding to this hole by sputtering, plating, etc. Connect.

その後、半絶縁性ＱａＡｇ基板１１に所定の厚さまで研
ＩＦした後、第１図（ｄ）に示すように半絶縁性ＧａＡ
ｓ基板１の裏面から裏面コンタクトホール５を形成し、
先く形成したソース接地用フンタクトホール１３まで到
達させた後、裏面コンタクトホール５に、たとえばスパ
ッタリング、メッキ等の方法で裏面コンタクト金属６を
付着させることくている。Thereafter, after polishing the semi-insulating QaAg substrate 11 to a predetermined thickness, the semi-insulating GaA
forming a backside contact hole 5 from the backside of the s-substrate 1;
After reaching the previously formed source ground contact hole 13, a back contact metal 6 is attached to the back contact hole 5 by, for example, sputtering or plating.

第２図は従来のパイ７ホール型半導体チップを接地面に
接地させた状態を示す断面図である一従来のパイ７ホー
ル型半導体装置は、半導体チップの裏面コンタクト金ｋ
Ｉ４＆の凹部にハンダ材７を流し込み、ハンダ材７の融
点まで温度を上げることによりハンダ材７Ｙ溶融させて
、半導体チップと接地面８とを接着させている。FIG. 2 is a cross-sectional view showing a state in which a conventional pi-7 hole type semiconductor chip is grounded to the ground plane.A conventional pi-7 hole type semiconductor device has a contact gold plate on the back surface of the semiconductor chip.
The solder material 7 is poured into the concave portion of I4&, and the temperature is raised to the melting point of the solder material 7, thereby melting the solder material 7Y and bonding the semiconductor chip and the ground plane 8 together.

しかしながら、従来のパイ７ホール型半導体装置は製造
工程の途中で第１図（ｄ）　Ｋ示したよ５に基板厚みが
数ｌＯμｍとなるため〈非常圧割れやすく作業性が悪い
という欠点を有Ｌ−（いた。さらに、ソース電極２を接
地面８に接地する際に、従来のパイ７ホール型半導体チ
ップは裏面フンタクト金属６が平坦でなく凹形状く形成
されているため、裏面コンタクト金ｍａと接地面８とが
隙間なく完全に接着されにくいことや、ハンダ材７の融
点まで温度を上げた時に、半絶縁性ＧａＡｓ基板１と裏
面フンタクト金属６との熱膨張率が異なるためにＧａＡ
ｌ結晶に歪みが生じたり、割れたりし易いという欠点が
あり、素子の信頼性を低下させていた。However, in the conventional pie-7 hole type semiconductor device, the substrate thickness becomes several 10 μm as shown in FIG. 1(d) during the manufacturing process. (Furthermore, when the source electrode 2 is grounded to the ground plane 8, the back surface contact metal 6 of the conventional pie7 hole type semiconductor chip is not flat but is formed in a concave shape. GaAs is difficult to adhere to the ground 8 completely without gaps, and when the temperature is raised to the melting point of the solder material 7, the thermal expansion coefficients of the semi-insulating GaAs substrate 1 and the bare metal 6 on the back surface are different.
The drawback is that the crystal is easily distorted and cracked, reducing the reliability of the device.

〔発明の概要〕[Summary of the invention]

この発明は、上記のような従来のパイ７ホール型牛導体
装置の欠点を除去するためになされたもので、従来のパ
イ７ホール型半導体装置の裏面コンタクトホールに相当
する部分に、たとえばＬＰＥ法によるＧａａｓ　４電層
を埋込み成長させるとともに、裏面を平坦面としたＧａ
　Ａ　ｓ基板を用いることにより、製造工程での作業性
を向上させ、かつ接地面との接着のｖＡＫ生じていた信
頼性の低下を除去したパイ７ホール截半導体装置を提供
するものである。以下、この発明を図面に基づいて説明
するＯ 〔発明の実施例〕 第３図（ａ）〜（ｅ）は、この発明の一実施例によるパ
イ７ホール屋半導体装置の一実施例の製造工程の要点を
示す断面図である・ まず、第３図（ａ）に示すように、半絶縁性ＧａＡｓ基
板１に従来のパイ７ホール型半導体装置の裏面コンタク
トホール５に相当する穴をあけ、この穴の部分に、たと
えばＬＰＢ法でＧａＡｓ導電層１２を埋込み成長させる
。次に第３図（ｂ）　Ｋ、示すように成長させたＧａＡ
ｓ　１ｊＨＩ！ｆｆｉ　１２の表面をラッピングにより
平坦にする。その後、半絶縁性ＱａＡｓ基板１の側から
所定の厚さまで研磨した後、第３図（Ｃ）に示すよ５に
、従来と同様に、例えばイオン注入層のような方法で活
性領域１１を形成し、さらに、この活性領域１１に対し
て第３図（ｄ）　Ｋ示すようにソース電極２．ドレイン
電極３およびゲート電極４を設ける。その後、第３図（
ｅ）　Ｋ示すように、ソース電極２の位置にソース接地
用フンタクトホール１３を、先に成長させたＧａＡＳ４
１ｉＣ層１２に到達す層上２に形成し、さらに、このソ
ース接地用コンタクトホール１３中に、たとえば、スパ
ッタリング、メッキ等の方法でソース接地用フンタクト
金属１４を付着させることにより、ソースミ電極２とＧ
ａＡｓ導電層１２とを接続させる。This invention was made in order to eliminate the drawbacks of the conventional pi-7-hole type conductor device as described above, and it is possible to apply a method using, for example, an LPE method to the portion corresponding to the back contact hole of the conventional pi-7-hole type semiconductor device. In addition to growing a GaAs 4-conductor layer with a flat surface on the back side,
By using an As substrate, it is possible to improve workability in the manufacturing process and to provide a semiconductor device with 7-hole holes, which eliminates a decrease in reliability caused by vAK of adhesion to a ground plane. Embodiments of the Invention FIGS. 3(a) to 3(e) show manufacturing steps of an embodiment of a pie7hole semiconductor device according to an embodiment of the invention. 3(a), first, as shown in FIG. A GaAs conductive layer 12 is buried and grown in the hole by, for example, the LPB method. Next, in Fig. 3(b) K, GaA grown as shown
s 1jHI! The surface of ffi 12 is made flat by lapping. Thereafter, after polishing the semi-insulating QaAs substrate 1 to a predetermined thickness, as shown in FIG. Furthermore, a source electrode 2. is attached to this active region 11 as shown in FIG. 3(d). A drain electrode 3 and a gate electrode 4 are provided. After that, see Figure 3 (
e) As shown in K, a hole 13 for source grounding is provided at the position of the source electrode 2 on the previously grown GaAS4
The source grounding contact hole 13 is formed on the layer 2 reaching the 1iC layer 12, and a source grounding contact hole 14 is deposited in the source grounding contact hole 13 by, for example, sputtering, plating, or the like. G
The aAs conductive layer 12 is connected.

ＧａＡｓ導電層１２の表面はハンダ材としてのオーミン
ク金ｔ４９で被覆する。The surface of the GaAs conductive layer 12 is coated with Ohmink gold T49 as a solder material.

第４図は以上のようにして得られたパイ７ホール型半導
体チップを接地面に接地した状態を示す断面図である。FIG. 4 is a sectional view showing a state in which the pie-7 hole type semiconductor chip obtained as described above is grounded to a ground plane.

従来の方法と同様にハンダ材７を介して半導体チップと
接地面８とを接着させることにより、パイ７ホール型半
導体装置が完成する。By bonding the semiconductor chip and the ground plane 8 via the solder material 7 in the same manner as in the conventional method, a pie-7 hole type semiconductor device is completed.

なお、上記実施例ではＧａＡｓ　４電ノー１２の結晶成
長方法としてＬＰＥ法を用いたが、この他に、ＭＯ−Ｃ
ＶＤ法、ＭＢ法あるいは、これらの成長の方法を組合わ
せても同様の効果を奏することは勿論である。In the above example, the LPE method was used as the crystal growth method for GaAs 4-electrode No. 12, but in addition to this, MO-C
Of course, similar effects can be achieved by using the VD method, the MB method, or a combination of these growth methods.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、この発明は、半導体結晶基
板上に活性領域を設げてトランジスタを形成した半導体
装置において、前記トランジスタの電極を前記半導体結
晶基板を貫通させてその裏面に成長させた同種の結晶導
電層に接続し、さらにこの結晶導電層の裏面を接地のた
めの平坦面とＬ４．：ので、接地する際に半導体チップ
と接地面とをハンダ材を介して完全に接着させることが
できる。また、従来のよ５に、半導体チップと接地面と
な接Ｍさせるためにハンダ材の融点まで温度を上げても
、結晶導電層と接地面となるコンタクト金属との熱膨張
率の差に起因する半導体結晶基板の歪みや割れが生ずる
ことがなく、素子の信頼性を極めて向上させることがで
きる。さらに、結晶導電層の成長は製造工程の最初の段
階で行うため、従来のように製造工程の途中で厚みがａ
ｌＯμｍという非常に薄いクエへを取り扱う必要がない
ので、作業性が著るしく向上するという利点がある。As explained in detail above, the present invention provides a semiconductor device in which a transistor is formed by providing an active region on a semiconductor crystal substrate, in which an electrode of the transistor is grown on the back surface of the semiconductor crystal substrate by penetrating the semiconductor crystal substrate. L4. is connected to the same type of crystal conductive layer, and the back surface of this crystal conductive layer is connected to a flat surface for grounding. : Therefore, when grounding, the semiconductor chip and the ground plane can be completely bonded via the solder material. In addition, even if the temperature is raised to the melting point of the solder material in order to bring the semiconductor chip into contact with the ground plane, as in the case of the conventional method, the difference in coefficient of thermal expansion between the crystal conductive layer and the contact metal that forms the ground plane causes Therefore, the semiconductor crystal substrate does not become distorted or cracked, and the reliability of the device can be greatly improved. Furthermore, since the crystal conductive layer is grown at the first stage of the manufacturing process, the thickness of the crystal conductive layer is
Since there is no need to handle extremely thin cubes of 10 μm, there is an advantage that workability is significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図＜ａ）〜（ｅ）は従来のパイ７ホール型ＧａＡｓ
ＦＥＴの製造工程を示す断面図、第２図は従来のパイ７
ホール型半導体チップを接地面に接地させた状態を示す
断面図、第３図（ａ）〜＜ｅ）はこの発明によるパイ７
ホール型半導体装置の一実施例の製造工程の要点を示す
断面図、第４図はこの発明によるパイ７ホール温半導体
チップを接地面に接地した状Ｍを示す断面図である。 図中、１は半絶縁性（）ＪＩＡＳ基板、２はソース電極
、３はドレイン電極、４はゲート電極、５は裏面コンタ
クトホール、７はハンダ材、８は接地面、９はオーミン
ク金属、１１は活性領域、１２はＧａＡｓ導電層、１３
はソース接地用コンタクトホール、１４はソース接地用
コンタクト金属である・なお、図中の同一符号は同一ま
たは相当部分を示す。 代理人　大岩増雄　　（外２名） 第１図 第２図 第　３　図 １．事件の表示　　　待願昭５９−１８３００１号２４
発明の名称　　　パイ１本−ル型半導体装置３、補正を
する者 ５、、？ＩＯ正の対象 明細書の特許請求の範囲の欄および発明の詳細な説明の
欄 ６６補正の内容 （１）明細書の特許請求の範囲を別紙のように祁正する
。 （２）　　同しく第１頁１９行、第７頁１０行、１５行
、１８〜１９行の「結晶導電層」を、いずれも「同種結
晶の導電層」と補正する。 （３）　　同じく第７頁１行のｒＭＢ法」を、ｒＭＢＥ
法」と補正する。 （４）　　同じく第７頁９行の「同種の結晶導電層」を
、「同種結晶の導ｇａ層」と補正する。 （５）　　同じく第８頁２行の「著るしく」を、「著し
く」と補正する。 以上 ２、特許請求の範囲 １　　　半導体結晶基板表面に活性領域を設けてトラン
ジスタを形成した半導体装置において、前記トランジス
タの電極を、前記半導体結晶基板を貫通さ１　　せて前
記半導体結晶基板表面に成長させた同亙絨品旦導電層に
接続し、さらに前記且星結晶且導電１の裏面を接地のた
めの平坦面としたことを特徴とするバイ１ネール型半導
体装置。Figure 1 <a) to (e) are conventional pi-7-hole type GaAs.
A cross-sectional view showing the FET manufacturing process, Figure 2 is a conventional PI7
3(a) to 3(e) are cross-sectional views showing the state in which the Hall-type semiconductor chip is grounded to the ground plane.
FIG. 4 is a cross-sectional view showing the main points of the manufacturing process of an embodiment of the Hall-type semiconductor device. FIG. 4 is a cross-sectional view showing a shape M in which a pie7-hole hot semiconductor chip according to the present invention is grounded to a ground plane. In the figure, 1 is a semi-insulating () JIAS substrate, 2 is a source electrode, 3 is a drain electrode, 4 is a gate electrode, 5 is a back contact hole, 7 is a solder material, 8 is a ground plane, 9 is an ohmink metal, 11 12 is an active region, 12 is a GaAs conductive layer, and 13 is an active region.
14 is a contact hole for source grounding, and 14 is a contact metal for source grounding. Note that the same reference numerals in the drawings indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3 Figure 1. Display of incident Machigan Sho 59-183001 No. 24
Title of the invention: 1 pie-ru type semiconductor device 3, corrector 5,...? Contents of amendments to the Claims column and Detailed Description of the Invention column 66 of the IO-correct subject specification (1) The claims of the specification will be corrected as shown in the attached sheet. (2) Similarly, "crystal conductive layer" on page 1, line 19, page 7, line 10, line 15, and lines 18 to 19 are corrected to "conductive layer of the same type of crystal." (3) Similarly, rMBE method” on page 7, line 1
amended to ``Act''. (4) Similarly, "the same kind of crystal conductive layer" on page 7, line 9 is corrected to "the same kind of crystal ga-conducting layer." (5) Similarly, "remarkably" in line 2 of page 8 is amended to "remarkably." Above 2, Claim 1 In a semiconductor device in which a transistor is formed by providing an active region on the surface of a semiconductor crystal substrate, an electrode of the transistor is grown on the surface of the semiconductor crystal substrate by penetrating the semiconductor crystal substrate. 1. A bi-1 conductor type semiconductor device, characterized in that the star crystal conductor 1 is connected to a conductive layer, and further has a back surface of the star crystal conductor 1 as a flat surface for grounding.

Claims (1)

【特許請求の範囲】[Claims] 　半導体結晶基板表面に活性領域を設けてトランジスタ
を形成した半導体装置において、前記トランジスタの電
極を、前記半導体結晶基板を貫通させて前記半導体結晶
基板表面に成長させた同種の結晶導電層に接続し、さら
に前記結晶導電層の裏面を接地のための平坦面としたこ
とを特徴とするバイアホール型半導体装置。In a semiconductor device in which a transistor is formed by providing an active region on the surface of a semiconductor crystal substrate, an electrode of the transistor is connected to a crystal conductive layer of the same type grown on the surface of the semiconductor crystal substrate by penetrating the semiconductor crystal substrate, Furthermore, a via hole type semiconductor device characterized in that the back surface of the crystalline conductive layer is a flat surface for grounding.
JP59183001A 1984-08-30 1984-08-30 Via hole type semiconductor device Pending JPS6159753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59183001A JPS6159753A (en) 1984-08-30 1984-08-30 Via hole type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59183001A JPS6159753A (en) 1984-08-30 1984-08-30 Via hole type semiconductor device

Publications (1)

Publication Number Publication Date
JPS6159753A true JPS6159753A (en) 1986-03-27

Family

ID=16128017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59183001A Pending JPS6159753A (en) 1984-08-30 1984-08-30 Via hole type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6159753A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5661170A (en) * 1979-10-25 1981-05-26 Mitsubishi Electric Corp Preparation of field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5661170A (en) * 1979-10-25 1981-05-26 Mitsubishi Electric Corp Preparation of field effect transistor

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