JPH07142518A - Lead frame, semiconductor chip, and semiconductor device - Google Patents
Lead frame, semiconductor chip, and semiconductor deviceInfo
- Publication number
- JPH07142518A JPH07142518A JP28855093A JP28855093A JPH07142518A JP H07142518 A JPH07142518 A JP H07142518A JP 28855093 A JP28855093 A JP 28855093A JP 28855093 A JP28855093 A JP 28855093A JP H07142518 A JPH07142518 A JP H07142518A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead frame
- island
- chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、リードフレームならび
に半導体チップおよびそれを用いた半導体装置に関し、
特に、共晶を利用して接合を行う半導体チップのクラッ
クを防止する技術に適用して有効な技術に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame, a semiconductor chip and a semiconductor device using the same.
In particular, the present invention relates to a technique effectively applied to a technique for preventing cracks in a semiconductor chip that is joined by utilizing a eutectic.
【0002】[0002]
【従来の技術】プラスチック封止形パッケージに搭載さ
れる半導体チップとリードフレームのチップ搭載部との
接着は、オーミックコンタクトの必要性などからAu−
Si(金−シリコン)共晶によるダイボンディングが行
われている。2. Description of the Related Art Adhesion between a semiconductor chip mounted in a plastic encapsulation type package and a chip mounting portion of a lead frame is due to the necessity of ohmic contact and the like.
Die bonding by Si (gold-silicon) eutectic is performed.
【0003】これは、予め金めっきなどが施されたリー
ドフレームのチップ搭載部に半導体チップを搭載し、共
晶温度である370℃以上の高温により加熱を行い、シ
リコンからなる半導体チップとの共晶を利用して接合を
行うものである。This is because a semiconductor chip is mounted on a chip mounting portion of a lead frame which has been plated with gold in advance, and is heated at a high temperature of 370 ° C. or higher, which is a eutectic temperature, so that the semiconductor chip is made of silicon. Bonding is performed using crystals.
【0004】[0004]
【発明が解決しようとする課題】ところが、この従来技
術による半導体チップの固定方法であると、銅合金から
なるリードフレームのチップ搭載部とシリコン基板から
なる半導体チップとの膨張率が異なるために、接着後の
冷却過程において生じる熱応力が半導体チップに加わ
り、それにより、半導体チップにクラックが発生してし
まう。However, in this method of fixing a semiconductor chip according to the prior art, since the chip mounting portion of the lead frame made of a copper alloy and the semiconductor chip made of a silicon substrate have different expansion coefficients, Thermal stress generated in the cooling process after bonding is applied to the semiconductor chip, which causes cracks in the semiconductor chip.
【0005】また、この半導体チップのクラックは、半
導体チップサイズが大きいほど顕著に現れてしまう。Further, the cracks of the semiconductor chip become more remarkable as the size of the semiconductor chip increases.
【0006】本発明者が検討したところによれば、図7
に示すように、半導体チップがリードフレームに接着し
ている面積と半導体チップに働く応力の関係とは、接着
面積が増えるに従って応力が大きくなっている。According to a study made by the present inventor, FIG.
As shown in, the relationship between the area where the semiconductor chip is bonded to the lead frame and the stress acting on the semiconductor chip is such that the stress increases as the bonding area increases.
【0007】これによって、半導体装置の特性劣化が生
じてしまい、製品の信頼性が著しく低下してしまうこと
になる。As a result, the characteristics of the semiconductor device are deteriorated, and the reliability of the product is significantly reduced.
【0008】本発明の目的は、半導体チップの熱応力に
よるクラックを確実に防止するリードフレームならびに
半導体チップおよびそれを用いた半導体装置を提供する
ことにある。An object of the present invention is to provide a lead frame, a semiconductor chip, and a semiconductor device using the same which reliably prevent cracks of the semiconductor chip due to thermal stress.
【0009】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【0010】[0010]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.
【0011】すなわち、請求項1記載の発明は、半導体
チップを搭載するためのリードフレームのチップ搭載部
の形状が凹凸形状よりなり、突起形状部分だけを接着さ
せることにより、半導体チップとリードフレームのチッ
プ搭載部との接着面積を小さくさせるものである。That is, according to the first aspect of the invention, the shape of the chip mounting portion of the lead frame for mounting the semiconductor chip is an uneven shape, and only the protrusion-shaped portion is adhered, so that the semiconductor chip and the lead frame are bonded together. The adhesive area with the chip mounting portion is reduced.
【0012】また、請求項2記載の発明は、半導体チッ
プを搭載するためのリードフレームのチップ搭載部の所
定箇所に所定の材料により金めっきが施され、金めっき
部分だけを接着させることにより、半導体チップとリー
ドフレームのチップ搭載部との接着面積を小さくさせる
ものである。According to a second aspect of the present invention, gold is plated with a predetermined material on a predetermined portion of a chip mounting portion of a lead frame for mounting a semiconductor chip, and only the gold plated portion is adhered. The adhesive area between the semiconductor chip and the chip mounting portion of the lead frame is reduced.
【0013】さらに、請求項3記載の発明は、半導体チ
ップの裏面の所定箇所に所定の材料により蒸着膜が形成
され、蒸着膜部分だけを接着させることにより、半導体
チップとリードフレームのチップ搭載部との接着面積を
小さくさせるものである。Further, according to a third aspect of the invention, a vapor deposition film is formed of a predetermined material at a predetermined position on the back surface of the semiconductor chip, and only the vapor deposition film portion is adhered to the semiconductor chip and the chip mounting portion of the lead frame. It reduces the adhesion area with.
【0014】また、請求項4記載の発明は、請求項1ま
たは2記載のリードフレームを用いて構成された半導体
装置である。The invention according to claim 4 is a semiconductor device configured by using the lead frame according to claim 1 or 2.
【0015】さらに、請求項5記載の発明は、請求項3
記載の半導体チップを用いて構成された半導体装置であ
る。Further, the invention according to claim 5 is the same as claim 3
It is a semiconductor device configured using the semiconductor chip described.
【0016】[0016]
【作用】上記のような構成のリードフレームならびに半
導体チップおよびそれを用いた半導体装置によれば、半
導体チップの接着面積を少なくすることができる。According to the lead frame, the semiconductor chip, and the semiconductor device using the same having the above-described structure, the bonding area of the semiconductor chip can be reduced.
【0017】それにより、半導体チップ接着後の冷却過
程において、リードフレームと半導体チップとの膨張率
が異なるために半導体チップに加わる熱応力を低減させ
ることができ、半導体チップの冷却過程における半導体
チップのクラックを防止することができる。This makes it possible to reduce the thermal stress applied to the semiconductor chip due to the different expansion rates of the lead frame and the semiconductor chip in the cooling process after bonding the semiconductor chip, and the semiconductor chip in the cooling process of the semiconductor chip can be reduced. It is possible to prevent cracks.
【0018】また、生産効率が良くなり、半導体装置の
特性劣化がなくなり、信頼性も向上する。Further, the production efficiency is improved, the characteristic deterioration of the semiconductor device is eliminated, and the reliability is also improved.
【0019】[0019]
【実施例】以下、本発明の実施例を図面に基づいて詳細
に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【0020】(実施例1)図1は、本発明の実施例1に
よる半導体チップの接着後のリードフレームの要部側面
図である。(Embodiment 1) FIG. 1 is a side view of essential parts of a lead frame after a semiconductor chip is adhered thereto according to Embodiment 1 of the present invention.
【0021】本実施例1において、リードフレーム1の
中央部に位置するチップ搭載部であるアイランド2は、
金などによってめっき3が施されており、所定の箇所に
突起2aが形成されいる。In the first embodiment, the island 2 which is the chip mounting portion located at the center of the lead frame 1 is
The plating 3 is applied with gold or the like, and the projection 2a is formed at a predetermined position.
【0022】また、半導体チップ4は、当該アイランド
2に搭載され、接着される。この半導体チップ4の裏面
には、たとえば、金を蒸着させることにより蒸着膜4a
が形成されている。The semiconductor chip 4 is mounted on and bonded to the island 2. On the back surface of the semiconductor chip 4, for example, by depositing gold, a vapor deposition film 4a is formed.
Are formed.
【0023】さらに、半導体チップ4の接着は、アイラ
ンド2上に搭載された半導体チップ4を共晶温度370
℃以上の高温で加熱し、金−シリコン共晶を利用して接
着を行う。Further, the semiconductor chip 4 is adhered by eutectic temperature 370 of the semiconductor chip 4 mounted on the island 2.
Heating is performed at a high temperature of ℃ or more, and adhesion is performed using a gold-silicon eutectic.
【0024】そして、アイランド2に接着された半導体
チップ4は、冷却工程を経て、次工程に送られる。Then, the semiconductor chip 4 bonded to the island 2 is sent to the next step through a cooling step.
【0025】次に、本実施例の作用について説明する。Next, the operation of this embodiment will be described.
【0026】半導体チップ4は、高温によって加熱され
アイランド2に接着されるが、このアイランド2には突
起2aが設けられているので、半導体チップ4は、当該
突起2aと係合される部分だけが金−シリコン共晶によ
り接着されることとなり、その他の半導体チップ4の部
分は接着されていないことになる。The semiconductor chip 4 is heated to a high temperature and adheres to the island 2. Since the island 2 is provided with the protrusion 2a, the semiconductor chip 4 has only a portion engaged with the protrusion 2a. The gold-silicon eutectic will bond them, and the other semiconductor chip 4 parts will not be bonded.
【0027】そして、接着された半導体チップ4は、冷
却工程で冷却されるが、半導体チップ4の接着面積がア
イランド2の突起2aだけと小さいために、半導体チッ
プ4に加わる熱応力が大幅に低減される。The bonded semiconductor chip 4 is cooled in the cooling process, but since the bonding area of the semiconductor chip 4 is as small as the protrusion 2a of the island 2, the thermal stress applied to the semiconductor chip 4 is greatly reduced. To be done.
【0028】それにより、本実施例1によれば、半導体
チップ4のクラックが確実に防止される。As a result, according to the first embodiment, cracks in the semiconductor chip 4 are reliably prevented.
【0029】また、半導体チップ4のクラックが防止さ
れることにより、半導体装置の生産効率が上がり、信頼
性が向上する。Further, since the cracks of the semiconductor chip 4 are prevented, the production efficiency of the semiconductor device is improved and the reliability is improved.
【0030】さらに、突起2aは、図2に示すように、
たとえば複数の突起2aを設けるなど半導体チップ4の
接着面積が小さければ前記実施例以外の形状でも効果は
同様である。Further, the protrusion 2a is, as shown in FIG.
If the bonding area of the semiconductor chip 4 is small, for example, by providing a plurality of protrusions 2a, the effect is the same even if the shape is other than the above-mentioned embodiment.
【0031】(実施例2)図3は、本発明の実施例2に
よる半導体チップの接着後のリードフレームの要部側面
図である。(Embodiment 2) FIG. 3 is a side view of essential parts of a lead frame after a semiconductor chip is adhered thereto according to Embodiment 2 of the present invention.
【0032】本実施例2においては、アイランド2の所
定の箇所にだけ、金などによってめっき3を施す。In the second embodiment, the plating 3 is applied to a predetermined portion of the island 2 with gold or the like.
【0033】そして、裏面に金などを蒸着させた蒸着膜
4aが形成されている半導体チップ4をアイランド2上
に搭載させ、共晶温度370℃以上の高温で加熱し、金
−シリコン共晶を利用して接着を行う。Then, the semiconductor chip 4 on the back surface of which the vapor deposition film 4a formed by vapor deposition of gold or the like is formed is mounted on the island 2 and heated at a high temperature of eutectic temperature of 370 ° C. or higher to form a gold-silicon eutectic crystal. Use to bond.
【0034】この半導体チップ4は、アイランド2のめ
っき3が施された箇所と係合した部分だけが接着される
ので接着面積が小さくなり、半導体チップ4に加わる熱
応力が大幅に低減される。Since only the portion of the semiconductor chip 4 engaged with the plated portion 3 of the island 2 is bonded, the bonding area is reduced, and the thermal stress applied to the semiconductor chip 4 is greatly reduced.
【0035】それにより、本実施例2においても、半導
体チップ4のクラックが確実に防止される。As a result, also in the second embodiment, cracks in the semiconductor chip 4 can be reliably prevented.
【0036】また、半導体チップ4のクラックが防止さ
れることにより、半導体装置の生産効率が上がり、信頼
性が向上する。Further, since the cracks of the semiconductor chip 4 are prevented, the production efficiency of the semiconductor device is improved and the reliability is improved.
【0037】さらに、めっき3は、図4に示すように、
たとえばアイランド2上の複数の箇所にめっき3を施す
など半導体チップ4の接着面積が小さければ前記実施例
以外の箇所にめっき3を成形しても効果は同様である。Further, the plating 3 is, as shown in FIG.
If the bonding area of the semiconductor chip 4 is small, for example, the plating 3 is applied to a plurality of locations on the island 2, the same effect can be obtained by molding the plating 3 on a location other than the above-described embodiment.
【0038】(実施例3)図5は、本発明の実施例3に
よる半導体チップの接着後のリードフレームの要部側面
図である。(Embodiment 3) FIG. 5 is a side view of a main part of a lead frame after a semiconductor chip is adhered thereto according to Embodiment 3 of the present invention.
【0039】本実施例3においては、たとえば、半導体
チップ4にマスクすることで、所定の箇所だけを金など
によって蒸着を行い、蒸着膜4aの成形を行う。In the third embodiment, for example, by masking the semiconductor chip 4, only predetermined portions are vapor-deposited with gold or the like to form the vapor-deposited film 4a.
【0040】そして、めっき3が施されたアイランド2
上に当該半導体チップ4を搭載させ、共晶温度370℃
以上の高温で加熱し、金−シリコン共晶を利用して接着
を行う。Then, the island 2 having the plating 3 applied thereto
The semiconductor chip 4 is mounted on the eutectic temperature of 370 ° C.
Heating is performed at the above high temperature, and adhesion is performed using a gold-silicon eutectic.
【0041】この半導体チップ4は、所定の箇所に成形
された蒸着膜4aと係合した部分だけがアイランド2と
接着されるので接着面積が小さくなり、半導体チップ4
に加わる熱応力が大幅に低減される。Since only the portion of the semiconductor chip 4 that engages with the vapor deposition film 4a formed at a predetermined position is bonded to the island 2, the bonding area becomes small and the semiconductor chip 4
The thermal stress applied to is greatly reduced.
【0042】それにより、本実施例3においても、半導
体チップ4のクラックが確実に防止される。As a result, also in the third embodiment, cracking of the semiconductor chip 4 is surely prevented.
【0043】また、半導体チップ4のクラックが防止さ
れることにより、半導体装置の生産効率が上がり、信頼
性が向上する。Further, by preventing cracks in the semiconductor chip 4, the production efficiency of the semiconductor device is improved and the reliability is improved.
【0044】さらに、蒸着膜4aは、図6に示すよう
に、たとえば半導体チップの複数の箇所に蒸着を行うな
ど半導体チップ4の接着面積が小さければ前記実施例以
外の箇所に蒸着膜4aを成形しても効果は同様である。Further, as shown in FIG. 6, if the adhesion area of the semiconductor chip 4 is small, for example, as shown in FIG. 6, the vapor deposition film 4a is formed at a portion other than the above-mentioned embodiment. However, the effect is the same.
【0045】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものでなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.
【0046】[0046]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.
【0047】(1)本発明によれば、半導体チップの熱
応力に起因するクラックを確実に防止することができ
る。(1) According to the present invention, it is possible to reliably prevent cracks due to thermal stress of the semiconductor chip.
【0048】(2)また、上記(1)により、本発明に
よれば、半導体装置の生産効率が上がり、半導体装置の
特性劣化がなくなるので半導体装置の信頼性が向上す
る。(2) Further, according to the present invention, due to the above (1), the production efficiency of the semiconductor device is improved and the characteristic deterioration of the semiconductor device is eliminated, so that the reliability of the semiconductor device is improved.
【図1】本発明の実施例1による半導体チップの接着後
のリードフレームの要部側面図である。FIG. 1 is a side view of an essential part of a lead frame after a semiconductor chip is bonded according to a first embodiment of the present invention.
【図2】本発明の他の実施例による半導体チップの接着
後のリードフレームの要部側面図である。FIG. 2 is a side view of a main part of a lead frame after a semiconductor chip is bonded according to another embodiment of the present invention.
【図3】本発明の実施例2による半導体チップの接着後
のリードフレームの要部側面図である。FIG. 3 is a side view of a main portion of a lead frame after a semiconductor chip is bonded according to a second embodiment of the present invention.
【図4】本発明の他の実施例による半導体チップの接着
後のリードフレームの要部側面図である。FIG. 4 is a side view of essential parts of a lead frame after a semiconductor chip is bonded according to another embodiment of the present invention.
【図5】本発明の実施例3による半導体チップの接着後
のリードフレームの要部側面図である。FIG. 5 is a side view of a main portion of a lead frame after a semiconductor chip is bonded according to a third embodiment of the present invention.
【図6】本発明の他の実施例による半導体チップの接着
後のリードフレームの要部側面図である。FIG. 6 is a side view of a main portion of a lead frame after a semiconductor chip is bonded according to another embodiment of the present invention.
【図7】本発明者により検討されたリードフレームと半
導体チップとの接着面積と応力の関係図である。FIG. 7 is a diagram showing a relationship between stress and a bonding area between a lead frame and a semiconductor chip examined by the present inventor.
1 リードフレーム 2 アイランド(チップ搭載部) 2a 突起 3 めっき 4 半導体チップ 4a 蒸着膜 1 lead frame 2 island (chip mounting part) 2a protrusion 3 plating 4 semiconductor chip 4a evaporated film
Claims (5)
レームのチップ搭載部の形状が、凹凸形状よりなること
を特徴とするリードフレーム。1. A lead frame in which a chip mounting portion of a lead frame for mounting a semiconductor chip has an uneven shape.
レームのチップ搭載部の所定箇所に所定の材料によりめ
っきが施されていることを特徴とするリードフレーム。2. A lead frame, wherein a predetermined portion of a chip mounting portion of a lead frame for mounting a semiconductor chip is plated with a predetermined material.
材料により蒸着膜が形成されていることを特徴とする半
導体チップ。3. A semiconductor chip, wherein a vapor deposition film is formed of a predetermined material at a predetermined position on the back surface of the semiconductor chip.
を用いて構成されたことを特徴とする半導体装置。4. A semiconductor device comprising the lead frame according to claim 1 or 2.
成されたことを特徴とする半導体装置。5. A semiconductor device comprising the semiconductor chip according to claim 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28855093A JPH07142518A (en) | 1993-11-17 | 1993-11-17 | Lead frame, semiconductor chip, and semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28855093A JPH07142518A (en) | 1993-11-17 | 1993-11-17 | Lead frame, semiconductor chip, and semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07142518A true JPH07142518A (en) | 1995-06-02 |
Family
ID=17731701
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28855093A Pending JPH07142518A (en) | 1993-11-17 | 1993-11-17 | Lead frame, semiconductor chip, and semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07142518A (en) |
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WO2004074168A3 (en) * | 2003-02-20 | 2005-04-14 | Analog Devices Inc | Packaged microchip with thermal stress relief |
US6946742B2 (en) | 2002-12-19 | 2005-09-20 | Analog Devices, Inc. | Packaged microchip with isolator having selected modulus of elasticity |
US7166911B2 (en) | 2002-09-04 | 2007-01-23 | Analog Devices, Inc. | Packaged microchip with premolded-type package |
JP2008041707A (en) * | 2006-08-01 | 2008-02-21 | Nissan Motor Co Ltd | Semiconductor device and manufacturing method therefor |
US8344487B2 (en) | 2006-06-29 | 2013-01-01 | Analog Devices, Inc. | Stress mitigation in packaged microchips |
KR20150056520A (en) * | 2012-09-17 | 2015-05-26 | 리텔퓨즈 인코포레이티드 | Low thermal stress package for large area semiconductor dies |
US9676614B2 (en) | 2013-02-01 | 2017-06-13 | Analog Devices, Inc. | MEMS device with stress relief structures |
US10131538B2 (en) | 2015-09-14 | 2018-11-20 | Analog Devices, Inc. | Mechanically isolated MEMS device |
US10167189B2 (en) | 2014-09-30 | 2019-01-01 | Analog Devices, Inc. | Stress isolation platform for MEMS devices |
US11417611B2 (en) | 2020-02-25 | 2022-08-16 | Analog Devices International Unlimited Company | Devices and methods for reducing stress on circuit components |
-
1993
- 1993-11-17 JP JP28855093A patent/JPH07142518A/en active Pending
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7166911B2 (en) | 2002-09-04 | 2007-01-23 | Analog Devices, Inc. | Packaged microchip with premolded-type package |
US6946742B2 (en) | 2002-12-19 | 2005-09-20 | Analog Devices, Inc. | Packaged microchip with isolator having selected modulus of elasticity |
WO2004074168A3 (en) * | 2003-02-20 | 2005-04-14 | Analog Devices Inc | Packaged microchip with thermal stress relief |
JP2010101900A (en) * | 2004-09-28 | 2010-05-06 | Analog Devices Inc | Packaged microchip with premolded-type package |
US8344487B2 (en) | 2006-06-29 | 2013-01-01 | Analog Devices, Inc. | Stress mitigation in packaged microchips |
JP2008041707A (en) * | 2006-08-01 | 2008-02-21 | Nissan Motor Co Ltd | Semiconductor device and manufacturing method therefor |
KR20150056520A (en) * | 2012-09-17 | 2015-05-26 | 리텔퓨즈 인코포레이티드 | Low thermal stress package for large area semiconductor dies |
JP2015528648A (en) * | 2012-09-17 | 2015-09-28 | リテルヒューズ・インク | Low thermal stress package for wide area semiconductor dies. |
US9676614B2 (en) | 2013-02-01 | 2017-06-13 | Analog Devices, Inc. | MEMS device with stress relief structures |
US10167189B2 (en) | 2014-09-30 | 2019-01-01 | Analog Devices, Inc. | Stress isolation platform for MEMS devices |
US10759659B2 (en) | 2014-09-30 | 2020-09-01 | Analog Devices, Inc. | Stress isolation platform for MEMS devices |
US10131538B2 (en) | 2015-09-14 | 2018-11-20 | Analog Devices, Inc. | Mechanically isolated MEMS device |
US11417611B2 (en) | 2020-02-25 | 2022-08-16 | Analog Devices International Unlimited Company | Devices and methods for reducing stress on circuit components |
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