JP3036291B2 - Semiconductor device mounting structure - Google Patents
Semiconductor device mounting structureInfo
- Publication number
- JP3036291B2 JP3036291B2 JP5083987A JP8398793A JP3036291B2 JP 3036291 B2 JP3036291 B2 JP 3036291B2 JP 5083987 A JP5083987 A JP 5083987A JP 8398793 A JP8398793 A JP 8398793A JP 3036291 B2 JP3036291 B2 JP 3036291B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- solder
- mounting structure
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
【０００１】[0001]
【産業上の利用分野】本発明は、例えば高周波トランジ
スタ等のＩＣチップが窒化アルミニウム基板上に搭載さ
れた半導体装置の実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a semiconductor device in which an IC chip such as a high-frequency transistor is mounted on an aluminum nitride substrate.
【０００２】[0002]
【従来の技術】従来の半導体装置の実装構造としては、
例えば図２に示すようなものが知られている。この図に
示すように、窒化アルミニウム基板２１の上面はメタラ
イズ層２２（Ｗ，Ｍｏ等）により被覆され、このメタラ
イズ層２２の上面はメッキ層２３（Ｎｉ，Ｃｕ等）によ
り覆われている。そして、このメッキ層２３の上には金
（または銀）メッキ２９、はんだ２４を介してＩＣチッ
プ２５（Ｓｉ）が搭載されていた。また、このＩＣチッ
プ２５から所定距離だけ離間してリードフレーム２６
（４２アロイ，コバール合金等）の一端部が、ろう材２
７（Ａｇ７２〜８５Ｃｕ２８〜１５等）によりメッキ層
２３上に固着されていた。なお、このリードフレーム２
６上にも金（または銀）メッキが施されていた。さら
に、上記ＩＣチップ２５の端子はボンディングワイヤ２
８（Ａｕ等）によりメッキ層２３の上面の回路パターン
の一部に接合されている。2. Description of the Related Art Conventional semiconductor device mounting structures include:
For example, the one shown in FIG. 2 is known. As shown in this figure, the upper surface of the aluminum nitride substrate 21 is covered with a metallized layer 22 (W, Mo, etc.), and the upper surface of the metallized layer 22 is covered with a plating layer 23 (Ni, Cu, etc.). An IC chip 25 (Si) was mounted on the plating layer 23 via gold (or silver) plating 29 and solder 24. The lead frame 26 is separated from the IC chip 25 by a predetermined distance.
(42 alloy, Kovar alloy etc.)
7 (Ag 72 to 85 Cu 28 to 15, etc.) on the plating layer 23. Note that this lead frame 2
6 was also plated with gold (or silver). Further, the terminals of the IC chip 25 are bonding wires 2
8 (Au or the like) is joined to a part of the circuit pattern on the upper surface of the plating layer 23.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな従来のＩＣチップの実装構造にあっては、窒化アル
ミニウム基板とリードフレームとの熱膨張係数差が大き
いため、リードフレームの銀ろう付時にリードフレーム
の下部に応力集中が生じる。この結果、当該部分のメタ
ライズ層、窒化アルミニウム基板にクラックが発生し、
リードフレームと窒化アルミニウム基板との間の密着強
度が低下するという課題があった。However, in such a conventional mounting structure of an IC chip, the difference in the thermal expansion coefficient between the aluminum nitride substrate and the lead frame is large, so that the lead frame is soldered when the lead frame is silver-brazed. Stress concentration occurs at the bottom of the frame. As a result, cracks occur in the metallized layer and the aluminum nitride substrate in that portion,
There has been a problem that the adhesion strength between the lead frame and the aluminum nitride substrate is reduced.
【０００４】また、ＩＣチップを固着するはんだは表面
の粗いメタライズ層上の金（または銀）メッキ上に塗布
していたため、はんだのなじみが悪いという課題があっ
た。さらに、ワイヤをメッキ層表面に直接ボンディング
していたため、メタライズ層表面の凹凸（Ｒａ値で３μ
ｍ程度）によりメッキ層とボンディングワイヤとの間の
接合強度が低下してボンディング不良が発生するという
課題があった。[0004] In addition, since the solder for fixing the IC chip is applied on the gold (or silver) plating on the metallized layer having a rough surface, there is a problem that the adaptability of the solder is poor. Furthermore, since the wire was directly bonded to the surface of the plating layer, irregularities ( Ra value of 3 μm)
m), there is a problem in that the bonding strength between the plating layer and the bonding wire is reduced and bonding failure occurs.
【０００５】[0005]
【課題を解決するための手段】請求項１に記載の半導体
装置の実装構造は、セラミックス基板と、このセラミッ
クス基板上に積層されたメタライズ層と、このメタライ
ズ層の上面に被着されたメッキ層と、このメッキ層の上
面に被着されたろう材層と、このろう材層の上面にはん
だを介して搭載された半導体装置と、このろう材層の上
面にその一端部が固着されたリードフレームとを備えた
半導体装置の実装構造である。According to a first aspect of the present invention, there is provided a mounting structure of a semiconductor device, comprising: a ceramic substrate; a metallized layer laminated on the ceramic substrate; and a plating layer deposited on the upper surface of the metallized layer. A brazing material layer adhered to the upper surface of the plating layer, a semiconductor device mounted on the upper surface of the brazing material layer via solder, and a lead frame having one end fixed to the upper surface of the brazing material layer This is a mounting structure of a semiconductor device having:
【０００６】また、請求項２に記載の半導体装置の実装
構造にあっては、上記セラミックス基板が窒化アルミニ
ウム基板である。In the semiconductor device mounting structure according to the second aspect, the ceramic substrate is an aluminum nitride substrate.
【０００７】[0007]
【作用】請求項１に記載の半導体装置の実装構造によれ
ば、リードフレームを接合するためのろう材の窒化アル
ミニウム基板への接合面積が大幅に増大している。この
結果、ろう材がリードフレームと窒化アルミニウム基板
との間の応力を緩和し、クラックの発生を防止すること
ができる。また、表面が平坦であるろう材層に対してワ
イヤをボンディングすることができるため、そのボンデ
ィング性が良好となる。すなわち、ボンディング不良の
発生率が減少する。また、その際の作業性が良好なもの
となる。また、ろう材層の上にはんだを介して半導体装
置を搭載する構造であるため、はんだがなじみ易くその
搭載性が良好となる。また、ろう材をメッキ層の略全面
に対して被着するため、その一部に被着する従来の場合
に比較して、そのろう材被着の作業性も大幅に向上す
る。さらに、全面に被着したろう材層に対してリードフ
レームを接合するため、接合の作業性も従来に比して大
幅に向上する。According to the semiconductor device mounting structure of the first aspect, the bonding area of the brazing material for bonding the lead frame to the aluminum nitride substrate is greatly increased. As a result, the brazing material can alleviate the stress between the lead frame and the aluminum nitride substrate, and can prevent cracks from occurring. Further, since the wire can be bonded to the brazing material layer having a flat surface, the bonding property is improved. That is, the rate of occurrence of bonding defects is reduced. In addition, workability at that time is improved. In addition, since the semiconductor device is mounted on the brazing material layer via the solder, the solder is easily adapted and the mountability is improved. Further, since the brazing material is applied to substantially the entire surface of the plating layer, the workability of applying the brazing material is greatly improved as compared with the conventional case in which the brazing material is applied to a part thereof. Further, since the lead frame is joined to the brazing material layer deposited on the entire surface, the workability of joining is greatly improved as compared with the related art.
【０００８】請求項２に記載の半導体装置の実装構造に
あっては、窒化アルミニウム基板に半導体装置を搭載し
たため、発熱量の大きい半導体装置、例えばパワートラ
ンジスタ等を搭載した場合でもその放熱をスムーズに行
うことができる。In the semiconductor device mounting structure according to the second aspect, since the semiconductor device is mounted on the aluminum nitride substrate, even when a semiconductor device having a large amount of heat, such as a power transistor, is mounted, the heat is smoothly radiated. It can be carried out.
【０００９】[0009]
【実施例】以下、図面を参照して本発明に係る半導体装
置の実装構造についての一実施例を説明する。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a mounting structure of a semiconductor device according to the present invention.
【００１０】図１に示すように、窒化アルミニウム基板
１１は、その上面にメタライズ層１２（ＷまたはＭｏ）
が積層されている。このメタライズ層１２の厚さは１０
〜３０μｍ程度である。メタライズ層１２の上面全面に
はＮｉまたはＣｕからなるメッキ層１３が例えば１〜８
μｍの厚さに被着されている。As shown in FIG. 1, an aluminum nitride substrate 11 has a metallized layer 12 (W or Mo) on its upper surface.
Are laminated. The thickness of this metallized layer 12 is 10
About 30 μm. On the entire upper surface of the metallized layer 12, a plating layer 13 made of Ni or Cu
It is applied to a thickness of μm.
【００１１】このように構成された窒化アルミニウム基
板１１に対してその上面にはＩＣチップ（Ｓｉ）１５お
よびリードフレーム１６（４２アロイ，コバール合金）
の一端部が搭載または接合されている。すなわち、上記
メッキ層１３の上面全面に例えばＡｇ８５Ｃｕ１５組成
の銀ろう１７（第１および第２のろう材層を兼ねるも
の）が被着されている。この銀ろう１７の厚さは例えば
２０μｍ程度としている。なお、ろう材としてはこの他
にもＡｇ７２〜８５Ｃｕ２８〜１５の範囲のものが好適
であるが、これらに限られるものではなく、リードフレ
ームの材質等により適宜選択するものとする。そして、
この銀ろう１７の表面は平坦に（例えばＲａ値で１μｍ
程度）形成されている。An IC chip (Si) 15 and a lead frame 16 (42 alloy, Kovar alloy) are provided on the upper surface of the aluminum nitride substrate 11 thus configured.
Is mounted or joined. That is, a silver braze 17 having a composition of, for example, Ag 85 Cu 15 (also serving as the first and second brazing material layers) is applied to the entire upper surface of the plating layer 13. The thickness of the silver solder 17 is, for example, about 20 μm. In addition, as the brazing material, a material in the range of Ag 72 to 85 Cu 28 to 15 is suitable, but is not limited thereto, and may be appropriately selected depending on the material of the lead frame. And
The surface of the silver solder 17 is flat (for example, 1 μm in Ra value).
Degree) is formed.
【００１２】また、この銀ろう１７の上面にはリードフ
レーム１６の一端部が固着、接合されている。さらに、
このリードフレーム１６上面および銀ろう１７の上面に
は金メッキ（または銀メッキ）層１９が所定の厚さに施
されている。そして、このリードフレーム１６の一端部
から所定間隔だけ離間して金メッキ層１９の上面にはは
んだ１４を介して上記ＩＣチップ１５が搭載されてい
る。このＩＣチップ１５表面の端子は金等のボンディン
グワイヤ１８により金メッキ層１９の表面に固着、接合
されている。また、リードフレーム１６とＩＣチップ１
５が同一ではない（異なる）メタライズ層上にそれぞれ
搭載されている場合もある。One end of a lead frame 16 is fixedly connected to the upper surface of the silver solder 17. further,
A gold plating (or silver plating) layer 19 is formed to a predetermined thickness on the upper surface of the lead frame 16 and the upper surface of the silver solder 17. The IC chip 15 is mounted on the upper surface of the gold plating layer 19 via the solder 14 at a predetermined distance from one end of the lead frame 16. The terminals on the surface of the IC chip 15 are fixed and bonded to the surface of the gold plating layer 19 by bonding wires 18 such as gold. Also, the lead frame 16 and the IC chip 1
5 may be respectively mounted on non-identical (different) metallization layers.
【００１３】以上の構成に係るＩＣチップの基板への実
装構造にあっては、ＩＣチップ１５の発熱に対して窒化
アルミニウム基板１１が放熱板として機能する。このと
き、リードフレーム１６の接合部分にあって窒化アルミ
ニウム基板１１等との熱膨張係数差による応力が付加さ
れても、従来に比して大面積、大容量の銀ろう１７がこ
の応力を緩和する。この結果、窒化アルミニウム基板１
１等にクラック等が生じることはない。すなわち、リー
ドフレーム１６の窒化アルミニウム基板１１に対する接
合強度を大幅に増加させることができ、本構造の耐久性
を飛躍的に高めることができるものである。In the structure for mounting an IC chip on a substrate according to the above configuration, the aluminum nitride substrate 11 functions as a heat radiating plate against heat generated by the IC chip 15. At this time, even if a stress due to a difference in thermal expansion coefficient from that of the aluminum nitride substrate 11 or the like is applied to the joint portion of the lead frame 16, the silver solder 17 having a larger area and a larger capacity than in the related art relieves this stress. I do. As a result, the aluminum nitride substrate 1
No cracks or the like occur in 1st class or the like. That is, the bonding strength of the lead frame 16 to the aluminum nitride substrate 11 can be greatly increased, and the durability of the present structure can be drastically increased.
【００１４】また、このＩＣチップ１５、リードフレー
ム１６の実装は、以下の手順によりなされる。すなわ
ち、窒化アルミニウム基板１１表面のメタライズする
（ペースト塗布後焼成）。次に、メタライズ層１２の上
面略全面をメッキする。さらに、メッキ層１３上の略全
面に銀ろう１７を塗布する。この場合、全面に対して塗
布するため銀ろう１７の塗布作業がきわめて容易であ
る。次いで、銀ろう１７の表面の所定位置にリードフレ
ーム１６の一端部を配置してこれを加熱し、接合する。
さらに、リードフレーム１６の上面および銀ろう１７の
上面に対して金メッキ１９を施す。そして、はんだ１４
を金メッキ層１９表面の所定位置に一定量だけ供給し、
ＩＣチップ１５をこのはんだ１４上に載置する。このと
き、はんだ１４は銀ろう１７および金メッキ層１９に対
してよくなじみＩＣチップ１５の搭載作業が良好とな
る。最後に、超音波ボンディングによりワイヤ１８を接
続する。The mounting of the IC chip 15 and the lead frame 16 is performed according to the following procedure. That is, the surface of the aluminum nitride substrate 11 is metallized (pasted and baked). Next, substantially the entire upper surface of the metallized layer 12 is plated. Further, a silver solder 17 is applied to substantially the entire surface of the plating layer 13. In this case, since the coating is performed on the entire surface, the coating operation of the silver solder 17 is extremely easy. Next, one end of the lead frame 16 is arranged at a predetermined position on the surface of the silver solder 17 and is heated and joined.
Further, gold plating 19 is applied to the upper surface of the lead frame 16 and the upper surface of the silver solder 17. And solder 14
Is supplied to a predetermined position on the surface of the gold plating layer 19 by a certain amount,
The IC chip 15 is placed on the solder 14. At this time, the solder 14 is well adapted to the silver solder 17 and the gold plating layer 19, and the mounting operation of the IC chip 15 is improved. Finally, the wires 18 are connected by ultrasonic bonding.
【００１５】なお、銀ろう１７は必ずしもメッキ層１３
の全面に被着しなくても、リードフレーム１６の接合部
分およびはんだ１４塗布部分について被着するものであ
ってもよい。この場合、リードフレーム１６の接合部分
にあっては、リードフレーム１６の接着部よりも例えば
１ｍｍ２以上の広さに銀ろう１７を塗布するものとす
る。なお、本発明は窒化アルミニウム基板に限られず高
放熱性が要求される他のセラミックス基板についても適
用することができるものでもある。Note that the silver solder 17 is not necessarily the plating layer 13.
May be applied to the joint portion of the lead frame 16 and the solder 14 application portion. In this case, it is assumed that the silver solder 17 is applied to the bonding portion of the lead frame 16 so as to have a width of, for example, 1 mm 2 or more than the bonding portion of the lead frame 16. The present invention is not limited to the aluminum nitride substrate, but can be applied to other ceramic substrates requiring high heat dissipation.
【００１６】[0016]
【発明の効果】本発明によれば、セラミックス基板等で
のクラックの発生を防止することができる。また、ボン
ディング不良の発生率が減少する。また、ワイヤボンデ
ィングの作業性が良好となる。また、はんだがなじみ易
く、半導体装置の搭載が容易である。また、従来に比較
して、ろう材被着の作業性が大幅に向上する。さらに、
リードフレーム接合の作業性も従来に比して大幅に向上
する。According to the present invention, the occurrence of cracks in a ceramic substrate or the like can be prevented. Further, the rate of occurrence of bonding defects is reduced. Further, workability of wire bonding is improved. In addition, the solder is easy to adjust, and the mounting of the semiconductor device is easy. In addition, the workability of applying the brazing material is greatly improved as compared with the related art. further,
The workability of lead frame joining is also greatly improved as compared with the conventional case.
【図１】本発明の一実施例に係る半導体装置の実装構造
を示す断面図である。FIG. 1 is a sectional view showing a mounting structure of a semiconductor device according to one embodiment of the present invention.
【図２】従来の半導体装置の実装構造を示す断面図であ
る。FIG. 2 is a cross-sectional view showing a mounting structure of a conventional semiconductor device.
１１ 窒化アルミニウム基板 １２ メタライズ層 １３ メッキ層 １４ はんだ １５ ＩＣチップ １６ リードフレーム １７ 銀ろう DESCRIPTION OF SYMBOLS 11 Aluminum nitride substrate 12 Metallization layer 13 Plating layer 14 Solder 15 IC chip 16 Lead frame 17 Silver solder
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−18648（ＪＰ，Ａ) 特開 昭63−289950（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/52 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-18648 (JP, A) JP-A-63-289950 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/12 H01L 21/52
Claims (2)
装置と、 このろう材層の上面にその一端部が固着されたリードフ
レームとを備えたことを特徴とする半導体装置の実装構
造。1. A ceramic substrate, a metallized layer laminated on the ceramic substrate, a plated layer deposited on an upper surface of the metallized layer, a brazing material layer deposited on an upper surface of the plated layer, A mounting structure of a semiconductor device, comprising: a semiconductor device mounted on an upper surface of a brazing material layer via solder; and a lead frame having one end fixed to the upper surface of the brazing material layer.
ム基板である請求項１に記載の半導体装置の実装構造。2. The mounting structure according to claim 1, wherein said ceramic substrate is an aluminum nitride substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5083987A JP3036291B2 (en) | 1993-03-18 | 1993-03-18 | Semiconductor device mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5083987A JP3036291B2 (en) | 1993-03-18 | 1993-03-18 | Semiconductor device mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06283621A JPH06283621A (en) | 1994-10-07 |
| JP3036291B2 true JP3036291B2 (en) | 2000-04-24 |
Family
ID=13817896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5083987A Expired - Lifetime JP3036291B2 (en) | 1993-03-18 | 1993-03-18 | Semiconductor device mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3036291B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8603017B2 (en) | 2005-03-07 | 2013-12-10 | American Medical Innovations, L.L.C. | Vibrational therapy assembly for treating and preventing the onset of deep venous thrombosis |
| US8795210B2 (en) | 2006-07-11 | 2014-08-05 | American Medical Innovations, L.L.C. | System and method for a low profile vibrating plate |
-
1993
- 1993-03-18 JP JP5083987A patent/JP3036291B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8603017B2 (en) | 2005-03-07 | 2013-12-10 | American Medical Innovations, L.L.C. | Vibrational therapy assembly for treating and preventing the onset of deep venous thrombosis |
| US8795210B2 (en) | 2006-07-11 | 2014-08-05 | American Medical Innovations, L.L.C. | System and method for a low profile vibrating plate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06283621A (en) | 1994-10-07 |
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