EP0263146A1 - Aluminum-backed wafer and chip - Google Patents

Aluminum-backed wafer and chip

Info

Publication number
EP0263146A1
EP0263146A1 EP87902270A EP87902270A EP0263146A1 EP 0263146 A1 EP0263146 A1 EP 0263146A1 EP 87902270 A EP87902270 A EP 87902270A EP 87902270 A EP87902270 A EP 87902270A EP 0263146 A1 EP0263146 A1 EP 0263146A1
Authority
EP
European Patent Office
Prior art keywords
chip
aluminum
gold
layer
attachment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP87902270A
Other languages
German (de)
French (fr)
Inventor
Carl M. Roberts
John R. Saxelby, Jr.
Roger M. Moseson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of EP0263146A1 publication Critical patent/EP0263146A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • This invention relates to an aluminum-backed wafer and chip substrates produced therefrom for attachment to any lead frame package and to a process for producing same.
  • the invention also relates to a package having an eutectic mounted aluminum-backed chip and to a method of producing such packages.
  • a wafer such as a thin insulating disc, usually silicon, having a large number of identical circuits formed on its face or top surface is first fabricated.
  • the back of each chip is mounted or secured onto a package receiving surface such as a cavity or tab of a package housing. This mounting or securing of the chip back is generally obtained by way of .a thin layer of gold plating on the package cavity or tab which is used as the bonding agent.
  • This mounting or securing is usually accomplished by heating the receiving surface of a package and by use of mild pressure and slight relative motion, called “scrubbing", between the back of the chip and the package receiving surface. Scrubbing can be accomplished by placing the back of the chip: onto the heated surface of the receiving package, onto full gold preform on the surface of the receiving package and wait- ing for the preform to melt, or, into previously placed and molten silicon/gold or other eutectic preform.
  • the mounting of the chip to such a package receiving surface or housing has not been entirely satisfactory for a number of reasons but especially because of the incompleteness of the bonding contact between the back side of the chip and the receiving surface of the package to which the chip is being mounted.
  • the backside surface area of the chip In generaly only about 10 to about 70%, usually only about 20 to 30%, of the backside surface area of the chip is in bonding contact or attachment with the receiving surface of the package. This limited contact area between chip back side and receiving surface of the package produces numer ⁇ ous undesirable and detrimental results.
  • the limited contact area produces a mismatch in the coefficients of thermal expansion of the attached and non-attached regions of the chip back, leading to differing rates of thermal expansion across the bottom or back of the chip, thus causing or resulting in undesirable non-uniform thermal expansion stresses in the top or circuit surface regions of the chip.
  • non-hermetic type plastic packaging due to the compres- sive forces of the plastic molding compound causing the chip to bend or distort, and thus resulting in non-uniform compressional stresses on the top surface of the chip.
  • These non-uniform streesses produced by the incomplete chip-package attachment condition mentioned result in uneven and changeable eletrical performance of the chip circuit or can render the circuit inoperable for its in ⁇ tended purpose or lead to early failure of the chip circuit.
  • a chip could be provided which enable essentially 100% attachment of its back surface to the receiving surface of a package. and that such would eliminate or minimize the aforemen ⁇ tioned deficiencies of partial chip backside attachment, while avoiding the unwanted results of a polymeric or silver/glass chip attach system.
  • a chip which provides essentially 100 % attachment of its back surface to the receiving surface of a package is provided by coating the silicon back surface of a silicon wafer, from which the chip is produced, with an attachment coating of aluminum.
  • Individual aluminum-backed chips produced by cutting such aluminum-backed silicon wafers into chips can then be eutectically mounted to the receiving surface, such as a cavity or tab, of any suitable package, such as a metal can header, sidebraze, cerdip, plastic package or the like, for achieving essentially 100% attachment.
  • a coating of aluminum is deposited as an attachment coating on the back side, opposite the electronic circuits, of a wafer.
  • a typical wafer may be about 5 inches in diameter and about 25 mils in thickness and be capable of being divided into 500 to 12,000 chips. Individual chips are then produced from such aluminum-backed wafers by separation in a conventional manner, such as by diamond scribing, laser scribing or saw- ing and the like.
  • the aluminum-backed chip produced from such aluminum-backed wafers can be mounted to a cavity or tab or other receiving surface of any suitable package using an eutectic preform, and the resulting bonding con ⁇ tact area between the chip back side and the receiving sur- face of the package will generally be in the range of from about 90 to 100%, usually at least 97 or 98%.
  • the resultin packaged devices have virtually eliminated or significantly reduced the effects of the detrimental stresses due to non- uniform thermal expansion and thermal dissipation as well as compressional forces resulting from the prior art relatively high percentage area of non-attachment between the chip back side and the receiving surface of the package.
  • the packaged products of this invention having bonding contact areas of attachment of from 90 to 100%, and usually at least 97 or 98%, have a coefficient of expansion across the chip that is essentially equalized and normalized resulting in reduced stresses in the top or circuit side of the chip.
  • the packaged products of the invention provide thermal dissipation across essentially the entire back side of the attached chip essentially equalizing and normalizing thermal gradients, thereby producing a more uniform thermal gradient across the chip and thus reducing the thermally induced stresses.
  • due to the high degree of attachment or bonding contact between the chip back side and the receiving surface of the package significantly reduced bending or compressional stress is obtained and compressional stresses are more uniformly equalized and normalized throughout the chip.
  • the aluminum attachment coating on the chip back side prevents or inhibits undesirable gold diffusion into the backside of the chip.
  • the chip can now be attached or mounted to other materials in addition to gold, such as for example, to copper, aluminum and nickel, thereby often eliminating the nec- cessity for more expensive gold receiving surfaces in the packages. Since the aluminum-backed chip is mounted with a eutectic preform, preferably a silicon/gold eutec ⁇ tic preform, a lower temperature melt at the receiving surface of the package can be employed, and good uniform contact is obtained by scrubbing the chip and the receiv- ing surface together.
  • the circuits on the chip exhibit excellent matching when mounted onto a package in accordance with this invention, even after thermal cycling over the relatively large thermal range of -55 ⁇ C to 125°C for 15 cycles, when direct exposure of the chip surface and the package.
  • the change in resistance of resistors on chips mounted according to this invention and subject to the aforementioned relatively severe thermal cycling, measured before and after thermal cycling was generally less than 0.003% and usually only 0.001% or less.
  • adhesion of the chip to the chip receiving surface of the package remained excellent, and there was no cracking or separation of the chip.
  • aluminum is deposited as an attachment coating on the back side of a wafer.
  • the deposition of the aluminum coating can be accomplished either before or after passivation of the wafer, although generally, and most preferably, deposi ⁇ tion is done after passivation of the finished wafer and prior to cutting of the wafer into many individual chips.
  • deposition of the aluminum attachment layer on the back side of the wafer can be done with or without removal of any oxide layer built up on the wafer back side.
  • the deposition of the aluminum attach ⁇ ment coating on the back side of the wafer is done after passivation of the wafer, and after any oxide surface has been removed from the back side of the wafer. Neces ⁇ sity for removal of any oxide layer from the back side can of course be avoided by preventing any oxide from originally occurring on the wafer back side before aluminizing.
  • oxide is to be removed from the wafer back side before aluminum deposition, the removal can be accomplished after fabrication of the wafer or within the main wafer fabrication process. Removal of the oxide from the wafer back side can be done by conven ⁇ tional plasma, chemical or sputter etch techniques, for example. It will be appreciated that during removal of oxide after fabrication of the wafer, the circuit (front or top) side of the wafer is to be protected by use of a photoresist deposited on the top side so as to avoid any damage thereto during etch of the wafer back side.
  • Deposition of the aluminum attachment layer onto the back side of a wafer, from which the oxide layer may or may not have been removed can be accom ⁇ plished by any suitable deposition techniques capable of depositing a thin uniform aluminum layer: for example, such as by deposition from the vapor state by evapora- tion, or by sputter (ion bombardment) deposition. If the oxide layer is to be removed by a sputter etch, the subsequent deposition of the aluminum layer may, if desired, be sputter deposited as part of the same vacuum process. Generally, the evaporation methods of deposition are preferred.
  • the thickness of the aluminum attachment layer deposited on the back side of the wafer will generally be at least 5,000 A thick, preferably from about 10,000 to about 30,000 A and most preferably about 15,000 A thick.
  • Wafers, on which an aluminum attachment layer has been deposited on the back side thereof, are then separated into individual chips for mounting onto a receiving area of a package, such as for example, onto a cavity or onto a tab of any suitable lead frame package.
  • Attachment or mounting of the aluminum-backed chip to the receiving area of the package is by way of an eutec- tic preform material.
  • Mounting at about 370 to about 450°C, generally at about 380 to 425°C and preferably at about 390°C, is obtained with a gold eutectic preform.
  • gold preforms such as for example, gold/ tin, gold/germanium and gold/tin/silicon preforms and the like which cause the aluminum to bond to the package may also be employed.
  • Another advantage obtained with the aluminum- backed chips of this invention is the reduction or pre ⁇ vention of diffusion of gold into the back side of the silicon die. Since aluminum will be absorbing or alloy ⁇ ing with the eutectic materials, not as much or no gold is diffused into the back side of the silicon wafer or chip. If desired, a covering of the aluminum-backed wafer by an additional conductive barrier film layer of any suitable barrier material, such as titanium or tungsten or the like may be employed. This additional barrier layer can be deposited on the first aluminum layer, and then a second aluminum attachment layer deposited so as to cover the barrier layer for prevent ⁇ ing diffusion of gold into the back side of the silicon wafer.
  • a conductive barrier film layer may first be deposited on the back side of the silicon wafer before deposition of the aluminum attachment layer.
  • Prevention or substantial elimination of such undesired gold diffusion into the back side of the sili ⁇ con wafer is also obtained by this invention since the presence of an aluminum attachment layer on the wafer back side allows the use of a lower temperature of the gold eutectic preform at the receiving surface of the package cavity or tab during mounting of the aluminum- backed chip.
  • the aluminum backed circuit chips of this invention may be mounted to one another, in either back-to-back or back- to-front relationship, such as for use in sensor prod- ucts or other die - die mounted products.
  • the aluminum backed side of a first chip may be etched to a pattern to match all or a portion of the circuit on the top side of a second such chip and the etched aluminum pattern of the first chip connected to all or a portion of the circuit on the top side of the second chip by way of etched vias in the first chip.
  • the aluminum backed side of a first chip could be similarly mounted to the aluminum backed side of a second chip.
  • attachment of the chips in front-to-back or back-to-back relationship could ' be accomplished, for example, by using gold preforms, preferably a gold/silicon preform, and conventional chip attachment or by bonding with locally applied ultrasonic or thermosonic energy or by soldering using an appropriate preform.
  • gold preforms preferably a gold/silicon preform
  • conventional chip attachment or by bonding with locally applied ultrasonic or thermosonic energy or by soldering using an appropriate preform.
  • Silicon wafers having circuits formed on the front surface thereof are fabricated according to any of the many known and varied techniques for producing same. After passivation of the wafers, the back sur ⁇ face of the wafers are, if desired, freed of any resid ⁇ ual oxide by sand blasting followed by plasma or chemi- cal etching. Thereafter, an attachment layer of alu ⁇ minum of a thickness of about 15,000 A is deposited on the wafer back side by sputtering using a Perkin Elmer 4400 sputter machine with an argon gas ambient at a pressure of about 7 microns, for example, while protecting the top surface (circuit) side of the wafer by any known protection techniques. The wafers are placed in the sputtering machinery with the top or cir ⁇ cuit side facing down, thus shielding the front side, and the wafer back side is exposed for collection of the sputtered aluminum.
  • the wafers are cut into individual chips, such as for example, by wafer sawing or the like.
  • the resulting individual aluminum-backed chip is then attached to the receiving surface of a package by way of a gold eutectic preform material, such as a gold/silicon eutectic preform.
  • a gold eutectic preform material such as a gold/silicon eutectic preform.
  • the individual chip is attached to the gold cavity of a sidebraze package by a 98/2 weight percent gold/silicon eutectic preform at 390°C by scrubbing the aluminum-backed chip into the gold cavity.

Abstract

Les contraintes non-uniformes dues à la compression, à la dissipation thermique et à la dilatation thermique dans des dispositifs à puce condititionnés en boîtiers sont éliminées ou sensiblement réduites en appliquant une couche d'aluminium sur la face arrière des tranches d'où les puces elles-mêmes, qui doivent être montées dans le dispositif à puce en boîtiers, sont produites. Les puces doublées d'aluminium produites à partir des tranches doublées d'aluminium peuvent être fixées sur des cavités ou des languettes de boîtiers de sorte qu'une fixation ou d'un contact de liaison à 100% de la face arrière de la puce sur le boîtier est obtenu lorsque la puce y est rattachée avec un matériau de préforme eutéctique en or.Non-uniform stresses due to compression, heat dissipation and thermal expansion in chip devices packaged in packages are eliminated or significantly reduced by applying a layer of aluminum on the rear face of the wafers from which the chips themselves, which must be mounted in the chip device in housings, are produced. Aluminum-lined chips produced from aluminum-lined wafers can be attached to cavities or housing tabs so that a 100% binding or binding contact from the back side of the chip on the case is obtained when the chip is attached to it with a gold eutectic preform material.

Description

ALUMINUM-BAC ED WAFER AND CHIP
1. Field of the Invention
This invention relates to an aluminum-backed wafer and chip substrates produced therefrom for attachment to any lead frame package and to a process for producing same. The invention also relates to a package having an eutectic mounted aluminum-backed chip and to a method of producing such packages.
2. Background of the Invention In producing semiconductor integrated circuit chips or die for use in electronic equipment, a wafer, such as a thin insulating disc, usually silicon, having a large number of identical circuits formed on its face or top surface is first fabricated. Upon completion of wafer fabrication and after preliminary testing of each device and then severing of the wafer into individual chips, the back of each chip is mounted or secured onto a package receiving surface such as a cavity or tab of a package housing. This mounting or securing of the chip back is generally obtained by way of .a thin layer of gold plating on the package cavity or tab which is used as the bonding agent. This mounting or securing is usually accomplished by heating the receiving surface of a package and by use of mild pressure and slight relative motion, called "scrubbing", between the back of the chip and the package receiving surface. Scrubbing can be accomplished by placing the back of the chip: onto the heated surface of the receiving package, onto full gold preform on the surface of the receiving package and wait- ing for the preform to melt, or, into previously placed and molten silicon/gold or other eutectic preform.
However, the mounting of the chip to such a package receiving surface or housing has not been entirely satisfactory for a number of reasons but especially because of the incompleteness of the bonding contact between the back side of the chip and the receiving surface of the package to which the chip is being mounted. In generaly only about 10 to about 70%, usually only about 20 to 30%, of the backside surface area of the chip is in bonding contact or attachment with the receiving surface of the package. This limited contact area between chip back side and receiving surface of the package produces numer¬ ous undesirable and detrimental results. For example, the limited contact area produces a mismatch in the coefficients of thermal expansion of the attached and non-attached regions of the chip back, leading to differing rates of thermal expansion across the bottom or back of the chip, thus causing or resulting in undesirable non-uniform thermal expansion stresses in the top or circuit surface regions of the chip.
Additionally, there is non-uniform thermal dis¬ sipation of heat from the chip to the package due to the partial contact of the chip to the-package. Since the area of best thermal dissipation is created in the attach- ment region, other heat escape paths in non-attachment areas create differeng and non-uniform thermal gradients throughout the chip resulting in non-uniform thermal dissipation stresses in the top surface of the chip. More¬ over, while the above undesirable stresses exist in hermetic packages, they are exacerbated therein by the ..
non-hermetic type plastic packaging, due to the compres- sive forces of the plastic molding compound causing the chip to bend or distort, and thus resulting in non-uniform compressional stresses on the top surface of the chip. These non-uniform streesses produced by the incomplete chip-package attachment condition mentioned result in uneven and changeable eletrical performance of the chip circuit or can render the circuit inoperable for its in¬ tended purpose or lead to early failure of the chip circuit.
It would be highly desirable therefore to provide a chip which has essentially 100% attachment of the chip back side to the receiving surface of the package so that the aforementioned non-uniform thermal dissipation, com¬ pressional and thermal expansion stresses, and resulting performance drawbacks of the packaged circuits, could be avoided or substantially eliminated. It has previously been proposed that either a polymeric chip attach material, such as an epoxy or polymide polymer, or a com¬ bination of silver and glass as a chip attach material, be employed.
However, each of these proposals themselves pro¬ duce unacceptable drawbacks and problems. Polymeric chip attach materials suffer from outgas of moisture from within the polymer and evenually may result in device corrosion. To utilize the silver/glass combination as a chip attach medium, the curing of the silver/glass requires furnace processing at approximately 400 to 420°C for several min¬ utes. This high temperature curing causes extensive oxida¬ tion of sealing surfaces on both header and sidebraze pack- ages, and such oxidation seriously adversely affects seal yield.
Therefore, it would be most beneficial if a chip could be provided which enable essentially 100% attachment of its back surface to the receiving surface of a package. and that such would eliminate or minimize the aforemen¬ tioned deficiencies of partial chip backside attachment, while avoiding the unwanted results of a polymeric or silver/glass chip attach system.
SUMMARY OF THE INVENTION
It has been discovered that a chip which provides essentially 100 % attachment of its back surface to the receiving surface of a package is provided by coating the silicon back surface of a silicon wafer, from which the chip is produced, with an attachment coating of aluminum. Individual aluminum-backed chips produced by cutting such aluminum-backed silicon wafers into chips can then be eutectically mounted to the receiving surface, such as a cavity or tab, of any suitable package, such as a metal can header, sidebraze, cerdip, plastic package or the like, for achieving essentially 100% attachment.
DETAILED DESCRIPTION OF THE INVENTION According to this invention a coating of aluminum is deposited as an attachment coating on the back side, opposite the electronic circuits, of a wafer. A typical wafer may be about 5 inches in diameter and about 25 mils in thickness and be capable of being divided into 500 to 12,000 chips. Individual chips are then produced from such aluminum-backed wafers by separation in a conventional manner, such as by diamond scribing, laser scribing or saw- ing and the like. The aluminum-backed chip produced from such aluminum-backed wafers can be mounted to a cavity or tab or other receiving surface of any suitable package using an eutectic preform, and the resulting bonding con¬ tact area between the chip back side and the receiving sur- face of the package will generally be in the range of from about 90 to 100%, usually at least 97 or 98%. The resultin packaged devices have virtually eliminated or significantly reduced the effects of the detrimental stresses due to non- uniform thermal expansion and thermal dissipation as well as compressional forces resulting from the prior art relatively high percentage area of non-attachment between the chip back side and the receiving surface of the package.
The packaged products of this invention having bonding contact areas of attachment of from 90 to 100%, and usually at least 97 or 98%, have a coefficient of expansion across the chip that is essentially equalized and normalized resulting in reduced stresses in the top or circuit side of the chip. Likewise, the packaged products of the invention provide thermal dissipation across essentially the entire back side of the attached chip essentially equalizing and normalizing thermal gradients, thereby producing a more uniform thermal gradient across the chip and thus reducing the thermally induced stresses. Similarly, due to the high degree of attachment or bonding contact between the chip back side and the receiving surface of the package, significantly reduced bending or compressional stress is obtained and compressional stresses are more uniformly equalized and normalized throughout the chip.
Numerous other advantages are obtained with this invention. For example, the aluminum attachment coating on the chip back side prevents or inhibits undesirable gold diffusion into the backside of the chip. Moreover, the chip can now be attached or mounted to other materials in addition to gold, such as for example, to copper, aluminum and nickel, thereby often eliminating the nec- cessity for more expensive gold receiving surfaces in the packages. Since the aluminum-backed chip is mounted with a eutectic preform, preferably a silicon/gold eutec¬ tic preform, a lower temperature melt at the receiving surface of the package can be employed, and good uniform contact is obtained by scrubbing the chip and the receiv- ing surface together. Significantly, the circuits on the chip, especially the thin film resistors on the chip, exhibit excellent matching when mounted onto a package in accordance with this invention, even after thermal cycling over the relatively large thermal range of -55βC to 125°C for 15 cycles, when direct exposure of the chip surface and the package. The change in resistance of resistors on chips mounted according to this invention and subject to the aforementioned relatively severe thermal cycling, measured before and after thermal cycling was generally less than 0.003% and usually only 0.001% or less. Moreover, adhesion of the chip to the chip receiving surface of the package remained excellent, and there was no cracking or separation of the chip.
Full bonding contact between chip back side and the receiving surface of the package for aluminum-backed chips of this invention was confirmed by sawing trans¬ versely through mounted chip and package at several loca¬ tions and observing full bonding contact between the chip back side and the package surface extending across the full expanse of the cut section in each instance.
In accordance with this invention aluminum is deposited as an attachment coating on the back side of a wafer. The deposition of the aluminum coating can be accomplished either before or after passivation of the wafer, although generally, and most preferably, deposi¬ tion is done after passivation of the finished wafer and prior to cutting of the wafer into many individual chips. Depending on the electrical performance requirements of the intended use of the packaged product, deposition of the aluminum attachment layer on the back side of the wafer can be done with or without removal of any oxide layer built up on the wafer back side. Generally, and most preferably, the deposition of the aluminum attach¬ ment coating on the back side of the wafer is done after passivation of the wafer, and after any oxide surface has been removed from the back side of the wafer. Neces¬ sity for removal of any oxide layer from the back side can of course be avoided by preventing any oxide from originally occurring on the wafer back side before aluminizing.
If oxide is to be removed from the wafer back side before aluminum deposition, the removal can be accomplished after fabrication of the wafer or within the main wafer fabrication process. Removal of the oxide from the wafer back side can be done by conven¬ tional plasma, chemical or sputter etch techniques, for example. It will be appreciated that during removal of oxide after fabrication of the wafer, the circuit (front or top) side of the wafer is to be protected by use of a photoresist deposited on the top side so as to avoid any damage thereto during etch of the wafer back side.
Deposition of the aluminum attachment layer onto the back side of a wafer, from which the oxide layer may or may not have been removed, can be accom¬ plished by any suitable deposition techniques capable of depositing a thin uniform aluminum layer: for example, such as by deposition from the vapor state by evapora- tion, or by sputter (ion bombardment) deposition. If the oxide layer is to be removed by a sputter etch, the subsequent deposition of the aluminum layer may, if desired, be sputter deposited as part of the same vacuum process. Generally, the evaporation methods of deposition are preferred.
The thickness of the aluminum attachment layer deposited on the back side of the wafer will generally be at least 5,000 A thick, preferably from about 10,000 to about 30,000 A and most preferably about 15,000 A thick.
Wafers, on which an aluminum attachment layer has been deposited on the back side thereof, are then separated into individual chips for mounting onto a receiving area of a package, such as for example, onto a cavity or onto a tab of any suitable lead frame package. Attachment or mounting of the aluminum-backed chip to the receiving area of the package is by way of an eutec- tic preform material. Mounting at about 370 to about 450°C, generally at about 380 to 425°C and preferably at about 390°C, is obtained with a gold eutectic preform. However, other gold preforms such as for example, gold/ tin, gold/germanium and gold/tin/silicon preforms and the like which cause the aluminum to bond to the package may also be employed. It has been found that a gold/ silicon preform (98%/2% by weight) produces excellent bonding between the aluminum and the package. However, it is envisioned that gold/silicon preforms, wherein the weight percent of silicon is increased to 4%, 6% or the like, will provide equally satisfactory bonding.
While the receiving areas of package substrates have generally been gold, and although the aluminum bonds to such gold surfaces extremely well according to this invention, it has also been discovered that such aluminum- backed chips can be mounted to other materials which may comprise the receiving area of the package, such as for example nickel, copper, aluminum and the like, thereby eliminating the necessity for gold on the surface of the receiving area of the package.
Another advantage obtained with the aluminum- backed chips of this invention is the reduction or pre¬ vention of diffusion of gold into the back side of the silicon die. Since aluminum will be absorbing or alloy¬ ing with the eutectic materials, not as much or no gold is diffused into the back side of the silicon wafer or chip. If desired, a covering of the aluminum-backed wafer by an additional conductive barrier film layer of any suitable barrier material, such as titanium or tungsten or the like may be employed. This additional barrier layer can be deposited on the first aluminum layer, and then a second aluminum attachment layer deposited so as to cover the barrier layer for prevent¬ ing diffusion of gold into the back side of the silicon wafer. Alternatively, a conductive barrier film layer may first be deposited on the back side of the silicon wafer before deposition of the aluminum attachment layer. Prevention or substantial elimination of such undesired gold diffusion into the back side of the sili¬ con wafer is also obtained by this invention since the presence of an aluminum attachment layer on the wafer back side allows the use of a lower temperature of the gold eutectic preform at the receiving surface of the package cavity or tab during mounting of the aluminum- backed chip.
Since removal of an oxide layer from the back side of the chip prior to aluminum layer deposition is not essential, and since removal of such an oxide layer can be achieved by various etch processes mentioned here¬ inbefore, it is no longer necessary to sandblast the wafer back side to do away with the oxide layer. This elimination of the sandblasting step is especially ad¬ vantageous since the sandblasting procedure, in addition to being a dirty, contaminating process, also causes non-uniform stresses in the crystal structure of the silicon wafer itself, as well as causing damage, at times, to the circuits therein. With this invention, sandblasting is neither required nor necessary. In another embodiment of this invention, the aluminum backed circuit chips of this invention may be mounted to one another, in either back-to-back or back- to-front relationship, such as for use in sensor prod- ucts or other die - die mounted products. For example, the aluminum backed side of a first chip may be etched to a pattern to match all or a portion of the circuit on the top side of a second such chip and the etched aluminum pattern of the first chip connected to all or a portion of the circuit on the top side of the second chip by way of etched vias in the first chip. Also, the aluminum backed side of a first chip could be similarly mounted to the aluminum backed side of a second chip. Actually, attachment of the chips in front-to-back or back-to-back relationship could'be accomplished, for example, by using gold preforms, preferably a gold/silicon preform, and conventional chip attachment or by bonding with locally applied ultrasonic or thermosonic energy or by soldering using an appropriate preform.
To better describe the wafers of this inven¬ tion reference may be made to the following illustra¬ tive example.
Silicon wafers having circuits formed on the front surface thereof are fabricated according to any of the many known and varied techniques for producing same. After passivation of the wafers, the back sur¬ face of the wafers are, if desired, freed of any resid¬ ual oxide by sand blasting followed by plasma or chemi- cal etching. Thereafter, an attachment layer of alu¬ minum of a thickness of about 15,000 A is deposited on the wafer back side by sputtering using a Perkin Elmer 4400 sputter machine with an argon gas ambient at a pressure of about 7 microns, for example, while protecting the top surface (circuit) side of the wafer by any known protection techniques. The wafers are placed in the sputtering machinery with the top or cir¬ cuit side facing down, thus shielding the front side, and the wafer back side is exposed for collection of the sputtered aluminum.
Following deposition of the aluminum attachment layer and removal of any protective coating from the top surface of the wafers, the wafers are cut into individual chips, such as for example, by wafer sawing or the like. The resulting individual aluminum-backed chip is then attached to the receiving surface of a package by way of a gold eutectic preform material, such as a gold/silicon eutectic preform. For example, the individual chip is attached to the gold cavity of a sidebraze package by a 98/2 weight percent gold/silicon eutectic preform at 390°C by scrubbing the aluminum-backed chip into the gold cavity. Following the above-described steps achieves bodning attachment of the chip back side to the receiving area of the cavity over at least about 98% of the avail¬ able surface area for attachment.

Claims

What is Claimed is:
1. A wafer of circuit chips for producing an individual chip therefrom and for attachment of said chip to the receiving surface of a package comprising a substrate having a front and back surface, said substrate front surface having the circuits formed thereon, and said back surface having deposited thereon an attachment layer of aluminum for increasing attachment contact between said chip back surface and the receiving surface cf a package.
2. A wafer of circuit chips for producing an individual chip therefrom and for attachment of said chip to the receiving surface of a package comprising a substrate having a front and back surface, said substrate front surface having circuits formed thereon, and said substrate back surface having deposited thereon a con¬ ductive barrier film layer, and an outer attachment layer of aluminum thereon for increasing attachment contact between said chip back surface and the receiving surface of a package.
3. A wafer of Claim 2 wherein said substrate back surface has an aluminum layer between the substrate back surface and the conductive barrier film layer.
4. A wafer of Claim 1, 2 or 3 wherein the attach¬ ment layer of aluminum comprises a layer of aluminum of a thickness of from about 5,000 to about 30,000A.
5. A wafer of Claim 1, 2 or 3 wherein said alu¬ minum attachment layer has deposited thereon an outer gold eutectic preform layer.
6. A circuit chip for attachment to a receiving surface of a package comprising a substrate having a front and back surface, said substrate front surface having a circuit formed thereon and said substrate back surface having deposited thereon an attachment layer of aluminum for increasing attachment contact between said chip back surface and the receiving surface of a package.
7. A circuit chip of Claim 6 wherein the attach¬ ment layer of aluminum comprises a layer of aluminum o of a thickness of from about 5,000 to about 30,000 A.
8. A circuit chip of Claim 6 wherein said aluminum attachment layer has deposited thereon an outer gold eutectic preform layer.
9. A packaged circuit having a chip receiving surface thereon, said chip receiving surface being in bonding contact with the aluminum attachment layer of a chip of Claim 6.
10. A packaged circuit of Claim 9 wherein the bonding contact between the aluminum attachment layer and the chip receiving surface of the package is by way of gold eutectic preform layer.
11. A packaged circuit of Claim 10 wherein the gold eutectic preform layer is selected from the group con¬ sisting of gold/silicon, gold/germanium, gold/tin and gold/tin/silicon preforms.
12. A packaged circuit of Claim 11 wherein said gold eutectic preform is gold/silicon preform.
13. A packaged circuit of Claim 11 wherein said gold eutectic preform is a gold/tin preform.
14. A packaged circuit of Claim 11 wherein said gold eutectic preform is a gold/germanium preform.
15. A packaged circuit of Claim 11 wherein said gold eutectic preform is a gold/tin/silicon preform.
16. A packaged integrated circuit of Claim 12 wherein the gold/silicon eutectic preform layer comprises 98 weight percent gold and about 2 weight percent silicon.
17. A chip-to-chip mounted product comprising a first circuit chip having a front and a back surface, said front surface having circuits formed thereon and said back surface having an aluminum attachment layer thereon, said aluminum attachment layer of said first chip being attached by an eutectic preform to at least part of the surface of a second circuit chip having a front surface having circuits formed thereon and a back surface having an aluminum attachment layer thereon.
EP87902270A 1986-03-19 1987-03-10 Aluminum-backed wafer and chip Withdrawn EP0263146A1 (en)

Applications Claiming Priority (2)

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US84128286A 1986-03-19 1986-03-19
US841282 1986-03-19

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DE4105592A1 (en) * 1991-02-22 1992-08-27 Messerschmitt Boelkow Blohm METHOD FOR THE AREA CONNECTING OF SILICON SEMICONDUCTOR DISC
US5693574A (en) * 1991-02-22 1997-12-02 Deutsche Aerospace Ag Process for the laminar joining of silicon semiconductor slices

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