JPS6223135A - Semiconductor device - Google Patents

Abstract

PURPOSE:To protect insulating film from cracks by rendering the bond strength at the corners and periphery of a substrate greater than the thermal stress in a resin moulding process by a method wherein the width of Al wirings at such locations in defined to be not wider than 25mum. CONSTITUTION:The widths W1, W2 of an Al wiring 3 formed along the periphery and at the corners of a chip 1 are rendered so narrow that they may not undergo detrimental effects produced by thermal stress in a resin molding process. For example, the with W1 of the Al wiring 3 along the chip periphery is made to be not wider than 25mum. Again, the with W2 (as measured along the direction from a corner to the chip center) of the Al wiring 3 is made to be approximately 50mum wide. With the wiring width being set as such, there will be no poor performance attributable to cracks, which leads to the realization of semiconductor devices with their reliability enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique for preventing passivation cracks caused by aluminum wiring in semiconductor devices, particularly resin-sealed semiconductor devices.

[Background technology]

In a grease-sealed bipolar IC, one A7 (aluminum) wiring is installed along the periphery of the semiconductor substrate (chip).
It is formed in a layer or multi-layer, and a sinusoid is formed between and on the wiring layer.
Structures in which an inorganic insulating film is formed, such as , are known. NIKKEI ELECTRO published by Nikkei Maguro Hill Co., Ltd.
NIC3MICRODEVICE 1983.8.2
2. p125) In such an IC structure, the surface and bottom of the semiconductor chip are covered with an inorganic insulating film due to thermal stress during resin molding. Cracks occurred in a part of the fM film, especially in 2I? It has been found that, in the case of the jiAJ arrangement, leakage occurs between the A and B wiring layers that match the pattern, causing defects in the electrical characteristics of the IC.

In such a rack, shrinkage stress is applied to the surface of the semiconductor substrate due to the difference in thermal expansion coefficient between the Si semiconductor of the chip, the inorganic insulating film (SiOl), and the sealing resin, making the A2 wiring softer than the inorganic insulating film. It is thought that cracks occur in the insulating film in contact with the deformation of the insulating film.

According to the results of a heat stress test carried out by the present inventor on a resin-molded semiconductor device having inorganic two-layer A2 wiring, it was found that the above-mentioned racks occur particularly frequently at the corners of the chip and around the chip. It's here.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and its purpose is to reduce the occurrence of cracks due to stress during resin molding in semiconductor devices such as ICs, and to
The reason is that the fP property is completely defective.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, there are people on the board! In a resin-sealed semiconductor device having a wiring layer and an inorganic insulating film on or between the layers, the width of the two wirings at the corner and peripheral portions of the substrate is 25 mm.
By specifying the thickness within μm, the adhesive strength of the insulating film at this portion is made stronger than the thermal stress during resin molding, thereby reducing the occurrence of cracks in the insulating film.

[Embodiment 1] FIGS. 1 and 2 show an embodiment of the present invention, in which FIG. 1 is a partial plan view of a semiconductor device with a single-layer A-e wiring structure, and FIG. It is a sectional view taken along the line A in FIG. 1.

1 is a Si semiconductor substrate (chip), 2 is a surface oxide (Si
3 is an A7 aluminum film, 4 is a surface protection insulating film made of CVD (fi phase chemical deposition) and PSG (phosphosilicon oxide glass). The widths W, , W of the AA wiring 3 formed in the periphery and corner portions of the chip 10 shown in the figure are made narrow enough to be unaffected by thermal stress during resin molding.

For example, the width WI of the wiring located along the chip periphery is set to about 25 μm or less. Also, the width of the wiring near the corner (curved in the direction connecting the corner and the center)
W is approximately 50 μm.

[Actions and effects of the present invention]

According to the present invention as described in the examples, effects can be obtained for the following reasons. When the high temperature melting resin polymer shrinks upon cooling during resin molding, the coefficient of thermal expansion of the resin is lower than that of the Si semiconductor substrate, 8102, etc. is larger than the thermally expandable group of the inorganic insulating film.
Stress σ is generated in the direction shown by the arrow in the figure.

The distribution state of this stress σ on the chip plane (Fig. 3) is small at the chip center 0 as shown in Fig. 4;
Experiments have revealed that the size increases toward the periphery and corners of the chip.

In the same figure, the relationship between the width of the wiring A and its position on the chip, which can handle such stress and not cause cracks in the insulation film, is shown by lines A, B, C, etc., which are orthogonal to the stress curve.
It is indicated by...

The range in which the width of the A wiring in the peripheral portion and corner portion is reduced is determined, for example, as follows.

When the dimensions on the chip plane shown in FIG. 3 are length X (for example, 5sn) and width y (for example, 5tl), there is a warpage at the periphery of 1/10j of the chip dimension, that is, -xI.
By setting the A4 wiring width W, ≦25 p m Wt≦50μ7FL, within the width range of Y (0,5111) and 2/10xy (1,0xy+) at the corner part, stress can be reduced. On the other hand, the wiring deformation and movement prevention strength of the inorganic insulating film covering the A wiring is relatively thick (
As a result, the occurrence of cracks is reduced. Aff
The width of the l wiring can be easily determined by changing the mask pattern.

By defining the wiring width in this manner, characteristic defects caused by cracks are eliminated, and high reliability of the semiconductor device can be obtained.

[Embodiment 2] FIGS. 5 and 6 show another embodiment of the present invention, in which FIG. 5 is a partial plan view of a semiconductor device with a two-layer AJ3 wiring structure, and FIG. It is a BB sectional view in FIG. 5. 1 is a Si substrate (chip), 2 is a 5ift film, 3 is a first
Layer A2 wiring, 5 is an interlayer insulating film made of PSG, 6 is a second layer
Layer A4-8i wiring, 7 is a protective insulating film.

In this Example 2, the AA wirings 3 and 6 are both located at the chip periphery, and by forming the wiring width WI to be 25 μm or less, the influence of stress during resin molding is minimized and the occurrence of cracks is prevented. .

[Application field]

The present invention is inorganic insulation m (PSG, CV D-81
It can be applied to general resin-sealed semiconductor devices having a wiring structure of two layers or two or more layers using ohS+104) as a wiring protection film or a wiring interlayer film.

[Brief explanation of the drawing]

1 and 2 show one embodiment of the present invention, FIG. 1 is a partial plan view of a semiconductor chip, and FIG. 2 is an A--
It is an A sectional view. Figure 3 is an overall plan view of the chip, Figure 4 is A! 5 is a curve diagram showing the relationship between wiring position, wiring width, and stress. FIGS. 5 and 6 show another embodiment of the present invention, and FIG. 5 is a partial plan view of a semiconductor chip, and FIG. FIG. 6 is a BB cross-sectional view in FIG. 5. 1...Si semiconductor chip, 2...Surface SiQ, film,
3-@1 layer AJ wiring, 4-P S G film, 5 ・P S
Glabellar membrane consisting of G, 6... Second layer A wiring, 7...
・Surface protection insulation film. Agent: Patent Attorney Katsuo Ogawa, 1st
figure,? Figure 2 Figure 5 Figure 6

Claims (1)

[Claims] 1. A resin-sealed semiconductor device in which wiring made of one or more layers of aluminum film is formed along the periphery of a semiconductor substrate, and an inorganic insulating film is formed on or between these wirings. A semiconductor device characterized in that the width of the wiring at the periphery and near the corners of the substrate is formed so thin that it is not affected by thermal stress during resin molding. 2. The semiconductor device according to claim 1, wherein the peripheral portion has a width of 1/10 of the substrate dimension. 3. The semiconductor device according to claim 1 or 2, wherein the width of the wiring in the peripheral portion is approximately 25 μm or less.