JPS60145628A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60145628A JPS60145628A JP59002157A JP215784A JPS60145628A JP S60145628 A JPS60145628 A JP S60145628A JP 59002157 A JP59002157 A JP 59002157A JP 215784 A JP215784 A JP 215784A JP S60145628 A JPS60145628 A JP S60145628A
- Authority
- JP
- Japan
- Prior art keywords
- film
- protective film
- silicon oxide
- plasma
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、特に表面保護膜の構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to the structure of a surface protective film.
半導体装置の表面保護膜は金属配線の断線や短絡を防止
するためあるいは外部汚染から半導体装置を保護するた
めに用いられる。A surface protective film for a semiconductor device is used to prevent disconnection or short circuit of metal wiring or to protect the semiconductor device from external contamination.
従来、表面保護膜はＣＶＤ法によって形成されたシリコ
ン酸化膜あるいはリンガラス層が一般的に用いられてい
る。しかしながら、シリコン酸化膜もリンガラス層膜も
機械的強度が弱く、かつ、段差被覆性が悪く、また膜の
緻密性も充分でない。Conventionally, a silicon oxide film or a phosphorus glass layer formed by a CVD method has generally been used as a surface protective film. However, both the silicon oxide film and the phosphorous glass layer film have weak mechanical strength, poor step coverage, and insufficient film density.
このため、配線の傷防止効果や外部からの水分等の浸入
によって配線が腐食したシ、電気特性が変動したりする
耐湿性の面において満足出来るものではなかった。For this reason, it has not been satisfactory in terms of the effect of preventing scratches on the wiring and the resistance to moisture, in which the wiring is corroded due to the intrusion of moisture from the outside, and the electrical characteristics are changed.
そこで、最近プラズマＣＶＤ法によって形成さするシリ
コン窒化膜（以下、プラズマ窒化膜と呼ぶ）が用いられ
る様になった。プラズマ窒化膜は機械的強度、膜の緻密
性および段差被膜性においてはシリコン酸化膜やリンガ
ラス層より優れ２いる。しかし、プラズマ窒化膜は成長
時のプラズマタ゛メージや応力さらに膜中に含まねる水
素等の影響によυ、半導体装置の電気的安定性に悪影響
をおよぼす場合がある。特にアルミニウム等の金属配線
にじかにプラズマ窒化膜を成長するとその電気的安定性
を着るしくそこなうことがある。Therefore, recently, a silicon nitride film (hereinafter referred to as a plasma nitride film) formed by plasma CVD has come into use. Plasma nitride films are superior to silicon oxide films and phosphorous glass layers in terms of mechanical strength, film density, and step coverage. However, the plasma nitride film may have an adverse effect on the electrical stability of the semiconductor device due to the influence of plasma image and stress during growth, as well as hydrogen contained in the film. In particular, if a plasma nitride film is grown directly on metal wiring such as aluminum, its electrical stability may deteriorate.
そこで、通鹿、表面保護膜としては第１図に示す様にシ
リコン酸化膜あるいはリンガラス層４とプラズマ窒化膜
５の２１−で用いられることが多い。Therefore, as shown in FIG. 1, a silicon oxide film or a phosphorus glass layer 4 and a plasma nitride film 5 (21-) are often used as surface protective films.
なお、１はシリコン基体、２はフィールド酸化膜、３は
アルミニウムでポンディングパッドである。Note that 1 is a silicon substrate, 2 is a field oxide film, and 3 is an aluminum bonding pad.
第１図において、表面保護膜はＨ形成後、ボンデンプ配
線のためパッド部の開孔Ａおよびチップ分割のだめのス
クライブ線の開孔Ｂが行なわれ、このため、各開孔部Ａ
、Ｂにおいては、下地のシリコン酸化膜あるいはリンガ
ラス層４が露出することになる。この結果、この部分へ
の外部からの水分等の浸入によって、耐湿性がそこなわ
れてしまう。また、開孔工程において、プラズマ窒化膜
５とシリコン酸化膜またはリンガラス１信４を同時に開
孔するため、エツチング不足による膜残りやシリコン酸
化′またはリンガラス層４の′アングーカットが起こり
、ボンディング不着、膜ノ・ガしていっ問題が発生する
。In FIG. 1, after H is formed on the surface protective film, holes A in the pad area for bond wiring and holes B for scribe lines for chip division are made.
, B, the underlying silicon oxide film or phosphorus glass layer 4 is exposed. As a result, moisture resistance is impaired due to moisture entering this portion from the outside. In addition, in the hole-opening process, since the plasma nitride film 5 and the silicon oxide film or the phosphor glass layer 4 are simultaneously opened, a film may remain due to insufficient etching, or the silicon oxide layer 4 or the phosphorus glass layer 4 may be uncut. Problems occur due to bonding failure and film damage.
本発明の目的は、耐湿性に優れた表向保ｄ騙膜を有する
半導体装置ケ提供するにある。An object of the present invention is to provide a semiconductor device having a surface insulation film with excellent moisture resistance.
本発明は半導体装置の表面保護膜として、シリコン酸化
膜またはリンカラス層とプラズマ窒化膜との２層構造を
有し、さらに表面保護膜の開孔部において、シリコン酸
化膜祉たはリンガラス層が露出しない様にプラズマ窒化
膜で覆う様にしたことを％徴とする。The present invention has a two-layer structure of a silicon oxide film or a phosphor glass layer and a plasma nitride film as a surface protection film for a semiconductor device, and furthermore, the silicon oxide film or phosphor glass layer is formed in the opening of the surface protection film. The percentage indicates that it is covered with a plasma nitride film so that it is not exposed.
次に、図面ｋｍＩｍＬ、てこの発明による半導体装置の
実施例を詳、別に説明する。Next, an embodiment of the semiconductor device according to the present invention will be described in detail with reference to the drawing kmImL.
第２図は本発明の一実施例ケ示す。シリコン基板１上の
フィールド酸化膜２上にＡｅ配慄３が形成される。この
Ａ ７配線や他の部分を保ｔΦする表面保護膜として、
まずシリコン酸化膜４を例えば５０００Ｘの厚さにＣＶ
ＩＪ法にて形成する。仄いて゛、ポンディングパッド部
開孔Ａおよびスクライブ線開孔１３ヲ公知の方法にて形
成する。しかる後、プラズマＣＶ Ｄ法によシプラズマ
蟹化膜５を例えば約１μｆＴｌの厚さに全面に形成する
。次に、ポンディングパッド部Ａおよびスクライブ線Ｂ
になるシリコン窒化膜にプラズマエツチング法にて開孔
する。この時、シリコン酸化膜４が各開孔部にて露出し
ない様に最初の孔よシ内側に開孔する。この様にして表
面保護膜を有する半導体装置が得られる。FIG. 2 shows one embodiment of the invention. An Ae distribution 3 is formed on a field oxide film 2 on a silicon substrate 1. As a surface protective film to protect this A7 wiring and other parts,
First, CVD the silicon oxide film 4 to a thickness of, for example, 5000X.
Formed by IJ method. Additionally, the bonding pad hole A and the scribe line hole 13 are formed by a known method. Thereafter, a plasma-cured film 5 is formed over the entire surface by plasma CVD to a thickness of, for example, about 1 μfTl. Next, bonding pad part A and scribe line B
A hole is formed in the silicon nitride film to be etched using a plasma etching method. At this time, holes are opened inside the first hole so that the silicon oxide film 4 is not exposed at each hole. In this way, a semiconductor device having a surface protective film is obtained.
以上述べた様に本発明によれば、ポンディングパッドお
よびスクライブ線を除いて半導体装置の表面は完全にプ
ラズマ窒化膜で覆われているので耐湿性にすぐれた半導
体装置が得られる。さらに機械的強度にも強いのは当然
である。また、開孔時の膜残りヤ、下地シリコン酸化膜
のアンダーカット等の問題もエツチングを別々にそれぞ
れ確実に行なうことが出来るのでボンディング不着や膜
ハガレの問題も改善できる。As described above, according to the present invention, the surface of the semiconductor device except for the bonding pads and scribe lines is completely covered with the plasma nitride film, so that a semiconductor device with excellent moisture resistance can be obtained. Naturally, it also has strong mechanical strength. Further, since the etching can be performed separately and reliably to deal with problems such as film residue when opening holes and undercuts in the underlying silicon oxide film, problems such as bonding failure and film peeling can also be alleviated.
第１図は従来の半導体装置を示す断面図、第２図は本発
明の一実施例を示す断面図である。
１・・・・・・シリコン基板、２・・・・・・フィール
ド酸化膜、３・・・・・・ＡＡ配粉、４・・・・・・シ
リコン酸化膜、５・・・・・・プラズマ窒化膜、Ａ・・
・・・・ボンティングパッド部、Ｂ・・・・・・スクラ
イブ線。
１、FIG. 1 is a sectional view showing a conventional semiconductor device, and FIG. 2 is a sectional view showing an embodiment of the present invention. 1...Silicon substrate, 2...Field oxide film, 3...AA powder distribution, 4...Silicon oxide film, 5... Plasma nitride film, A...
...Bonting pad part, B...Scribe line. 1,
Claims (1)
線導体層が形成された半導体チップの該配線導体層を保
護する表面保護膜がシリコン酸化膜またはリンガラス層
から成る第１の保護膜とシリコン窒化膜から成る第２の
保護膜との２層構造でなり、この表面保護膜の開孔部に
２いて、前記第１の保護膜を覆うごとく前記第２の保護
膜を形成したことを特徴とする半導体装置。A surface protective film for protecting the wiring conductor layer of a semiconductor chip in which a plurality of element regions are formed and a wiring conductor layer connected to a predetermined element region is formed is a first protective film made of a silicon oxide film or a phosphorus glass layer. It has a two-layer structure with a second protective film made of a silicon nitride film, and the second protective film is formed in the opening of the surface protective film so as to cover the first protective film. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59002157A JPS60145628A (en) | 1984-01-10 | 1984-01-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59002157A JPS60145628A (en) | 1984-01-10 | 1984-01-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60145628A true JPS60145628A (en) | 1985-08-01 |
Family
ID=11521515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59002157A Pending JPS60145628A (en) | 1984-01-10 | 1984-01-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60145628A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS649382A (en) * | 1987-06-30 | 1989-01-12 | Victor Company Of Japan | Magnetic sensor |
| US5294295A (en) * | 1991-10-31 | 1994-03-15 | Vlsi Technology, Inc. | Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges |
| US6520189B1 (en) | 1986-09-09 | 2003-02-18 | Semiconductor Energy Laboratory Co., Ltd. | CVD apparatus |
| JP2007035941A (en) * | 2005-07-27 | 2007-02-08 | Ricoh Co Ltd | Method for manufacturing semiconductor device |
-
1984
- 1984-01-10 JP JP59002157A patent/JPS60145628A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6520189B1 (en) | 1986-09-09 | 2003-02-18 | Semiconductor Energy Laboratory Co., Ltd. | CVD apparatus |
| JPS649382A (en) * | 1987-06-30 | 1989-01-12 | Victor Company Of Japan | Magnetic sensor |
| US5294295A (en) * | 1991-10-31 | 1994-03-15 | Vlsi Technology, Inc. | Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges |
| JP2007035941A (en) * | 2005-07-27 | 2007-02-08 | Ricoh Co Ltd | Method for manufacturing semiconductor device |
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