KR940007290B1 - Manufacturing method of wirebonding pad - Google Patents
Manufacturing method of wirebonding pad Download PDFInfo
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- KR940007290B1 KR940007290B1 KR1019910022980A KR910022980A KR940007290B1 KR 940007290 B1 KR940007290 B1 KR 940007290B1 KR 1019910022980 A KR1019910022980 A KR 1019910022980A KR 910022980 A KR910022980 A KR 910022980A KR 940007290 B1 KR940007290 B1 KR 940007290B1
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- polyimide
- bonding pad
- wire bonding
- protective film
- photosensitive polyimide
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- 238000004519 manufacturing process Methods 0.000 title description 3
- 239000004642 Polyimide Substances 0.000 claims abstract description 47
- 229920001721 polyimide Polymers 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 4
- 230000001681 protective effect Effects 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 239000011241 protective layer Substances 0.000 abstract 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000002161 passivation Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- LBDSXVIYZYSRII-IGMARMGPSA-N alpha-particle Chemical compound [4He+2] LBDSXVIYZYSRII-IGMARMGPSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- QEVHRUUCFGRFIF-MDEJGZGSSA-N reserpine Chemical compound O([C@H]1[C@@H]([C@H]([C@H]2C[C@@H]3C4=C(C5=CC=C(OC)C=C5N4)CCN3C[C@H]2C1)C(=O)OC)OC)C(=O)C1=CC(OC)=C(OC)C(OC)=C1 QEVHRUUCFGRFIF-MDEJGZGSSA-N 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도는 집적회로칩을 나타낸 평면도.1 is a plan view showing an integrated circuit chip.
제2a도 내지 제2c도는 제1도의 a-a' 부분을 절단한 종래의 와이어 본딩 패드 형성단계를 나타낸 단면도2a to 2c are cross-sectional views showing a conventional wire bonding pad forming step of cutting the a-a 'portion of FIG.
제3a도 내지 제3d도는 제1도의 a-a' 부분을 절단한 본 발명의 실시예에 의한 와이어 본딩 패드 형성단계를 나타낸 단면도.3A to 3D are cross-sectional views illustrating a step of forming a wire bonding pad according to an embodiment of the present invention by cutting a-a 'portion of FIG. 1.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 집적회로칩 2 : 집적회로부1: integrated circuit chip 2: integrated circuit unit
3 : 와이어본딩패드 3A : 와이어본딩패드부3: wire bonding pad 3A: wire bonding pad portion
4 : 실리콘기판 5 : 금속층4 silicon substrate 5 metal layer
5A : 금속배선 6 : 보호막5A metal wiring 6: protective film
7 : 폴리이미드층 7A : 폴리이미드패턴7: polyimide layer 7A: polyimide pattern
8 : 절연층 9 : 폴리이미드잔여물8: insulation layer 9: polyimide residue
10 : 패드영역10: pad area
본 발명은 와이어 본딩 패드(Wire Bonding Pad) 형성방법에 관한 것으로, 특히 반도체 제조공정에 집적회로 칩상에 와이어 본딩 패드 형성공정중 폴리이미드 마스크(Polyimide Mask) 형성시 패드 형성부분에 폴리이미드 잔여물이 남는 것을 제거하기 위하여 O2플라즈마 공정을 추가하는 와이어 본딩 패드 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a wire bonding pad. In particular, a polyimide residue is formed on a pad forming portion when a polyimide mask is formed during a wire bonding pad forming process on an integrated circuit chip in a semiconductor manufacturing process. A method of forming a wire bonding pad is added which adds an O 2 plasma process to remove the residue.
일반적으로 반도체 소자의 칩 제조공정에서 설계된 단위셀을 배열하고 연결하기 위해 실리콘 기판의 예정된 부분에 불순물의 선택적 도입공정, 절연층과 도전층을 적층하는 적층공정 및 패턴마스크 공정등이 차례로 실행되어 각각의 칩에 집적회로가 형성된다.Generally, in order to arrange and connect unit cells designed in a chip manufacturing process of a semiconductor device, selective introduction of impurities into a predetermined portion of a silicon substrate, a lamination process of laminating an insulating layer and a conductive layer, and a pattern mask process are performed in this order. An integrated circuit is formed on the chip of.
이와 같이 하여 형성된 집적회로 칩은 조립공정으로 보내져서 칩절단, 칩부착, 와이어 본딩, 몰드, 포밍, 트립공정등의 순서로 진행하여 각각의 IC를 형성한다.The integrated circuit chips thus formed are sent to an assembly process to proceed with chip cutting, chip attachment, wire bonding, mold, forming, trip process, and the like to form respective ICs.
본 발명에서는 조립공정중 와이어를 칩상부의 패드에 본딩하는데 사용되는 와이어 본딩 패드를 형성하는 방법을 설명하고자 한다.In the present invention, a method of forming a wire bonding pad used to bond the wire to the pad on the chip during the assembly process will be described.
종래의 와이어 본딩 패드 형성방법을 제1 및 제2a도 내지 제2c도를 참조하여 설명하면 다음과 같다.A conventional method of forming a wire bonding pad will be described with reference to FIGS. 1 and 2A through 2C.
제1도는 웨이퍼에서 절단된 집적회로 칩(1)을 도시한 평면도로서, 집적회로 칩(1)의 중앙부에는 단위셀이 배열되어 회로를 구성한 집적회로부(2)가 형성되고, 집적회로부(2)의 주변부를 따라 일정부분에 다수의 와이어 본딩 패드(3)가 형성됨을 개략적으로 도시한 것이다.FIG. 1 is a plan view showing an integrated circuit chip 1 cut from a wafer. An integrated circuit unit 2 including unit cells is arranged at a central portion of the integrated circuit chip 1 to form a circuit. It is schematically shown that a plurality of wire bonding pads 3 are formed at a portion along the periphery of the substrate.
제2a도 내지 제2c도는 종래 기술에 의해 제1도의 a-a'를 따라 절단하여 와이어 본딩 패드(3)를 형성하는 단계를 도시한 단면도이다.2A to 2C are cross-sectional views showing a step of forming the wire bonding pad 3 by cutting along a-a 'in FIG. 1 according to the prior art.
제2a도는 실리콘 기판(4)의 절연층(8) 상부에 금속층(5)(예를들면 알루미늄층)을 증착한 다음, 마스크패턴공정으로 금속배선(5A)을 길게 형성한 후, 전반적으로 보호막(6)을 증착 형성한 상태를 도시한 것으로, 상기 보호막(6)은 제품의 품질을 향상시키고 습기에 의한 제품의 신뢰도 저하 및 α-입자(α-Particle)에 의한 소프트 에어를 방지하기 위하여 산화막 또는 질화막으로 증착한 것이다.FIG. 2A shows a metal layer 5 (for example, an aluminum layer) is deposited on the insulating layer 8 of the silicon substrate 4, and then the metal wiring 5A is formed long by a mask pattern process. The protective film 6 is formed by depositing and forming an oxide film in order to improve the quality of the product, to reduce the reliability of the product due to moisture, and to prevent soft air due to the α-Particle. Or a nitride film.
제2b도는 상기 보호막(6) 상부에 와이어 본딩 패드 마스크를 사용하여 감광막 마스크 패턴을 형성하고(도시안됨), 노출되는 보호막(6)을 식각하여 금속배선(5A)의 예정된 영역이 노출된 와이어 본딩 패드부(3A)를 형성한 다음, 상기 감광막 마스크 패턴을 제거한 상태의 단면도이다.FIG. 2B illustrates a wire bonding pad mask formed on the passivation layer 6 to form a photoresist mask pattern (not shown), and etching the exposed passivation layer 6 to expose a predetermined area of the metal line 5A. After forming the pad part 3A, it is sectional drawing of the state which removed the said photosensitive film mask pattern.
제2c도는 와이어 본딩 패드부(3A)를 포함한 전체구조 상부에 감광성 폴리이미드층(7)을 코팅한 후, 와이어 본딩 패드부(3A)를 노출시키기 위해 마스크를 이용하여 광을 노광시킨 다음, 상기 감광성 폴리이미드층(7)을 현상액으로 현상하여 와이어 본딩 패드부(3A)를 노출시킨 감광성 폴리이미드 패턴(7A)를 형성하고,이것을 고온에서 경화(Curing)시킨 상태를 도시한 것으로, 감광성 폴리이미드층(7)을 경화시키면 α-입자에 의한 소프트 에러 방지 보호막으로 작용하게 된다.FIG. 2C illustrates that the photosensitive polyimide layer 7 is coated on the entire structure including the wire bonding pad portion 3A, and then light is exposed using a mask to expose the wire bonding pad portion 3A. The photosensitive polyimide layer 7 was developed with a developer to form a photosensitive polyimide pattern 7A exposing the wire bonding pad portion 3A, and the photosensitive polyimide layer 7 was cured at a high temperature. Curing layer 7 acts as a soft error prevention protective film by α-particles.
그러나, 상기한 종래기술은 상기의 감광성 폴리이미드층(7)을 현상하여 폴리이미드 패턴(7A)을 형성할때, 와이어 본딩 패드부(3A)에 감광성 폴리이미드 잔여물(9)이 남게 되어 후공정의 프로브 테스트시나 와아어 본딩 공정시 전기적인 접촉이 불량하게 하는 문제점을 야기시킨다.However, in the above-described conventional technique, when the photosensitive polyimide layer 7 is developed to form the polyimide pattern 7A, the photosensitive polyimide residue 9 remains in the wire bonding pad portion 3A. This leads to a problem of poor electrical contact during the probe test of the process or during the wafer bonding process.
따라서, 상기한 문제점을 해결하기 위한 본 발명은 와이어 본딩 패드 형성공정중 경화공정을 행한 후, 감광성 폴리이미드 성분이 고온의 O2에 의해 산화되는 현상을 이용하여 와이어 본딩 패드부에 잔존하는 절연막을 후속 공정인 폴리이미드 에치(Palyimide Etch)에 의해 제거시키므로써 와이어 본딩 패드와 외부 단자의 전기적 접촉이 양호하게 되어 수율이 안정되고 제품 특성을 개선시킬 수 있는 와이어 본딩 패드 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention provides an insulating film remaining in the wire bonding pad part by using a phenomenon in which the photosensitive polyimide component is oxidized by high temperature O 2 after the curing step in the wire bonding pad forming step. The purpose of the present invention is to provide a method for forming a wire bonding pad which can be improved by improving the product properties by providing good electrical contact between the wire bonding pad and the external terminal by removing the polyimide etch. have.
이리한 목적을 달성하기 위한 본 발명 실시예에 의하면 실리콘 기판상에 금속배선을 형성한 집적회로 칩상에 전반적으로 보호막을 증착한 후, 상기 보호막을 예정부분 식각하여 금속배선을 노출시킨 다음, 보호막을 포함하는 전체구조 상부에 전반적으로 감광성 폴리이미드를 코팅하는 단계와, 와이어 본딩 패드가 형성될 부분의 감광성 폴리이미드를 노광시키고, 노광된 폴리이미드를 현상액으로 현상하여 금속배선 상부가 노출되는 와이어 본딩 패드를 형성하는 단계와, 상기 감광성 폴리이미드를 고온에서 경화시키는 단계로 이루어지는 와이어 본딩 패드 형성방법에 있어서, 폴리이미드를 현상한 후에도 와이어 본딩 패드부에 남아 있는폴리이미드 잔여물을 제거하기 위하여, 상기 감광성 폴리이미드의 경화공정후 O2플라즈마로 10 내지 60초간 폴리이미드 에치공정을 실시하는 것을 특징으로 한다.According to an exemplary embodiment of the present invention for achieving the above object, after depositing a protective film on an integrated circuit chip on which a metal wiring is formed on a silicon substrate, the protective film is partially etched to expose the metal wiring, and then the protective film is exposed. Coating the photosensitive polyimide on the entire structure including the whole, and exposing the photosensitive polyimide of the portion where the wire bonding pad is to be formed, and developing the exposed polyimide with a developer to expose the upper portion of the metal wiring. In the wire bonding pad forming method comprising the step of forming a; and curing the photosensitive polyimide at a high temperature, in order to remove the polyimide residue remaining in the wire bonding pad portion even after the polyimide is developed, Pole for 10 to 60 seconds with O 2 plasma after curing process of polyimide A liimide etch process is performed.
이하 본 발명을 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, the present invention will be described with reference to the accompanying drawings.
제3a도 내지 제3d도는 제1도의 a-a 부분을 절단하여 본 발명의 실시예에 의한 와이어 본딩 패드 형성단계를 나타낸 단면도이다.3A to 3D are cross-sectional views illustrating a wire bonding pad forming step according to an embodiment of the present invention by cutting a-a portion of FIG. 1.
제3a도는 제2a도와 같이 실리콘 기판(4)상에 금속층(예를들어, 알루미늄)(5)을 증착하고 마스크 패턴공정으로 금속배선(5A)을 형성한 다음, 전반적으로 보호막(6)을 형성한 단면도이다.FIG. 3A shows a metal layer 5 (e.g., aluminum) 5 deposited on the silicon substrate 4 as shown in FIG. 2A, the metal wiring 5A is formed by a mask pattern process, and then the protective film 6 is generally formed. One cross section.
제3b도는 제2b도와 같이 상기 보호막(6) 상부에 와이어 본딩 패드 마스크를 사용하여 감광막 패턴을 형성하고(도시안됨), 감광막 패턴 하부의 노출되는 보호막(6)을 식각하여 금속배선(5A)의 예정된 영역이 노출된 와이어 본딩 패드부(3A)를 형성한 다음, 상기 감광막 패턴을 제거한 상태의 단면도로서, 상기 감광막은 두께 3 내지 4μm인 노볼락 수지 (Novolac Resine) 계통의 감광성 물질을 이용하며, 보호막(6)은 CF4+O2플라즈마에서 5 내지 10분 식각한다.3B illustrates a photoresist pattern (not shown) using a wire bonding pad mask on the passivation layer 6 as illustrated in FIG. 2B, and the exposed passivation layer 6 under the photoresist layer pattern is etched to form a metal wiring 5A. After forming the wire bonding pad portion 3A exposing a predetermined area, the cross-sectional view of the photoresist pattern is removed, wherein the photoresist uses a photosensitive material of Novolac Resine system having a thickness of 3 to 4 μm. The protective film 6 is etched for 5 to 10 minutes in a CF 4 + O 2 plasma.
제3c도는 제2c도와 같이 와이어 본딩 패드부(3A)를 포함한 전체구조 상부에 감광성 폴리이미드층(7)을 코팅한 후, 와이어 본딩 패드부(3A)를 노출시키기 위해 마스크를 이용하여 광을 노광시킨 다음, 노광된 감광성 폴리이미드층(7)을 현상액으로 현상하여 와이어 본딩 패드부(3A)를 노출시킨 감광성 폴리이미드 패턴(7A)을 형성하고, 이것을 고온에서 경화(Curing)시킨 상태를 도시한 것으로, 상기 감광성 폴리이미드층(7)은 스트레스 완화(Stress Buffer)의 역활을 위해 스핀 코팅(Spin Coating) 방식으로 코팅 두께는 5 내지15μm로 코팅하고, 상기 경화공정은 300 내지 400℃의 고온에서 30 내지 60분 경화하여 감광성 물질을 폴리이미드화시켜 보호막(6)과 더불어 보호막 역활을 한다.FIG. 3C shows the photosensitive polyimide layer 7 on the entire structure including the wire bonding pad portion 3A as shown in FIG. 2C, and then exposes light using a mask to expose the wire bonding pad portion 3A. Next, the exposed photosensitive polyimide layer 7 was developed with a developer to form a photosensitive polyimide pattern 7A exposing the wire bonding pad portion 3A, and the state of being cured at high temperature. The photosensitive polyimide layer 7 may be coated with a spin thickness of 5 to 15 μm in a spin coating method to act as a stress buffer, and the curing process may be performed at a high temperature of 300 to 400 ° C. The film is cured for 30 to 60 minutes to polyimide the photosensitive material to act as a protective film together with the protective film 6.
여기서 주지할 것은 제3c도 공정후 종래기술과 같이 와이어 본딩 패드부(3A)에 감광성 폴리이미드 잔여물(6)이 남는다는 점이다.Note that after the process of FIG. 3C, the photosensitive polyimide residue 6 remains in the wire bonding pad portion 3A as in the prior art.
제3d도는 상기 보호막(6)과 감광성 폴리이미드 패턴(7A)을 마스크층으로 하여 와이어 본딩 패드부(3A)에 남아 있는 폴리이미드 잔여물(9)을 폴리이미드 에치 공정으로 식각한 상태를 도시한 것으로, 상기 폴리이미드 에치공정은 O2플라즈마로 10 내지 60초간 실시한다. 이때, 상기 감광성 폴리이미드 패턴(7A)의 표면에도 소정두께 에치된다.3D illustrates a state in which the polyimide residue 9 remaining in the wire bonding pad portion 3A is etched by the polyimide etch process using the protective film 6 and the photosensitive polyimide pattern 7A as a mask layer. The polyimide etch step is performed for 10 to 60 seconds in an O 2 plasma. At this time, a predetermined thickness is also etched on the surface of the photosensitive polyimide pattern 7A.
상기한 바에 의거한 본 발명 실시예는 경화공정 후 추가공정의 O2플라즈마 에치공정을 10 내지 60초간실시하여 와이어 본딩 패드부에 남아 있는 폴리이미드 잔여물을 제거하므로써, 와이어 본딩 패드와 외부 단자의 전기적 접촉이 양호하게 되어 소자의 특성 및 수율을 향상시킬 수 있다.The embodiment of the present invention based on the above is performed by removing the polyimide residue remaining in the wire bonding pad portion by performing the O 2 plasma etch process of the additional process after the curing process for 10 to 60 seconds, thereby removing the wire bonding pad and the external terminal. Good electrical contact can improve device characteristics and yield.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910022980A KR940007290B1 (en) | 1991-12-14 | 1991-12-14 | Manufacturing method of wirebonding pad |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910022980A KR940007290B1 (en) | 1991-12-14 | 1991-12-14 | Manufacturing method of wirebonding pad |
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| Publication Number | Publication Date |
|---|---|
| KR930014854A KR930014854A (en) | 1993-07-23 |
| KR940007290B1 true KR940007290B1 (en) | 1994-08-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019910022980A KR940007290B1 (en) | 1991-12-14 | 1991-12-14 | Manufacturing method of wirebonding pad |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE43674E1 (en) | 2000-10-18 | 2012-09-18 | Megica Corporation | Post passivation metal scheme for high-performance integrated circuit devices |
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| KR100437621B1 (en) * | 1996-10-30 | 2004-08-25 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE43674E1 (en) | 2000-10-18 | 2012-09-18 | Megica Corporation | Post passivation metal scheme for high-performance integrated circuit devices |
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