USRE43674E1 - Post passivation metal scheme for high-performance integrated circuit devices - Google Patents
Post passivation metal scheme for high-performance integrated circuit devices Download PDFInfo
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- USRE43674E1 USRE43674E1 US11/518,595 US51859506A USRE43674E US RE43674 E1 USRE43674 E1 US RE43674E1 US 51859506 A US51859506 A US 51859506A US RE43674 E USRE43674 E US RE43674E
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Definitions
- the invention relates to the fabrication of integrated circuit devices, and more particularly, to a post passivation scheme that provides low-resistance metal interconnects in addition to bond pads on the surface of an Integrated Circuit device that is covered with a conventional layer of passivation.
- Improvements in semiconductor device performance are typically obtained by scaling down geometric dimensions of the Integrated Circuit (IC) devices, resulting in decreasing the cost per device while improving device performance.
- Metal connections which connect the Integrated Circuit to other circuit or system components, become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on device performance.
- Parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce metal interconnect resistance by using wider metal lines result in higher capacitance of these wires.
- low resistance metal such as copper
- low dielectric materials are used in between signal lines.
- Current practice is to create metal interconnection networks under a layer of passivation.
- This approach limits the interconnect network to fine-line interconnects, which is associated with low parasitic capacitance and high line resistance.
- the latter two parameters because of their relatively high values, degrade device performance, an effect which becomes even more severe for high-frequency applications and for long interconnect lines that are, for instance, typically used for clock distribution lines.
- fine-line interconnect metal cannot carry high values of current that is typically needed for ground busses and for power busses.
- the invention provides such a method.
- An analogy can be drawn in this respect, as follows: the currently used fine-line interconnection schemes, which are created under a layer of passivation, are the streets in a city.
- the interconnections that are created above a layer of passivation can be considered the freeways between cities.
- the interconnection metal lines become thinner and the operating voltages that are applied to the devices become lower.
- the voltage that is applied to the internal circuits is typically about 2.0 Volts or less.
- the IR voltage drop that is introduced by the interconnect lines has a relatively large impact on device functionality and performance, this in particular for circuits within a device that are removed by a considerably distance from bond pads.
- circuits that are located in the center of a device with wire-bonding pads located at the periphery of a chip, for those devices the IR drop that is introduced by interconnect lines can cause either device malfunction or a degradation in the operational speed of the device.
- the invention addresses these concerns.
- a principle objective of the invention is to provide a low impedance metal interconnect system with bond pads on top of a Integrated Circuit device that is covered with a conventional layer of passivation.
- Another objective of the invention is to provide a scheme for metal interconnects with bond pads that negates the effects of IR voltage drops introduced by the interconnect wires for applications where a voltage supply of 2 Volts or less is used.
- Yet another objective of the invention is to provide a low-cost, high-performance post passivation metal interconnection system with bond pads that allows interconnection of power, ground, signal and clock lines over long distances.
- a still further objective of the invention is to provide a low-cost, high-performance post passivation metal interconnection system that allows interconnection of power, ground, signal and clock lines to relatively far removed bond pads without introducing significant IR voltage drop introduced by the metal interconnect system.
- a new post-passivation metal interconnect scheme is provided over the surface of an IC device that has been covered with a conventional layer of passivation.
- the metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads.
- the interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop.
- the post passivation metal scheme is connected to external circuits through wirebonding pads, solder bonding, TAB bonding and the like.
- a top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding.
- the composite metal is created by a bulk (low-resistance) conduction metal covered by a layer of (wire-bondable) metal to which wire bond connections can be readily made.
- a diffusion barrier metal may be applied between the bulk metal and the wire-bondable metal, in addition a layer of Barrier-Metal (BM) may be required underneath the bulk conduction metal.
- BM Barrier-Metal
- FIG. 1 is a cross section of a silicon substrate over which a prior art fine-line interconnect network is created over which a layer of passivation is deposited, power and/or ground pins are provided through the layer of passivation for external connection.
- the structure that is shown in cross section in FIG. 1 addresses prior art power and ground distribution networks.
- FIG. 2 is a cross section of a silicon substrate over which a prior art fine-line interconnect network is created over which a layer of passivation is deposited, clock and/or signal pins are provided through the layer of passivation for external connection.
- the structure that is shown in cross section in FIG. 2 addresses prior art clock and signal distribution networks.
- FIG. 3 is a cross section of a silicon substrate over which an interconnect network is created according to the invention, no ESD-circuit is provided as part of the structure.
- a power/ground contact pad is provided through the surface of a layer of dielectric for external connection.
- the structure that is shown in cross section in FIG. 3 addresses only power and ground distribution networks of the invention.
- FIG. 4 is a cross section of a silicon substrate over which an interconnect network is created according to the invention, no EDS circuit is provided as part of the structure.
- a contact pad is provided through the surface of a layer of dielectric for external connection.
- the structure that is shown in cross section in FIG. 4 addresses clock and signal distribution networks of the invention.
- FIG. 5 shows a cross section of several overlying and interconnected layers of interconnect metal and a bond pad used by the invention for the creation of interconnect metal above the surface of a layer of passivation.
- FIGS. 6 through 10 shows five structures of the invention for creating overlying layers of interconnect metal thereby including a wirebonding pad.
- FIG. 1 shows a cross section of a silicon substrate on the surface of which has been created a conductive interconnect network.
- the structure that is shown in cross section in FIG. 1 addresses prior art power and ground distribution networks.
- the various features that have been highlighted in FIG. 1 are the following:
- circuits are created in or on the surface of a silicon substrate, interconnect lines are created for these circuits for further interconnection to external circuitry.
- the circuits are, on a per I/O pin basis, provided with an ESD circuit, these circuits with their ESD circuit are connected to a power or ground pin that penetrates a layer of passivation.
- the layer of passivation is the final layer that overlies the created interconnect line structure, the interconnect line underneath the layer of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistance and high parasitic capacitance.
- ESD circuits are, as is known in the art, provided for the protection of semiconductor circuits against unexpected electrical charges. For this reason, each pin that connects to a semiconductor circuit must be provided with an ESD circuit.
- FIG. 2 shows a cross section of a prior art configuration that resembles the cross section shown in FIG. 1 .
- the structure that is shown in cross section in FIG. 2 however addresses clock and signal distribution networks.
- FIG. 2 shows, in addition to the previously highlighted aspects of FIG. 1 , the following elements:
- the layer of passivation is the final layer that overlies the created structure.
- the interconnect lines underneath the layer of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistance and high parasitic capacitance.
- pins 56 are signal or clock pins:
- FIG. 3 this figure refers to power and ground interconnects.
- a bond pad is provided through the surface of the thick layer of dielectric for external connection.
- FIG. 3 can be summarized as follows: a silicon substrate is provided in the surface of which have been created semiconductor devices and no electrostatic discharge (ESD) circuit. A first layer of dielectric is deposited over the substrate, a fine-line interconnect network is created in the first layer of dielectric making contact with the active circuits. A layer of passivation is deposited over the surface of the first layer of dielectric. A pattern of metal plugs (or, for low aspect ratio vias and as previously pointed out, direct interconnects between the overlying layers of metal) is created in the layer of passivation that aligns with points of contact created in the surface of the first layer of dielectric.
- ESD electrostatic discharge
- One or more layers of dielectric are deposited over the surface of the layer of passivation, a wide thick line interconnect network is created in the one or more layers of dielectric, contacting the ESD and conventional circuits of the device.
- the first layer of metal of the post-passivation interconnection scheme can be created on top of the passivation, without adding thick dielectric in between.
- a bond pad serving as a point of electrical contact comprising a power or ground contact is provided in or on the surface of the one or more layers of dielectric.
- FIG. 3 shows, as highlighted and in summary, a cross section of a silicon substrate 40 over which a interconnect network is created according to the invention, with the interconnect network created in a thick layer of dielectric overlying a layer of passivation and remaining internal to the thick layer of dielectric. No ESD, receiver, driver or I/O circuit access pin is provided through the surface of the layer of dielectric for external to internal interface.
- Shown in FIG. 3 is the power/ground bus interconnect line 74 , providing for an interconnect scheme of thick, wide lines overlying a passivation layer 62 . Due to the thick, wide lines of the interconnect network that is created overlying a layer 62 of passivation, the power/ground distribution can take place entirely within the interconnect layer 64 .
- the power/ground bus 74 is connected to a bond pad 74 ′, allowing direct and relatively loss-free connection of the power/ground signals to the semiconductor circuits 42 .
- the reason why the circuit configuration that is shown in the cross section of FIG. 3 does not required the use of ESD circuits is basically attributable to the very low impedance of the post-passivation interconnect provided by the invention. That is layer 64 , FIG. 3 , which is a layer of post-passivation dielectric in which, as a post-passivation metal scheme process of the invention, interconnects have been created.
- the accumulated electrostatic discharge will be evenly distributed to the circuits 42 without thereby experiencing a significant resistance.
- the junction capacitance of all the circuits act as a collective and relatively large ESD circuit, that is the collective junction capacitance of circuits 42 is large enough that no ESD circuit is required.
- the electrostatic charge will find the path of lowest resistance, which is the circuit that is close to the bond pad of the device, and destroy that circuit. This chain of events of prevented by the post-passivation interconnect scheme of the invention.
- the cross section that is shown in FIG. 4 is identical to the cross section that has been shown in FIG. 3 , the difference being that the cross section shown in FIG. 4 provides for clock/signal pulses provided over clock/signal bus 74 and the bond pad 74 ′.
- the method that is followed for the creation of the structure that is shown in cross section in FIG. 6 is therefore the same as the previously highlighted method that is used for the creation of the structure of FIG. 3 .
- FIGS. 3 and 4 show a fine-line interconnect network 60 that underlies the layer 62 of passivation
- the invention also enables for and can be further extended with the complete elimination of the fine-line interconnect network 60 and creating an interconnect network 64 that uses only thick, wide wires.
- the first layer of dielectric 60 is not applied, the layer 62 of passivation is deposited directly over the surface of the created semiconductor devices 58 in or on the surface of substrate 40 .
- the post-passivation interconnection scheme can be a single layer of metal or can be more than one layer of metal. Where a single layer of metal is used, the post-passivation interconnection scheme provides both low-resistance interconnection and bond pad capabilities. For applications using more than one layer of metal, the bottom layer of metal is provided for low-resistance interconnect purposes while the top layer of metal provides both low resistance interconnect and bond pad capabilities.
- the post passivation interconnect structure of the present invention comprises a thick, wide metallization system formed above the passivation layer 62, wherein the thick, wide metallization system is used as a distribution network for a clock or signal voltage, and wherein the thick, wide metallization system is connected to the one or more internal circuits, wherein the thick, wide metallization system comprises a metal in the thick, wide metallization system greater than about 1 micrometer in thickness and one or more thick layers of dielectric, wherein the thick layers of dielectric each have a thickness greater than about 2 micrometers.
- the bond pads can be connected to external circuits by solder bonding, wirebonding, tape-automated bonding (TAB) and the like.
- TAB tape-automated bonding
- the bond pad exposed through opening 17 , FIG. 5 is connected to external circuitry by means of bond wire 18 .
- the top layers 15 / 16 in FIG. 5 must comprise a first metal, for instance copper, for purposes of low-resistance, and a second metal, for example Au, for purposes of wire-bonding.
- a layer of metal, for instance Ni is required as a diffusion barrier.
- a layer of adhesion material such as Cr
- the top layer of metal preferably comprises a composite layer of metal such as Cr/Cu/Ni/Au.
- a bottom layer of metal such as layer 14 in FIG. 5
- a layer of Cr may also be required underneath the layer of low-resistance copper for adhesion purposes while a layer of Ni is required overlying the layer of low-resistance copper for applications where protection of the surface of the layer of copper is required.
- the metallurgy of the top layer of metal requires a bulk conduction metal such as copper, gold, aluminum, and the like, in addition to a wire bondable metal such as gold and aluminum is required.
- a layer of diffusion barrier material such as Ni, is required between and overlying the bulk conduction metal and the wire-bondable metal.
- a layer of adhesion material and a barrier layer may also be required under the bulk conduction metal.
- the low-resistance metal such as Au and Al
- the low-resistance metal can also be used for wire-bonding purposes, in which case, the metallurgy becomes simpler.
- layer 14 and 15 , FIG. 5 can both comprise TiW/Au whereby TiW is used as the adhesion layer.
- this cross section is to be viewed as an example of creating overlying interconnects through one or more layers of dielectric, highlighted in the cross section of FIG. 5 are:
- FIGS. 6 through 10 show specific methods and structures for the thick, heavy interconnect scheme and the wire-bonding pad of the invention. These methods and structures will now discussed in detail. It must thereby be kept in mind that the invention provides for a post-passivation interconnect scheme for the interconnections to external circuits. This interconnect to external circuits is typically provided by methods of solder bonding. The significant difference between conventional methods of interconnecting to external circuits is that the invention combined a new, post-passivation interconnect scheme with using wire-bonding techniques. In this manner, the invention solves the problem of typically experiences high IR voltage drop across interconnect lines. A significant aspect of the invention is further that it allows the application of widely available wire-bonding infrastructure and thereby negates the need for relatively expensive methods of solder bonding flip chips.
- the cross sections that are shown in FIGS. 5 through 10 focus on using a wire bonding approach for creating a chip and by applying post-passivation interconnections for the connection of the device to external circuits.
- the post-passivation can be a single layer of metal or can comprise multiple layers of metal.
- a first layer of metal in the post-passivation process is typically on the surface of a thick layer of dielectric. For purposes of cost-reduction, this first layer of metal can also be created directly overlying the surface of the layer of passivation.
- the invention provides a bulk metal such as Cu, Au, Al and the like.
- the invention provides a metal of good wire-bonding characteristics such as Au, Al and the like.
- the metal scheme is relatively simple since both of these metals have low-resistance and good wire-bonding characteristics. This will be further highlighted using the cross section of FIG. 6 and FIG. 9 for Au and Al, respectively.
- a layer of wire-bondable metal such as Au or Al is additionally required.
- a layer of diffusion barrier material such as Ni, is required between the layer of Cu and the overlying layer of Au.
- a adhesion layer for instance comprising Cr, is required between the layer of Cu and the underlying layer of dielectric (polyimide). This will be further highlighted using the cross section of FIGS. 7 and 8 .
- the cross section that is shown in FIG. 6 is an application of the invention where Au or Al is used as the interconnect metal.
- the metal scheme is relatively simple since both of these metals have low-resistance and good wire-bonding characteristics.
- the layer of Cu or Al forms the low-resistance interconnect layer while this metal can also be used for good wire-bonding purposes.
- a Au layer can be created using conventional electroplating technology.
- Au is an inert metal, a layer of Au does not require an overlying layer of polyimide.
- the method of providing at least one bond pad over the surface of the post-passivation interconnection structure may comprise the steps of:
- FIG. 7 has, in addition to or differing with the elements that have been highlighted under FIG. 6 , the following elements:
- the method of providing at least one bond pad over the surface of the post-passivation interconnection structure may comprise the steps of:
- FIG. 8 The cross section that is shown in FIG. 8 has the basic elements that have been highlighted under FIG. 7 , these basic elements have however been processed in a different manner, which will become clear in following the processing flow as this processing flow applies to the cross section of FIG. 8 .
- the method of providing at least one bond pad over the surface of the post-passivation interconnection structure may comprise the steps of:
- the cross section that is shown in FIG. 9 has the simplest metal system, a thick sputtered layer of Al is used in this case.
- the method of providing at least one bond pad over the surface of said post-passivation interconnection structure may comprise the steps of:
- FIG. 10 The cross section that is shown in FIG. 10 has the basic elements that have been highlighted under FIG. 7 , these basis elements have however processed in a different manner which will become clear in the following processing flow as this processing flow applies to the cross section of FIG. 10 .
- the method of providing at least one bond pad over the surface of the post-passivation interconnection structure may comprise the steps of:
- the invention has provided methods and structures for creating thick, heavy layers of interconnect metal connected with bond pads over the surface of a conventional layer of passivation.
- the invention has further provided processing sequences for the creation of the bond pads and the thick heavy layers of metal.
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Abstract
Description
-
- 40, a silicon substrate on the surface of which has been created an interconnect network
- 42, a sample number of semiconductor circuits that have been created in or on the surface of the
substrate 40 - 44, two electrostatic discharge (ESD) circuits created in or on the surface of the
substrate 40, one ESD circuit is provided for each pin that is accessible for external connections (pins 52, see below) - 46 is a layer of interconnect lines; these interconnect lines are above the surface of
substrate 40 and under thelayer 48 of passivation and represent a typical application of prior art fine-line interconnects; these fine-line interconnects oflayer 46 typically have high resistance and high parasitic capacitance - 48 is a layer of passivation that is deposited over the surface of the
layer 46 of interconnect lines; thisconventional layer 48 of passivation is used to protect the underlying devices and the underlying fine-line interconnections - 50 is a power or ground bus that connects to the
circuits 42 via fine-line interconnect lines provided inlayer 46; this power or ground bus is typically of wider metal since this power or ground bus carries the accumulated current or ground connection for thedevices 42 - 52 are two power or ground pins that pass through the
layer 48 of passivation and that have been connected to the power orground bus 50.
-
- 45 are two ESD circuits that are provided in or on the surface of the
substrate 40; ESD circuits are always required for any external connection to an input/output (I/O) pin - 45′ which are circuits that can be receiver or driver or I/O circuits for input (receiver) or output (driver) or I/O purposes respectively
- 54 is a clock or signal bus, and
- 56 are clock or signal pins that have been extended through the
layer 48 of passivation.
- 45 are two ESD circuits that are provided in or on the surface of the
-
- pins 56 must be connected to ESD and driver/receiver or I/
O circuits 45 - for signal or clock pins 56, these pins must be connected not only to ESD circuits but also to driver or receiver or I/O circuits, highlighted as
circuit 45′ inFIG. 2 - after (clock and signal) stimuli have passed through the ESD and driver/receiver or I/O circuits, these stimuli are further routed using, under prior art methods, fine-line interconnect wires. A layer of passivation is deposited over the dielectric layer in which the interconnect network has been created.
- pins 56 must be connected to ESD and driver/receiver or I/
-
- 40 is the silicon substrate on the surface of which interconnect lines are created in accordance with the invention
- 42 are semiconductor circuits that are created in or on the surface of
substrate 40, the semiconductor circuits having one or more active devices - 58 are connection pads to the
semiconductor devices 42 that have been created in or on the surface ofsubstrate 40 - 60 is a layer of fine-line interconnects that has been created overlying connection pads 58 to the
semiconductor devices 42 - 61 is one of the vias or a local fine line interconnections that have been provided for
layer 60, more such vias or local fine line interconnections are shown inFIG. 3 but are, for reasons of simplicity, not highlighted - 62 is a layer of passivation that has been deposited overlying the
layer 60 of fine-line interconnects. In creatinglayer 62 of passivation, a layer of approximately 0.5 μm. PECVD oxide can be deposited first followed by a layer of approximately 0.7 μm. nitride.Passivation layer 62 is very important because it protects the device wafer from moisture and foreign ion contamination. The positioning of this layer between the sub-micron process (of the integrated circuit) and the tens-micron process (of the interconnecting metallization structure) is of critical importance since it allows for a cheaper process that possibly has less stringent clean room requirements for the process of creating the interconnecting metallization structure. - 63 is one of vias that passes through
layer 62 of passivation, more such vias are shown inFIG. 3 but are, for reasons of simplicity, not highlighted - 64 is a layer of post-passivation dielectric in which, as a post-passivation metal scheme process, interconnects have been created; in some applications, the metal can also be created directly on top of the
layer 62 of passivation - 74 is the combined (for multiple connection pads in layer 58) power or ground bus
- 67 is a via or a local thick metal scheme that is created overlying the
layer 62 of passivation, more such vias or local thick metal schemes are shown inFIG. 3 but are, for reasons of simplicity, not highlighted - 74′ is the power or ground bond pad for the multiple semiconductor devices in layer 58.
-
- provides an ESD circuit for each pin that is used for external input/output interconnect
- provides, after ESD stimuli have passed in parallel through the ESD circuits, a fine-line interconnect network for further distribution of the power and ground stimuli, and
- the fine-line power and ground distribution network is created underneath a layer of passivation.
-
- does not need to create an ESD circuit for each pin that is used for external input/output interconnect; this in view of the more robust wiring and the power/ground bond pad that drives the ESD circuit, resulting in reduced power loss by an unexpected power surge over the interconnect line, resulting in more power being delivered to an ESD circuit, and
- allows for the power and ground interconnects to be directly connected to the internal circuits of a semiconductor device, this either without an ESD circuit or with a smaller than regular ESD circuit (as previously explained).
-
- the prior art fine line interconnect lines are created underneath a layer of passivation, the wide, thick interconnect lines of the invention are created above a first and second layer of passivation
- the fine-line interconnect lines are typically created in a layer of inorganic dielectric, the thick wide interconnect lines are typically created in a layer of dielectric comprising polymer. This because an inorganic material cannot be deposited as a thick layer of dielectric because such a layer of dielectric would develop fissures and crack as a result
- fine-line interconnect metal is typically created using methods of sputter with resist etching or of damascene processes using oxide etch with electroplating after which CMP is applied. Either one of these two approaches cannot create thick metal due to cost considerations or oxide cracking
- thick, wide interconnect lines can be created by first sputtering a thin metal base layer, coating and patterning a thick layer of photoresist, applying a thick layer of metal by electroplating, removing the patterned photoresist and performing metal base etching (of the sputtered thin metal base). This method allows for the creation of a pattern of very thick metal, metal thickness in excess of 1 μm can in this manner be achieved while the thickness of the layer of dielectric in which the thick metal interconnect lines are created can be in excess of 2 μm
- the thick, wide metal is formed after formation of the layer of passivation. The semiconductor devices and the fine line interconnection are already well protected by the layer of passivation from mobile ions, moisture and other contaminants. The wide, thick wire can then be formed using unconventional processes which however in most Integrated Circuit fabrication facilities are restrictive in use in for instance applying polymers, Au, Cr, Ni dry film etc. Furthermore, environmental requirements during fabrication can be relaxed.
-
- 40, the cross section of the surface of a silicon substrate
- 42, active semiconductor devices that have been created in or on the surface of
substrate 40 - 60, a layer of dielectric in and through which fine-line interconnect wires have been created; these interconnect wires make contact with the underlying
active semiconductor devices 42 and have in addition been provided with points of electrical contact or top metal in the surface oflayer 60 - 10, two examples of top metal that has been provided in the surface of
layer 60, making contact with the fine-line interconnect wires that have been created inlayer 60 - 62, a layer of passivation deposited over the surface of
layer 60, including the surface oftop metal contacts 10; thepassivation layer 62 is used to protect the underlying active devices (layer 42) and the fine-line interconnections (layer 60 of dielectric) - 11, 12 and 13 respectively a first, a second and a third thick layer of dielectric; these three layers of dielectric significantly are created over the surface of
layer 62 of passivation and are the layers of dielectric in and through which the thick interconnect metal of the invention is created, including at least one contact pad in the surface of the upper layer of dielectric that makes electrical contact with the thick interconnect metal oflayers layer 11 can be omitted, i.e. the layer 14 of metal is directly formed on the surface of thelayer 62 of passivation - 14, a first layer of patterned and etched metal overlying
first layer 11 of dielectric and being in contact withtop metal 10 by means of openings created through thefirst layer 11 of dielectric and thelayer 62 of passivation - 15 and 16, a second layer of patterned and etched metal overlying
second layer 12 of dielectric and being in contact with the first layer 14 of patterned and etched metal by means of openings created through thesecond layer 12 of dielectric;layer 16 can for instance serve as a contact pad,layer 15 provides further interconnect to surrounding circuitry (not shown); layers 15 and 16 can be used for purposes other than forming contacts, these layers can also be used as conductive layers such as layers of signal interconnects - 17, an opening created through the
third layer 13 of dielectric, exposing the surface of patterned and etchedlayer 16 of metal, forming a contact pad over the surface of this exposure - 18, a wire bond connection that establishes electrical contact between the
contact pad 16 and surrounding circuitry (not shown).
-
- layer 14 can comprise a compound layer of Cr/Cu/Ni where the layer of Cu forms the bulk, low-resistance layer of metal, the lower layer of Cr provides adhesion to the overlying layer of Cu and the upper layer of Ni protects the surface of the layer of copper, and
- layers 15 and 16 can comprise a compound layer of Cr/Cu/Ni/Au where the layer of copper provides the bulk, low-resistance layer of metal, the lower layer of Cr provides adhesion to the overlying layer of Cu and the underlying polyimide, the layer of Ni overlying the layer of Cu serves as a diffusion barrier layer while the upper layer of Au is the wire-bondable layer of metal.
-
- 40, the cross section of the surface of a silicon substrate
- 42, active semiconductor devices that have been created in or on the surface of
substrate 40 - 60, a layer of dielectric in and through which fine-line interconnect wires have been created; these interconnect wires make contact with the underlying
active semiconductor devices 42 and have in addition been provided with points of electrical contact or top metal in the surface oflayer 60 - 10, top metal that has been provided in the surface of
layer 60, making contact with the fine-line interconnect wires that have been created inlayer 60 - 62, a layer of passivation deposited over the surface of
layer 60, including the surface oftop metal contact 10 - 11 a first thick layer of dielectric; this
layer 11 of dielectric is created over the surface oflayer 62 of passivation; for purposes of-cost-reduction, thefirst layer 11 of dielectric can be omitted in some applications - 19 and 20, layers of patterned and etched metal forming a bonding pad/low resistance interconnect layer. The
upper layer 20 comprises a selected metal which is selected for purposes of providing low-resistance interconnect while this layer can simultaneously be used for wire-bonding purposes, preferably using Au or Al. Thelower layer 19 is used for purposes of adhesion to the layer of dielectric as well as for forming a diffusion layer to thecontact pad 10. - The processing flow that is provided for the creation of the structure that has been shown in cross section in
FIG. 6 is as follows:
- 1. conventionally performing Front-Of-Line (FOL) processing, comprising processing of
layer 42 of active semiconductor devices,layer 60 of fine-line interconnect metal thereby including the creation oftop metal 10 andlayer 62 of passivation - 2. patterning and etching an opening through the
layer 62 of passivation, this opening being aligned with a portion of thetop metal 10, exposing the surface oftop metal 10; it is clear that where at this time only one opening is indicated, the invention is not limited to the creation of one opening through thelayer 62 of passivation but can create as many openings as are desired for a device layout - 3. depositing a
first layer 11 of dielectric, preferably comprising polyimide; for purposes of cost reduction, this layer can be omitted in some applications - 4. patterning and etching the deposited
first layer 11 of dielectric, creating an opening through this first layer of dielectric; this opening being aligned with the opening that has been created through thelayer 62 of passivation, making this opening being aligned with a portion of thelayer 10 of top metal - 5. successively creating layers of barrier metal such as TiW (layer 19) over which a layer (layer 20) of Au or Al is created, preferably using the method of metal sputtering for the creation of these
layer 19 of metal; it must specifically be noted thatlayer 19 is a composite sputtered layer comprising about 3,000 Angstrom of TiW and about 1,000 Angstrom of Au;layer 20 is a thick layer of Au created by using electroplating techniques;layer 20 is therefore not only used as a bond pad but can additionally be used for interconnect wiring; these latter comments further emphasize that the invention provides for the creation of a metal system that can be simultaneously used for the creation of conductive interconnect traces and for wire bonding purposes; it must as a consequence be pointed out that aspects of separately creating either interconnect traces or wire bond pads are not addressed or provided for by the invention. - 6. creating an exposure mask, preferably comprising photoresist, over the surface of sputtered
layers 19, this mask exposing these layers over a surface area of the metal layers 19 that is to form as a metal system that can be simultaneously used for low resistance conduction and wire bonding, this mask exposing the surface areas where the wiring and the bond pad are required - 7. applying a Au plating to the exposed surface of the
layer 19;layer 20 is a thick layer of Au created by using electroplating techniques;layer 20 is therefore not only used as a bond pad but can additionally be used for interconnect wiring; these latter comments further emphasize that the invention provides for the creation of a metal system that can be simultaneously used for the creation of conductive interconnect traces and for wire bonding purposes; it must as a consequence be pointed out that aspects of separately creating either interconnect traces or wire bond pads are not addressed or provided for by the invention - 8. removing the exposed photoresist, and
- 9. etching layers 19 using the plated Au is a mask. Thus, a metal system has been created for low-resistance interconnects and for wire-bonding purposes.
-
- providing a
substrate 40,active devices 42 having been created in or on the surface of thesubstrate 40, alayer 60 of fine-line interconnect metal includingtop metal 10 being connected to theactive devices 42 having been provided over the surface of thesubstrate 40, alayer 62 of passivation having been provided over the surface of thelayer 60 of fine-line interconnect metal; - patterning and etching an opening through the
layer 62 of passivation, this opening being aligned with aportion 10 of the top metal, exposing thesurface 10 of top metal; - successively creating a first layer (one layer of layers 19) of metal comprising TiW over which a second layer metal (one layer of layers 19) comprising Au is created, preferably using the method of metal sputtering for the creation of these
layers 19; - creating an exposure mask (not shown in FIG. 6), preferably comprising photoresist, over the surface of sputtered second layer of metal comprising Au, this mask exposing the second layer of metal over a surface area that is to form the low-resistance interconnection and the bond pad;
- applying a
bulk metal 20 plating to the exposed surface of the second layer of metal comprising Au; - removing the exposure mask; and
- etching the second layer of metal comprising Au and the first layer of metal comprising TiW in accordance with the plated
layer 20 of bulk metal, leaving in place the first and thesecond layers 19 of metal where the platedlayer 20 of bulk metal plating has been applied, thereby providing a metal system serving as both low-resistance conduction and wirebonding pads.
- providing a
-
- 21, a first layer of metal, preferably comprising Cr or Ti or TiW or a compound thereof;
layer 21 serves as an adhesion layer between theoverlying layer 22 of Cu and theunderlying layer 11 of dielectric; a thin layer of copper (not shown) is subsequently sputtered over thesurface 21 to serve as a seed layer for the electroplating oflayer 22,layer 22 is not yet formed at this time - 22, a second layer of metal of the bond pad, preferably comprising Cu or a Cu compound, selected for its low-resistance characteristics
- 23, a third layer of metal of the bond pad, preferably comprising Ni or a Ni compound
- 12, a second layer of dielectric, an
opening 25 has been created through this layer of dielectric, exposing the surface oflayer 23 for the creation of thefourth layer 24 of metal of the bond pad, and - 24, a fourth layer of metal of the bond pad, preferably comprising Au or an Au compound.
- 21, a first layer of metal, preferably comprising Cr or Ti or TiW or a compound thereof;
- 1. conventionally performing Front-Of-Line (FOL) processing, comprising processing of
layer 42 of active semiconductor devices,layer 60 of fine-line interconnect metal thereby including the creation oftop metal 10 andlayer 62 of passivation - 2. patterning and etching an opening through the
layer 62 of passivation, this opening is to be aligned with a portion of thetop metal 10, exposing the surface oftop metal 10 - 3. depositing a
first layer 11 of dielectric, preferably comprising polyimide; in some applications, this layer of dielectric can be omitted for reasons of cost-reduction - 4. patterning and etching the deposited
first layer 11 of dielectric, creating an opening through this first layer of dielectric; this opening is to be aligned with the opening that has been created through thelayer 62 of passivation making this opening being aligned with a portion of thelayer 10 of top metal - 5. creating layers 21 (comprising Cr or Ti or TiW) and a layer of Cu (not shown), preferably using the method of metal sputtering for the creation of these layers of metal
- 6. creating an exposure mask, preferably comprising photoresist, over the surface of sputtered
layers 21, this mask exposing these layers over a surface area of themetal layer 21 that is to form as a bond pad, this mask further covering all surface areas of thelayer 22 21 that are not serving as a bond pad - 7. applying a Cu plating (not shown in
FIG. 7 )layer 22 to the exposed surface of thelayer 21 - 8. applying a Ni plating to the copper plated surface of
layers layer 22, creatinglayer 23 - 9. removing the exposed photoresist, and
- 10. etching
layer 21 essentially in accordance with the applied Ni and Cu plating layers 23 and 22, leaving inplace layer 21 where the Cu and Ni plating (layer 22 and 23) haslayers layer 23, further exposing the surface of thefirst layer 11 of dielectric - 11. depositing a
second layer 12 of dielectric, preferable comprising polyimide, over the exposed surface oflayer 23 and the exposed surface of thefirst layer 11 of dielectric - 12. patterning and etching the deposited
second layer 12 of dielectric, creating anopening 25 through thesecond layer 12 of dielectric that aligns with the patterned andetched layers layer 23, and - 13. performing electroless gold plating to the exposed surface of
layer 23, creatingbond pad 24.
-
- providing a
substrate 40,active devices 42 having been created in or on the surface of thesubstrate 40, alayer 60 of fine-line interconnect metal having been provided over the surface of thesubstrate 40, at least onelayer 10 of patterned top metal having been provided over the surface of thelayer 60 of fine-line interconnect metal, the at least one layer of patterned top metal having been connected to thelayer 60 of fine-line interconnect metal, alayer 62 of passivation having been provided over the surface of thelayer 60 of fine-line interconnect metal; - patterning and etching at least one first opening through the
layer 62 of passivation, the at least one first opening being aligned with aportion 10 of the at least one layer of top metal, exposing thesurface 10 of the at least one layer of top metal; - creating a
first layer 21 of metal, serving as a diffusion barrier and an adhesion layer, over the surface of thelayer 62 of passivation, preferably using metal sputtering for the creation of thefirst layer 21 of metal; - creating a second layer (not shown in FIG. 7) of seed metal for subsequent processing of electroplating, preferably using methods of metal sputtering;
- creating an exposure mask (not shown in FIG. 7), preferably comprising photoresist, over the surface of the sputtered second layer of metal, the exposure mask exposing the second layer of metal over a surface area of the second layer of metal that is to form a low resistance interconnection;
- applying a first metal plating to the exposed surface of the second layer of metal, creating a
third layer 22 of metal to form a low-resistance interconnection over the exposed surface area of the second layer of metal; - applying a second metal plating to the exposed surface of the third layer of metal, creating a
fourth layer 23 of metal to form a diffusion barrier over the surface area of thethird layer 23 of metal; - removing the exposure mask;
- etching the first and second layers (21 and seed layer) of metal in accordance with the applied third and fourth metal plating, thereby leaving in place the first, the second, the third and the fourth layers (21, seed layer, 22 and 23) of metal that serve as diffusion barrier, electroplating seed layer, low-resistance layer and diffusion barrier respectively;
- depositing a
second layer 12 of dielectric, preferably comprising polyimide, over the exposed surface of thefourth layer 23 of metal and the exposed surface of thelayer 62 of passivation; - patterning and etching the deposited
layer 12 of dielectric, creating anopening 25 through thelayer 12 of dielectric that aligns with a portion of the patterned and etched first, second, third and fourth layers (21, seed layer, 22 and 23) of metal, exposing the surface of thefourth layer 23 of metal; and - applying a third metal plating to the exposed surface of the
fifth layer 24 of metal, preferably using electroless plating, creating a bond pad.
- providing a
- 1. conventionally performing Front-Of-Line (FOL) processing, comprising processing of
layer 42 of active semiconductor devices,layer 60 of fine-line interconnect metal thereby including the creation oftop metal 10 andlayer 62 of passivation - 2. patterning and etching an opening through the
layer 62 of passivation, this opening is to be aligned with a portion of thetop metal 10, exposing the surface oftop metal 10 - 3. depositing a
first layer 11 of dielectric, preferably comprising polyimide; this layer of dielectric can be omitted in some applications - 4. patterning and etching the deposited
first layer 11 of dielectric, creating an opening through thisfirst layer 11 of dielectric; this opening is to be aligned with the opening that has been created through thelayer 62 of passivation making this opening being aligned with a portion of thelayer 10 of top metal - 5. creating a
layer 21 of Cr or Ti or TiW, preferably using the method of metal sputtering for the creation of these layers of metal; a thin layer of copper (not shown) is sputtered over the surface oflayer 21 to serve as a seed layer for the electroplating of overlyinglayer 22,layer 22 is not yet formed at this time - 6. creating a exposure mask, preferably comprising photoresist, over the surface of sputtered
layer 21, this mask exposing this layer over a surface area of themetal layer 21 that is to form as the low resistance interconnection and a bond pad, this mask further covering all surface areas of thelayer 21 that are not serving as a bond pad - 7. applying a Cu plating to the exposed surface of the
layers 21, creatinglayer 22 - 8. applying a Ni plating to the exposed surface of the
layers 22, creatinglayer 23 - 9. applying a Au plating to the exposed surface of the
layers 23, creatinglayer 24; this essentially creates a three layered mask of layers 21 (over which a thin layer of copper, not shown, has been sputtered), 22 and 23 - 10. removing the exposure mask
- 11. etching layers 21 (and the thereover sputtered thin layer of copper) essentially in accordance with the applied Au plating, leaving in place layers 21, 22, 23 and 24 where the Au plating has been applied, thereby leaving in place layers 21, 22, 23 and 24 that serve as the low resistance interconnection and a bond pad, exposing the surface of
layer 24, further exposing the surface of thefirst layer 11 of dielectric - 12. depositing a
second layer 12 of dielectric, preferable comprising polyimide, over the exposed surface oflayer 24 and the exposed surface of thefirst layer 11 of dielectric - 13. patterning and etching the deposited
second layer 12 of dielectric, creating anopening 26 through thesecond layer 12 of dielectric that aligns with a portion of the patterned andetched layers layer 24.
-
- providing a
substrate 40,active devices 42 having been created in or on the surface of thesubstrate 40, alayer 60 of fine-line interconnect metal having been provided over the surface of thesubstrate 40, at least onelayer 10 of patterned top metal having been provided over the surface of thelayer 60 of fine-line interconnect metal, the at least onelayer 10 of patterned top metal having been connected to thelayer 60 of fine-line interconnect metal, alayer 62 of passivation having been provided over the surface of thelayer 60 of fine-line interconnect metal; - patterning and etching at least one first opening through the
layer 62 of passivation, the at least one first opening being aligned with a portion of the at least onelayer 10 of top metal, exposing the surface of the at least onelayer 10 of top metal; - creating a
first layer 21 of metal over the surface of thelayer 62 of passivation, preferably using the method of metal sputtering for the creation of thislayer 21 of metal; - sputtering a thin second layer (not shown in FIG. 8) over the surface of the
first layer 21 of metal, the second layer serving as an electroplating seed layer; - creating an exposure mask (not shown in FIG. 8), preferably comprising photoresist, over the surface of the sputtered second layer of metal, the exposure mask exposing the surface of the second layer of metal over a surface area that is to serve as a low-resistance interconnection and a bond pad;
- creating a
third layer 22 of metal over the exposed surface of the second layer of metal; - creating a
fourth layer 23 of metal over the exposed surface of thethird layer 22 of metal; - creating a
fifth layer 24 of metal over the exposed surface of thefourth layer 23 of metal; - removing the exposure mask;
- etching the first and the second layers (21 and seed layer) of metal in accordance with the created
fifth layer 24 of metal, leaving in place the first, second, third, fourth and fifth layers (21, seed layer, 22, 23 and 24) of metal where thefifth layer 24 of metal has been applied, these layers serving as a low-resistance interconnection and a bond pad, exposing the surface of thefifth layer 24 of metal, further exposing the surface of thelayer 62 of passivation; - depositing a
layer 12 of dielectric, preferable comprising polyimide, over the exposed surface of thefifth layer 24 of metal and the exposed surface of thelayer 62 of passivation; - patterning and etching the deposited
second layer 12 of dielectric, creating anopening 26 through the second layer of dielectric that aligns with a portion of the patterned and etched first, second, third, fourth and fifth layers of metal, exposing the surface of thefifth layer 24 of metal, creating a bond pad.
- providing a
- 1. conventionally performing Front-Of-Line (FOL) processing, comprising processing of
layer 42 of active semiconductor devices,layer 60 of fine-line interconnect metal thereby including the creation oftop metal 10 andlayer 62 of passivation - 2. patterning and etching an opening through the
layer 62 of passivation, this opening is to be aligned with a portion of thetop metal 10, exposing the surface oftop metal 10 - 3. depositing a
first layer 11 of dielectric, preferably comprising polyimide; in some applications, this layer of dielectric can be omitted for cost reasons - 4. patterning and etching the deposited
first layer 11 of dielectric, creating an opening through this first layer of dielectric; this opening is to be aligned with the opening that has been created through thelayer 62 of passivation making this opening being aligned with a portion of thelayer 10 of top metal - 5. creating a
layer 21 of Al; this layer of Al is thicker than 1 μm and is preferably created using methods of metal sputtering - 6. creating an exposure mask, preferably comprising photoresist, over the surface of sputtered
Al layer 21; this mask exposes a surface area except the surface of theAl layer 21 that is to form a low-resistance interconnection and a bond pad, this mask further covering all surface areas of the metal layer that are not serving as a bond pad - 7. etching the Al metal layer in accordance with the exposure mask, preferably using wet etching
- 8. removing the exposure mask
- 9. depositing a
second layer 12 of dielectric, preferable comprising polyimide, over the exposed surface oflayer 24 21 and the exposed surface of thefirst layer 11 of dielectric - 10. patterning and etching the deposited
second layer 12 of dielectric, creating anopening 26 through thesecond layer 12 of dielectric that aligns with a portion of the patterned and etchedlayer 21, exposing the surface oflayer 24 21, the exposed surface oflayer 24 21 serving as a bond pad.
-
- providing a
substrate 40,active devices 42 having been created in or on the surface of thesubstrate 40, alayer 60 of fine-line interconnect metal having been provided over the surface of thesubstrate 40, at least onelayer 10 of patterned top metal having been provided over the surface of thelayer 60 of fine-line interconnect metal, said at least onelayer 10 of patterned top metal having been connected to saidlayer 60 of fine-line interconnect metal, alayer 62 of passivation having been provided over the surface of thelayer 60 of fine-line interconnect metal; - patterning and etching at least one first opening through the
layer 62 of passivation, said at least one first opening being aligned with a portion of said at least onelayer 10 of top metal, exposing the surface of said at least onelayer 10 of top metal; - depositing a
first layer 11 of dielectric over the surface of saidlayer 62 of passivation, including at least one opening created through saidlayer 62 of passivation, saidfirst layer 11 of dielectric preferably comprising polyimide; - patterning and etching the deposited
first layer 11 of dielectric, creating at least one second opening through thisfirst layer 11 of dielectric, said at least one second opening being aligned with said at least one first opening through thelayer 62 of passivation; - creating a
layer 21 of metal over the surface of saidfirst layer 11 of dielectric including inside surfaces of said second opening created through saidfirst layer 11 of dielectric, preferably using the method of metal sputtering for the creation of thislayer 11 of metal; - creating an exposure mask (not shown in FIG. 9), preferably comprising photoresist, over the surface of sputtered
layer 21 of metal, said exposure mask covering this layer over a surface area of themetal layer 21 that is to serve as a low-resistance interconnection and a bond pad; - etching the
layer 21 of metal in accordance with the exposure mask, exposing the surface of saidfirst layer 11 of dielectric; - removing the exposure mask, exposing the surface of said
layer 21 of metal; - depositing a
second layer 12 of dielectric, preferable comprising polyimide, over the exposed surface of the fourth layer of metal and the exposed surface of thefirst layer 11 of dielectric; and - patterning and etching the deposited
second layer 12 of dielectric, creating anopening 26 through thesecond layer 12 of dielectric that aligns with a portion of the patterned and etchedlayer 21 of metal, exposing the surface of thelayer 21 of metal, the exposed surface of thelayer 21 of metal serving as a bond pad.
- providing a
- 1. conventionally performing Front-Of-Line (FOL) processing, comprising processing of
layer 42 of active semiconductor devices,layer 60 of fine-line interconnect metal thereby including the creation oftop metal layer 62 of passivation;top metal - 2. patterning and
etching openings layer 62 of passivation,openings top metal 10′, exposing the surface oftop metal 10′; opening 32 to be aligned with a portion of thetop metal 10, exposing the surface oftop metal 10 - 3. depositing a
first layer 11 of dielectric, preferably comprising polyimide; in some applications, this layer of dielectric can be omitted - 4. patterning and etching the deposited
first layer 11 of dielectric, creating openings through this first layer of dielectric; these openings are to be aligned with theopenings - 5. creating a
layer 21 of TiW or Ti or Cr over which a thin layer of Cu (not shown) is created; the thin layer of copper (not shown) serves as a seed layer for the electroplating of an overlying layer - 6. creating an exposure mask, preferably comprising photoresist, to expose
area 100;area 100 can be an interconnecting network covering a large portion of the chip area, connecting toareas 10′, a portion of which forms a wire bonding pad exposed throughopening 28; the length ofarea 100 can be large since low resistance interconnect metal is used, while 10′ should be short since higher resistance metal is used - 7. applying a Cu plating 22 to the exposed surface of the
layer 21 inarea 100 - 8. applying a Ni plating 23 to the exposed surface of the
layers 22 inarea 100 - 9. removing the exposure mask
- 10. etching (the thin layer of copper, not shown) and
layer 21 of TiW using the patternedlayers layer 10′ of aluminum in thebond pad 28 - 11. depositing a
second layer 12 of dielectric, preferably comprising polyimide, over the complete surface of the wafer - 12. patterning and etching the
layer 12 of dielectricoutside area 100′, to openregion 29, exposing the surface of the bond pad exposed throughopening 28.
-
- providing a
substrate 40,active devices 42 having been created in or on the surface of thesubstrate 40, alayer 60 of fine-line interconnect metal including top metal being connected to theactive devices 42 having been provided over the surface of thesubstrate 40, thetop metal 10 comprising wire-bondable metal 10′, thetop metal 10 comprising at least one first portion of top metal which comprises abond pad 10′, thetop metal 10 further comprising at least one second portion of top metal that needs to be connected to the first portion of top metal, alayer 62 of passivation having been provided over the surface of thelayer 60 of fine-line interconnect metal; - patterning and etching a first, second and a
third openings layer 62 of passivation, thefirst opening 28 being aligned with a portion of the first portion of top metal, thesecond opening 31 being aligned with a portion of the second portion of top metal, thethird opening 32 being aligned with a portion of the second portion of top metal, exposing the surface of the first and second portion of top metal; - depositing a
first layer 11 of dielectric, preferably comprising polyimide, over the surface of thelayer 62 of passivation, including the first, second andthird openings layer 62 of passivation; - patterning and etching the deposited
first layer 11 of dielectric, creating a fourth, a fifth and a sixth openings through thefirst layer 11 of dielectric, thefourth opening 29 through thefirst layer 11 of dielectric being aligned with thefirst opening 28 created through thelayer 62 of passivation, the fifth and sixth openings through thefirst layer 11 of dielectric respectively being aligned with the second andthird openings layer 62 of passivation; - creating a
first layer 21 of metal over the surface of thefirst layer 11 of dielectric, creating a second layer (not shown in FIG. 10) of metal serving as seed layer over the surface of thefirst layer 21 of metal; - creating an exposure mask (not shown in FIG. 10), preferably comprising photoresist, over the surface of the created second layer of metal, exposing the second layer of metal only over the surface area of the second layer of metal at least in a region over and between the second and third opening while not exposing the first opening;
- creating a patterned
third layer 22 of metal over the exposed surface of the second layer of metal; - creating a patterned
fourth layer 23 of metal over the surface of the patternedthird layer 22 of metal; - removing the exposure mask, exposing the surface of the second layer of metal, leaving in place a mask of the patterned third and
fourth layers 23 of metal in place overlying the second layer of metal; - etching the second and the first layers (seed layer and 21) of metal in accordance with the mask of third and
fourth layers top metal 10′ in the bond pad, thereby exposing the surface of thefirst layer 11 of dielectric; - depositing a
second layer 12 of dielectric over the surface of the patternedfourth layer 23 of metal and the surface of thefirst layer 11 of dielectric, preferable comprising polyimide; and - patterning and etching the deposited
second layer 12 of dielectric, creating an opening through thesecond layer 12 of dielectric that aligns with the bond pad.
- providing a
Claims (119)
Priority Applications (1)
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US11/518,595 USRE43674E1 (en) | 2000-10-18 | 2006-09-08 | Post passivation metal scheme for high-performance integrated circuit devices |
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US09/691,497 US6495442B1 (en) | 2000-10-18 | 2000-10-18 | Post passivation interconnection schemes on top of the IC chips |
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US20364605A | 2005-08-12 | 2005-08-12 | |
US11/518,595 USRE43674E1 (en) | 2000-10-18 | 2006-09-08 | Post passivation metal scheme for high-performance integrated circuit devices |
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US10/004,027 Reissue US6605528B1 (en) | 2000-10-18 | 2001-10-24 | Post passivation metal scheme for high-performance integrated circuit devices |
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