JP5335931B2 - Chip package with power management integrated circuit and related technology - Google Patents

Abstract

Chip packages having power management integrated circuits are described. Power management integrated circuits can be combined with on-chip passive devices, and can provide voltage regulation, voltage conversion, dynamic voltage scaling, and battery management or charging. The on-chip passive devices can include inductors, capacitors, or resistors. Power management using a built-in voltage regulator or converter can provide for immediate adjustment of the voltage range to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices. Related fabrication techniques are described.

Description

  This application claims priority from US Provisional Patent Application No. 61 / 140,895, filed December 26, 2008. By quoting this application here, the entire contents thereof are also included in the present application.

Conventional technology

  Conventional printed circuit boards (“PCBs”) typically have various components, which have different power inputs that require different voltages. In PCBs having a large number of electrical devices, each of which may require a different voltage, power supplies having different output voltages are commonly used. These output voltages are typically selected to correspond to the general voltage range used by PCB electronic devices. However, such an approach rather consumes a large amount of energy, increases the difficulty of circuit design, and is considerably more expensive. Currently, a fairly large size voltage regulator is used to deal with many different voltage ranges, and no on-chip regulator has been realized.

  In order to reduce the amount of energy required, one widely used method is to change the voltage from one power supply unit using multiple voltage regulators or converters to address the need for electrical devices. doing. These voltage regulators or converters allow the voltage entering each electrical device to correspond to the operating voltage of that device.

  The more different types of electrical devices on the PCB, the greater the number of corresponding voltage regulating devices so that the power supply voltage entering the electrical devices is in the correct voltage range. However, such circuit designs may utilize overly high quality, high cost voltage regulator devices. In addition, the electrical wiring between different voltage regulators must be separated, requiring more metal wires, which increases the total manufacturing cost. Of course, such circuit designs may not be suitable for use in micron scale electronic products or may not be very economical. In addition, using multiple voltage regulators instead of multiple power supply units can effectively reduce the amount of wasted resources, but the multiple voltage regulators used in consideration of different electrical devices Therefore, the circuit on the PCB becomes rather complicated. Since the signal passes through a complicated wiring configuration, the signal response time is naturally long and cannot be immediate, and at the same time the efficiency of power management is reduced. This circuit design also occupies a large part of the PCB and is an inefficient use of circuit routing.

  The present disclosure describes semiconductor chips and application circuits that address the disadvantages already described. In one aspect of the present disclosure, a semiconductor chip structure and related application circuits are provided. Using a chip manufacturing method, a switching voltage regulator or voltage converter is integrated into a semiconductor chip so that the switching voltage regulator or voltage converter and the semiconductor chip are combined as one structure.

In another aspect of the present disclosure, a semiconductor chip structure and an application circuit thereof having an ability to quickly adapt to a power supply voltage variation and efficiently reduce a transient response time are provided.
In another aspect of the present disclosure, a semiconductor chip structure and its application circuit are provided. The use of such integrated voltage regulators or converters reduces the overall difficulty of circuit design on PCBs or motherboards, reduces manufacturing costs, and miniaturizes electronic products. Fulfill.

  Embodiments of the present disclosure can provide a semiconductor chip structure that includes a silicon substrate having multiple devices and a set of external components. On this silicon substrate, a passivation layer can be provided in the thin circuit structure. The passivation layer can have a number of passivation layer openings for electrical connection from external components or circuits to the thin circuit structure. The device can include an active device. Examples of active devices can include p-type metal oxide semiconductor (MOS) devices (eg, MOSFETs), N-type MOS devices, and / or complementary metal oxide semiconductor (CMOS) devices, It is not limited to these. Example embodiments of the present disclosure can include voltage feedback devices and / or switch controllers made with the aforementioned active devices in a semiconductor chip. Similarly, embodiments can also include external passive components such as resistors, capacitors, and inductors.

  Example embodiments of the present disclosure can provide a circuit structure. The circuit structure includes, from top to bottom, at least one first dielectric layer, a first metal layer, a second dielectric layer, and a second metal layer. The first dielectric layer can be located on the substrate, and a contact window can be provided in the first dielectric layer. The first metal layer can be located on the first dielectric layer and a corresponding contact window can be used to electrically connect every point on the first metal layer to the corresponding device. . The second dielectric layer may be located on the first metal layer and may include a number of vias. The second metal layer can be electrically connected to the corresponding first metal layer through the corresponding via. A polymer layer can be provided directly above or above the passivation layer. The polymer layer can have an opening over the opening in the passivation layer, and an under bump metal structure or a post-passivation metal layer can be provided over the opening in the passivation layer. Also, according to different embodiments of the semiconductor chip, a solder layer, or solder wetting layer, or wire bondable layer, barrier layer, metal layer, and adhesion / barrier layer are provided in the under bump metal structure. be able to. The thickness of the solder layer can vary depending on the different thicknesses of the semiconductor chip packaging structure and the materials used therein. The post-passivation metal layer can have the same composition as the under-bump metal structure, or comprises an adhesion / barrier layer and a metal layer, such as a copper or gold layer. Finally, a second polymer layer can be provided on the post-passivation metal layer, and the second polymer layer can incorporate an opening exposing the post-passivation metal layer.

  The embodiments of the present disclosure may also include various application circuits that are adapted to the semiconductor chip. The application circuit includes an internal electric circuit and an external electric circuit. The internal and external circuits can be electrically connected using a metal circuit. Devices implemented in the internal circuit may be, but are not necessarily limited to, P-type MOS devices, N-type MOS devices, CMOS devices, voltage feedback devices, and / or switch controllers. Not a translation. External electrical circuit components can include, but are not limited to, resistors, capacitors, and inductors. The internal electrical circuit can be located in or on the silicon substrate, while the metal circuit and the external circuit are on the substrate, and there is a metal circuit between the internal circuit and the external circuit. Semiconductor chips and chip packages according to the present disclosure can utilize a variety of packaging techniques, including but not limited to the following techniques. Packaging methods include thin small outline package (TSOP), small outline J-lead (SOJ), quad flat package (QFP), thin Quad flat package (TQFP) and ball grid array (BGA). In addition, the wire bonding or flip chip technique can be used to electrically connect the semiconductor chip in the present disclosure to the outside.

  Accordingly, aspects and embodiments of the present disclosure can provide a semiconductor chip having the ability to accommodate switching voltage regulation and various voltages required by various chip designs and / or components. This semiconductor chip shortens the transient response time, reduces the circuit routing area used on the PCB, and reduces the complexity of circuit connections. These improvements can lead to a reduction in the overall cost of manufacturing the semiconductor device.

  Other features and advantages of the present disclosure will be understood by reading and understanding the detailed description of example embodiments described herein with reference to the drawings.

Other features and advantages of the present disclosure will be understood by reading and understanding the detailed description of example embodiments described herein with reference to the drawings. In the drawing
FIG. 1 shows a circuit diagram of an example embodiment of the present disclosure. FIG. 2 is a graph showing the relationship between the used frequency and the output impedance. FIG. 3 shows a cross-sectional diagram of a semiconductor chip according to a first embodiment of the present disclosure. FIG. 3A shows a semiconductor chip manufacturing process according to the first embodiment of the present disclosure. FIG. 3B shows a semiconductor chip manufacturing process according to the first embodiment of the present disclosure. FIG. 3C shows a semiconductor chip manufacturing process according to the first embodiment of the present disclosure. FIG. 3D shows a semiconductor chip manufacturing process according to the first embodiment of the present disclosure. FIG. 3E shows a semiconductor chip manufacturing process according to the first embodiment of the present disclosure. FIG. 4 shows a cross-sectional diagram of a semiconductor chip according to a second embodiment of the present disclosure. FIG. 4A shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4B shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4C shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4D shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4E shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4F shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4G shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4H illustrates a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4I illustrates a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4J illustrates a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4K illustrates a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4L illustrates a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4M shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4N shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4O illustrates a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4P shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4Q shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4R shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4S illustrates a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4T illustrates a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4U shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AA shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AB shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AC shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AD shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AE shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AF shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AG shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AH shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AI shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AJ shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AK shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AL shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 4AM shows a semiconductor chip manufacturing process according to the second embodiment of the present disclosure. FIG. 5 shows a cross-sectional diagram of a semiconductor chip according to a third embodiment of the present disclosure. FIG. 5A shows a semiconductor chip manufacturing process according to the third embodiment of the present disclosure. FIG. 5B shows a semiconductor chip manufacturing process according to the third embodiment of the present disclosure. FIG. 5C shows a semiconductor chip manufacturing process according to the third embodiment of the present disclosure. FIG. 5D shows a semiconductor chip manufacturing process according to the third embodiment of the present disclosure. FIG. 6 shows a cross-sectional diagram of a semiconductor chip according to a fourth embodiment of the present disclosure. FIG. 6A shows a semiconductor chip manufacturing process according to the fourth embodiment of the present disclosure. FIG. 6B shows a semiconductor chip manufacturing process according to the fourth embodiment of the present disclosure. FIG. 6C shows a semiconductor chip manufacturing process according to the fourth embodiment of the present disclosure. FIG. 6D shows a semiconductor chip manufacturing process according to the fourth embodiment of the present disclosure. FIG. 6E shows a semiconductor chip manufacturing process according to the fourth embodiment of the present disclosure. FIG. 6F shows a semiconductor chip manufacturing process according to the fourth embodiment of the present disclosure. FIG. 6G shows a semiconductor chip manufacturing process according to the fourth embodiment of the present disclosure. FIG. 6H illustrates a semiconductor chip manufacturing process according to the fourth embodiment of the present disclosure. FIG. 6I shows a semiconductor chip manufacturing process according to the fourth embodiment of the present disclosure. FIG. 7A shows a cross-sectional diagram of a semiconductor chip according to a fifth embodiment of the present disclosure. FIG. 7B shows a cross-sectional diagram of a semiconductor chip according to a sixth embodiment of the present disclosure. FIG. 8 illustrates a ball grid array (BGA) package structure according to a fourth embodiment of the present disclosure. FIG. 9 illustrates a ball grid array (BGA) package structure according to a fourth embodiment of the present disclosure. FIG. 10 illustrates a ball grid array (BGA) package structure according to a fourth embodiment of the present disclosure. FIG. 11 illustrates a ball grid array (BGA) package structure according to a fourth embodiment of the present disclosure. FIG. 12A shows a semiconductor chip package structure according to the first, second, fourth, and fifth embodiments of the present disclosure. FIG. 12B shows a semiconductor chip package structure according to the first, second, fourth, and fifth embodiments of the present disclosure. FIG. 12C illustrates a semiconductor chip package structure according to the first, second, fourth, and fifth embodiments of the present disclosure. FIG. 12D illustrates a semiconductor chip package structure according to the first, second, fourth, and fifth embodiments of the present disclosure. FIG. 12E illustrates a semiconductor chip package structure according to the first, second, fourth, and fifth embodiments of the present disclosure. FIG. 12F illustrates a semiconductor chip package structure according to the first, second, fourth, and fifth embodiments of the present disclosure. FIG. 13A shows a semiconductor chip package structure according to a third embodiment of the present disclosure. FIG. 13B shows a semiconductor chip package structure according to a third embodiment of the present disclosure. FIG. 13C shows a semiconductor chip package structure according to a third embodiment of the present disclosure. FIG. 13D shows a semiconductor chip package structure according to a sixth embodiment of the present disclosure. FIG. 13E shows a semiconductor chip package structure according to a sixth embodiment of the present disclosure. FIG. 13F shows a semiconductor chip package structure according to a sixth embodiment of the present disclosure. FIG. 14 shows a diagram of an equivalent circuit of the semiconductor chip according to the first embodiment of the present disclosure. FIG. 15 shows a diagram of an equivalent circuit of a semiconductor chip according to the second embodiment of the present disclosure. FIG. 16 is a graph showing the relationship between the voltage of the circuit in FIG. 15 and time. FIG. 17A shows a manufacturing process according to a seventh embodiment of the present disclosure. FIG. 17B shows a manufacturing process according to the seventh embodiment of the present disclosure. FIG. 17C illustrates a manufacturing process according to the seventh embodiment of the present disclosure. FIG. 17D shows a manufacturing process according to a seventh embodiment of the present disclosure. FIG. 17E illustrates a manufacturing process according to the seventh embodiment of the present disclosure. FIG. 17F shows a manufacturing process according to the seventh embodiment of the present disclosure. FIG. 17G shows a manufacturing process according to the seventh embodiment of the present disclosure. FIG. 17H illustrates a manufacturing process according to the seventh embodiment of the present disclosure. FIG. 17I illustrates a manufacturing process according to a seventh embodiment of the present disclosure. FIG. 17J illustrates a manufacturing process according to the seventh embodiment of the present disclosure. FIG. 17K illustrates a manufacturing process according to the seventh embodiment of the present disclosure. FIG. 17L illustrates a manufacturing process according to the seventh embodiment of the present disclosure. FIG. 18A shows a manufacturing process according to an eighth embodiment of the present disclosure. FIG. 18B shows a manufacturing process according to an eighth embodiment of the present disclosure. FIG. 18C shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18D shows a manufacturing process according to an eighth embodiment of the present disclosure. FIG. 18E shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18F shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18G shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18H shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18I shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18J shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18K shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18L shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18M shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18N shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18O shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18P shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 18Q shows a manufacturing process according to the eighth embodiment of the present disclosure. FIG. 19B shows a side view and a top view of a manufacturing process according to the ninth embodiment of the present disclosure. FIG. 19B shows a side view and a top view of a manufacturing process according to the ninth embodiment of the present disclosure. FIG. 20A is a side view and a top view according to a tenth embodiment of the present disclosure, respectively. FIG. 20B is a side view and a top view according to the tenth embodiment of the present disclosure, respectively. FIG. 21A shows a manufacturing process according to an eleventh embodiment of the present disclosure. FIG. 21B shows a manufacturing process according to an eleventh embodiment of the present disclosure. FIG. 21C shows a manufacturing process according to the eleventh embodiment of the present disclosure. FIG. 21D shows a manufacturing process according to an eleventh embodiment of the present disclosure. FIG. 21E shows a manufacturing process according to the eleventh embodiment of the present disclosure. FIG. 21F shows a manufacturing process according to the eleventh embodiment of the present disclosure. FIG. 21G shows a manufacturing process according to the eleventh embodiment of the present disclosure. FIG. 21H shows a manufacturing process according to the eleventh embodiment of the present disclosure. FIG. 21I shows a manufacturing process according to the eleventh embodiment of the present disclosure. FIG. 21J shows a manufacturing process according to the eleventh embodiment of the present disclosure. FIG. 21K shows a manufacturing process according to the eleventh embodiment of the present disclosure. FIG. 22 shows a circuit diagram of a voltage amplification device according to an example embodiment of the present disclosure. FIG. 23 shows a circuit diagram of a voltage amplification device according to an example embodiment of the present disclosure. FIG. 24 shows a cross-sectional view of an N-type double diffusion MOS (DMOS) according to an example embodiment of the present disclosure. FIG. 25 shows a top view of an N-type DMOS device according to an example embodiment of the present disclosure. FIG. 26A shows a side view of a system-in package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 26B shows a side view of a system-in package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 27A illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 27B illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 28A illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 28B illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 29A illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 29B illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 30A illustrates a system-in-package or module that includes a power management IC chip having an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 30B illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 31A illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 31B illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 32A illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 32B illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 33A illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device, according to an example embodiment of the present disclosure. FIG. 33B illustrates a system-in-package or module that includes a power management IC chip with an on-chip passive device according to an example embodiment of the present disclosure. FIG. 34 is a step-down DC-DC switching voltage regulator or converter including an on-chip passive device for input power and a switch controller having two N-type switching DMOS devices, according to an example embodiment of the present disclosure. Indicates. FIG. 35 is a step-down DC-DC switching including an on-chip passive device for input power and a switch controller having a P-type switching NMOS device and an N-type switching DMOS device according to an example embodiment of the present disclosure. Indicates a voltage regulator or converter. FIG. 36 is a step-up DC-DC switching voltage regulator or converter including an on-chip passive device for input power and a switch controller having two N-type switching DMOS devices, according to an example embodiment of the present disclosure. Indicates. FIG. 37 shows a cross-sectional view of a portion of the step-down switching voltage regulator or converter of FIG. FIG. 38 shows a cross-sectional view of a portion of the step-up switching voltage regulator or converter of FIG. FIG. 39 shows a circuit diagram of an operational amplifier, according to an example embodiment of the present disclosure. FIG. 40 shows a circuit layout having functional blocks of a converter that realizes the circuit diagram of FIG. FIG. 41 shows a circuit layout having functional blocks of a converter that realizes the circuit diagram of FIG.

  Although certain embodiments are illustrated in the drawings, the illustrated embodiments are exemplary and variations of what is shown and other embodiments described herein may be envisioned and practiced within the scope of the disclosure. it can.

  Aspects of the present disclosure are directed to related application circuits having a semiconductor chip structure and a number of passive devices integrated on the semiconductor chip. By using active devices from different functional semiconductor chips to match passive components integrated on the semiconductor chip, immediate voltage adaptation can be achieved within a specific voltage range.

The embodiment of the present disclosure can provide a semiconductor chip structure having the equivalent circuit structure 1 shown in FIG. A feature of the circuit structure 1 used in the example embodiment of the present disclosure is that the circuit structure incorporates a voltage regulator 12 ′, also called a converter, which is connected to the parasitic elements 14 ′ and PC board parasitic elements 14 ′. It is to be manufactured after the parasitic element 15 'of the chip package. Thus, the voltage regulator 12 'need not bear the burden of the parasitic elements 14' and 15 ', so that the voltage regulator or converter integrated with one chip allows circuit operation under higher frequencies. The voltage regulator or converter 12 'can be controlled by pulse-frequency-modulation or pulse-width-modulation to control the duty cycle. The modulation frequency of the voltage regulator or converter 12 'can be between 1 KHz and 300 MHz, and is preferably between 1 MHz and 100 MHz for duty cycle control. Also, this circuit structure design can reduce the manufacturing cost and simplify the routing design on the PCB. This is because the distance between the voltage regulator 12 'and the corresponding electrical device 16' is shortened. The simplification of the routing design increases the speed and efficiency of signal distribution and eliminates the problem of large voltage fluctuations when using high frequencies. An example of the relationship between the load current frequency and the impedance resistance value is shown in FIG.
Subsequently, preferred embodiments of each structure in the semiconductor chip structure are proposed first. Next, an application circuit is proposed with reference to a specific embodiment.

Embodiment 1
FIG. 3 shows a substrate 100 made of a type of semiconductor substrate. The substrate should be silicon, gallium arsenide (GaAs), silicon indium (SiIn), silicon antimony (SiSb), indium antimony (InSb), or silicon germanium (SiGe). Many devices, such as devices 110, 112, and 114, are located within or above substrate 100. These devices 110, 112, and 114 can be primarily active devices, but can also include passive devices. Active devices include voltage feedback devices, switch controllers, or p-channel MOS devices, n-channel MOS devices, n-channel DMOS devices, p-channel DMOS devices, LDMOS, BiCMOS devices, bipolar junction transistors. MOS devices such as (BJT) or CMOS are included.

  As shown in FIG. 3, a thin circuit structure can be placed on or positioned on the substrate 100. The circuit structure can include a first dielectric layer 150, a number of metal layers 140, and at least one second dielectric layer 155. The thickness of the first dielectric layer 150 and the second dielectric layer 155 can be between 0.3 micrometers and 2.5 micrometers in the example embodiment, and the first and second dielectric layers Materials used to make can include boron-containing silicate glass, silicon nitride, silicon oxide, silicon oxynitride, and carbon-containing low-k dielectric materials. The thickness of the metal layer 140 can be between 0.1 micrometers and 2 micrometers in the example embodiment, and the materials used to make the metal layer are copper, aluminum-copper alloy, tantalum, Tantalum nitride, tungsten, and tungsten alloys can be included. Devices 110, 112, 114 can be electrically connected to metal layer 140 through metal contacts 120 and metal vias 130. The metal contact 120 and the metal via 130 pass through the first dielectric layer 150 and the second dielectric layer 155. The metal contacts 120 and vias 130 can be W-plugs or Cu-plugs. In addition, the metal layer 140 can be formed by various methods including damascene processes, electroplating, CVD, and sputtering. For example, damascene processes, electroplating, sputtering, and CVD can be used to form the copper metal layer 140, and sputtering can be used to form the aluminum metal layer 140. The first dielectric layer 150 and the second dielectric layer 155 can be formed by chemical vapor deposition (CVD) or can be formed by a carbon nanotube material.

A passivation layer 160 can be disposed on the circuit structure constituted by the first dielectric layer 150, the metal layer 140, and the second dielectric layer 155. The passivation layer 160 can protect the devices 110, 112, 114 and the metal layer 140 described above from moisture and metal ion contamination. In other words, the passivation layer 160 can cause mobile ions such as sodium ions, transition metal ions such as moisture, gold, silver, and copper, and other impurities to pass through and damage the devices 110, 112, 114. Can be prevented. Devices 110, 112, 114 are under a MOS device, n-channel DMOS device, p-channel DMOS device, LDMOS, BiMOS device, bipolar transistor, or voltage feedback device, and switch controller, or passivation layer 160. It can be all of a certain metal layer 140. In addition, the passivation layer 160 is typically made of silicon oxide (such as SiO ₂ ), phosphosilicate glass (PSG), silicon nitride (such as Si ₃ N ₄ ), or silicon oxynitride. Typically, the thickness of the passivation layer 160 is between 0.3 and 2 micrometers, and when including a silicon nitride layer, the thickness of the silicon nitride layer typically exceeds 0.3 micrometers. Less than 2 micrometers.

  In the following, ten example methods for manufacturing or fabricating the passivation layer 160 will be described. Of course, according to the present disclosure, other suitable methods of manufacturing or fabricating the passivation layer 160 may be utilized.

  In the first method, the passivation layer 160 is formed by depositing a silicon oxide layer to a thickness between 0.2 and 1.2 μm using a CVD method, and a silicon nitride layer is formed on the silicon oxide layer using the CVD method. Can be formed by depositing to a thickness between 0.3 and 1.2 μm.

  In the second method, the passivation layer 160 is formed by depositing a silicon oxide layer to a thickness of between 0.2 and 1.2 μm using a CVD method, and then using this plasma enhanced CVD (PECVD) method. A silicon oxynitride layer is deposited on the silicon layer to a thickness between 0.05 and 0.3 μm, and then a CVD method is used to deposit a silicon nitride layer on the silicon oxynitride layer between 0.2 and 1.2 μm. It can be formed by depositing to a thickness of.

  In the third method, the passivation layer 160 is formed by depositing a silicon oxynitride layer to a thickness between 0.05 and 0.3 μm using the CVD method, and then depositing the silicon oxynitride layer on the silicon oxynitride layer using the CVD method. A silicon oxide layer is deposited to a thickness between 0.2 and 1.2 μm, and then a silicon nitride layer is deposited on the silicon oxide layer to a thickness between 0.2 and 1.2 μm using a CVD method. Can be formed.

  In the fourth method, the passivation layer 160 deposits a first silicon oxide layer to a thickness between 0.2 and 0.5 μm using a CVD method, and then uses a spin coating method to form a first silicon oxide layer. A second silicon oxide layer is deposited on the silicon oxide layer to a thickness of between 0.5 and 1 μm, and then a third silicon oxide layer is formed on the second silicon oxide layer using a CVD method to a thickness of 0.2 and By depositing to a thickness between 0.5 μm and then depositing a silicon nitride layer on the third silicon oxide to a thickness between 0.2 and 1.2 μm using a CVD method. it can.

  In the fifth method, the passivation layer 160 can be formed by depositing a silicon oxide layer to a thickness of between 0.5 and 2 μm, for example, using a high density plasma CVD (HDP-CVD) method. On this silicon oxide layer, a silicon nitride layer can be deposited with a desired thickness, for example, 0.2 and 1.2 μm by using the CVD method.

  In a sixth method, the passivation layer 160 can be formed by depositing an undoped silicate glass (USG) layer to a desired thickness, for example, between 0.2 and 3 μm. Next, for example, an insulating layer of tetraethyl orthosilicate (“TEOS”), phosphosilicate glass (“PSG”), or borophosphosilicate glass (“BPSG”), for example, 0.5 and 3 μm. Can be deposited on the USG layer at a desired thickness. A silicon nitride layer can then be deposited on the insulating layer, for example by using a CVD method, with a desired thickness between 0.2 and 1.2 μm, for example.

  In the seventh method, the passivation layer 160 uses the CVD method to arbitrarily volume the first silicon oxynitride layer to a thickness between 0.05 and 0.3 μm, and then uses the CVD method. A silicon oxide layer is deposited on the one oxynitride layer to a thickness of between 0.2 and 1.2 μm, and then a second silicon oxynitride layer is deposited on the silicon oxide layer using a CVD method to a thickness of 0.05 and 0.00. Arbitrarily deposited to a thickness between 3 μm, then CVD method is used to deposit a silicon nitride layer on the second silicon oxynitride layer or silicon oxide layer to a thickness between 0.2 and 1.2 μm And then depositing a third silicon oxynitride layer on the silicon nitride layer to a thickness of between 0.05 and 0.3 μm using a CVD method and on the third silicon oxynitride layer using a CVD method Or a silicon oxide layer of 0.2 and 1.2 μm on the silicon nitride layer. By depositing a thickness of between, it can be formed.

  In the eighth method, the passivation layer 160 is formed by depositing a first silicon oxide layer to a thickness between 0.2 and 1.2 μm using a CVD method, and then using a spin coating method. A second silicon oxide layer is deposited on the layer to a thickness of between 0.5 and 1 μm, and then a third silicon oxide layer is deposited on the second silicon oxide layer by a CVD method to a thickness of 0.2 and 1.2 μm. And then using a CVD method to deposit a silicon nitride layer on the third silicon oxide layer to a thickness between 0.2 and 1.2 μm and using the CVD method It can be formed by depositing a fourth silicon oxide layer on the silicon nitride layer to a thickness between 0.2 and 1.2 μm.

  In the ninth method, the passivation layer 160 is formed by depositing a first silicon oxide layer to a thickness between 0.5 and 2 μm using the HDP-CVD method, and then using the CVD method on the first silicon oxide layer. A silicon nitride layer is deposited to a thickness between 0.2 and 1.2 μm and a second silicon oxide layer is deposited on the silicon nitride to a thickness between 0.5 and 2 μm using HDP-CVD. It can be formed by depositing.

  In the tenth method, the passivation layer 160 is formed by depositing a first silicon nitride layer to a thickness of between 0.2 and 1.2 μm using a CVD method, and then using a CVD method on the first silicon nitride layer. A silicon oxide layer is deposited to a thickness between 0.2 and 1.2 μm, and a second silicon nitride layer is deposited on the silicon oxide layer using a CVD method to a thickness between 0.2 and 1.2 μm. It can be formed by depositing.

  Still referring to FIG. 3, the passivation layer 160 may include more than one passivation layer opening 165 to expose a portion of the underlying metal layer 140. The passivation layer opening 165 can be any desired and practical shape, for example, a circle, a square, a rectangle, or a polygon with more than five edges. Different shapes can have different opening dimensions and characteristics. For example, a circular opening has a dimension defined by its diameter, a square opening has a dimension defined by its side length, and a polygon with more than 5 edges is the longest Has dimensions defined by diagonal lines.

  The portion of the metal layer 140 exposed by the passivation layer opening 165 in the passivation layer 160 defines the pads 166, 167. An optional metal cap (not shown) may be provided on the pads 166, 167 to protect the pads 166, 167 from being damaged by oxidation. The metal cap can be an aluminum-copper alloy, a gold layer, a titanium-tungsten alloy layer, a tantalum layer, a tantalum nitride layer, or a nickel layer. For example, if the pads 166 and 167 are copper pads, a metal cap such as an aluminum-copper alloy must be used to protect the copper pads exposed by the passivation layer openings 165 from oxidation. Oxidation can damage copper pads. When the metal cap is an aluminum-copper alloy, a barrier layer is formed between the copper pad and the aluminum-copper alloy. The barrier layer includes titanium, titanium-tungsten alloy, titanium nitride, tantalum, tantalum nitride, chromium, or nickel. There are the following methods under conditions without a metal cap, but one skilled in the art should be able to infer a similar method when a metal cap is added.

  With continued reference to FIG. 3, an under bump metal (“UBM”) structure 250 is disposed over the passivation layer opening 165. The thickness of the under bump metal structure 250 can be selected as desired, and in an example embodiment is between about 1 micrometer and 15 micrometers. This under bump metal structure 250 can be connected to external devices 310 and 320 through solder layer 300. The solder layer 300 may include a gold-tin alloy, a tin-silver alloy, a tin-silver-copper alloy, or other lead-free alloy. Using a tin-silver alloy as an example, the ratio of tin to silver can be adjusted as needed, with the most common tin / silver ratio being 96.0 to 97 / 3.0 to 4 . The thickness of the solder layer 300 can be between 30 micrometers and 350 micrometers in the example embodiment, but of course other thicknesses can be realized. Under bump metal structure 250 can be a TiW / Cu / Ni metal layer structure, a Ti / Cu / Ni metal structure, a Ti / Cu metal structure, or a Ti / Cu / Ni / Au metal structure.

A suitable method for forming the TiW / Cu / Ni / Au under bump metal structure 250 will be described with reference to FIGS. 3A-3E. Initially, as shown in FIG. 3A, a TiW adhesion / barrier metal layer 168 is deposited with a thickness of between 0.05 and 0.5 micrometers using a sputtering or vapor deposition process. , And a passivation layer 160, and then using a sputtering process, a copper seed layer 170 (FIG. 3B) is deposited on the TiW metal layer 168 at a thickness of 0.05 and 1 micrometer. Can be formed. Next, a patterned photoresist layer 172 (FIG. 3C) can be formed on the seed layer 170. This patterned photoresist layer 172 has more than one opening 172a to expose the seed layer 170. Next, one or more metal layers can be deposited / formed using an electroplating or electroless plating process (FIG. 3D). For example, the following can be formed. (I) a copper metal layer 174 having a desired thickness between, for example, 3 and 30 micrometers, (ii) a nickel layer 176 having a desired thickness, for example, between 0.5 and 5 micrometers, ( iii) a gold layer 178 having a desired thickness of, for example, between 0.05 and 1.5 micrometers, preferably between 0.05 and 0.2 micrometers, respectively, of the patterned photoresist layer 172 It can be formed in the opening 172a. Finally, the photoresist layer 172 and portions of the seed layer 170 and TiW metal layer 168 that are not under the gold layer 178 are removed (FIG. 3E) to complete the TiW / Cu / Ni / Au under bump metal structure 250. . Here, the Cu seed layer 170 removal process can be performed using a wet etching solution containing H ₂ SO ₄ or NH ₄ OH, and the TiW adhesion / barrier metal layer 168 removal process is 20-40%. This can be done using a wet etching solution containing H ₂ O ₂ . In some cases, the PH value of the etching solution for removing TiW is preferably higher than 6 in order to prevent Cu corrosion during TiW removal. Of course, other suitable removal processes may be used within the scope of this disclosure.

Other methods for forming the seed layer 170 include vapor deposition, electroplating, or electroless plating. Sputtering may be preferred. Since the seed layer 170 is important for constructing an electrical circuit thereon, the material used for the seed layer 170 can be variously changed depending on the material used for the electrical circuit in a subsequent process.
For example, when the metal layer 174 made of a copper material is formed on the seed layer 170 by electroplating, copper is also an optimal material for use in the seed layer 170. Similarly, if the metal layer 174 is made of a gold material and is formed on the seed layer 170 by electroplating, the best material to use for the seed layer 170 is gold. Similarly, when the metal layer 174 is made of a palladium material and formed on the seed layer 170 by electroplating, palladium is also an optimal material for use in the seed layer 170. If the metal layer 174 is made of a platinum material and formed on the seed layer 170 by electroplating, platinum is also an optimal material for use in the seed layer 170. When the metal layer 174 is made of a rhodium material and is formed on the seed layer 170 by electroplating, rhodium is also an optimal material for use in the seed layer 170. Similarly, when the metal layer 174 is made of a ruthenium material and formed on the seed layer 170 by electroplating, ruthenium is also an optimal material for use in the seed layer 170. When the metal layer 174 is made of a ruthenium material and is formed on the seed layer 170 by electroplating, rhenium is also an optimal material for use in the seed layer 170. When the metal layer 174 is made of a silver material and is formed on the seed layer 170 by electroplating, silver is also an optimal material for use in the seed layer 170.

  The structure of the under bump metal structure 250 can vary depending on the method used to form the solder layer 300 (FIG. 3). For example, when the solder layer 300 is formed on the under bump metal structure 250 by electroplating, the under bump metal structure 250 is preferably a TiW / Cu / Ni alloy structure or a Ti / Cu / Ni alloy structure. There is a case. Solder structure 300 can be electroplated on nickel, TiW, or Ti metal layers formed by sputtering on pads 166, 167, and passivation layer 160, and Cu / Ni is deposited by electroplating. Can do. A copper seed layer deposited by sputtering may be provided between the TiW and Ti metal layers and the copper layer.

  In other examples, when the solder layer 300 is provided by external devices 310 and 320 or by solder printing, the under bump metal structure 250 is preferably a TiW / Cu / Ni / Au or Ti / Cu / Ni / Au structure. Good.

  Through the solder layer 300, the under bump metal structure 250 overlying the passivation layer opening 165 can be electrically connected to external devices 310 and 320 (shown as 310 in the figure). External devices 310 and 320 are also electrically connected to the metal layer 140 under the passivation layer 160, and thus the external devices 310 and 320 are also electrically connected to the devices 110, 112, and 114.

  External devices 310 and 320 can be passive devices, such as inductors, capacitors, resistors, or integrated passive devices. In example embodiments of the present disclosure, external devices 310 and 320 each include a capacitor and an inductor. For example, the external device 310 can be a capacitor, while the external device 320 can be an inductor. Alternatively, external device 310 can be an integrated passive device, while external device 320 can be an inductor. The dimensions of external devices 310 and 320 may be selected from industry standard dimension 1210, dimension 0603, dimension 0402, or dimension 0201, where dimension 0201 represents 0.02 inch x 0.01 inch, dimension 1210, dimension 0603, And the dimension 0402 is estimated from the same standard. In general, the length of the external devices 310 and 320 can be between 0.2 mm and 5 mm and the width between 0.1 mm and 4 mm in the example embodiment. External devices 310 and 320 can be configured directly on the under bump metal structure 250 through the connection of the solder layer 300. Also, the external devices 310 and 320 can be mounted either before or after a dice sawing procedure is performed on the substrate 100.

  Finally, the semiconductor chip after the die sawing procedure can be electrically connected to an external circuit or power supply by a flip chip technique, for example through a copper or gold wire made by wire bonding or by soldering. it can. For example, a copper wire or gold wire can be connected to the pad 167 by wire bonding techniques. In this case, pad 167 is a copper pad, an aluminum pad, an aluminum cap, or a nickel cap.

Embodiment 2
Referring to FIG. 4, the chip structure according to the second embodiment (“embodiment 2”) of the present disclosure is similar to that of the first embodiment (“embodiment 1”) described above, and thus the manufacturing process and characteristics are the same. The description of a part of (property) will not be repeated. The difference between Embodiment 2 and Embodiment 1 is in the under bump metal structure 260 and the bonding metal layer 400c configured on or above the pad 166b. The bonding metal layer 400c can be used to electrically connect to an external circuit through a copper wire or a gold wire (not shown) formed by wire bonding.

The structure of Embodiment 2 can be manufactured by a suitable method including the following method.
Manufacturing method 1 of Embodiment 2:
Referring to FIG. 4A, the integrated circuit 20 represents all the structures below the passivation layer 160. Also, integrated circuit 20 includes substrate 100, devices 110, 112, 114, first dielectric layer 150, metal layer 140, second dielectric layer 155, metal contact 120, and via 130 (shown in FIG. 4). Not included). In circuit 20, a number of passivation layer openings 165 expose a number of pads 166a and 166b.

  Referring to FIG. 4B, the adhesion / barrier layer 22 is formed on the passivation layer 160 and the pads 166a and 166b, for example by using sputtering. The thickness of the adhesion / barrier layer 22 is selected as desired. In example embodiments, this thickness can be between about 0.1 micrometers and about 1 micrometer with an optimum thickness being between 0.3 micrometers and 0.8 micrometers. The adhesion / barrier can be selected from or consist of the following materials: Ti, TiW, TiN, Ta, TaN, Cr, and Mo. Ti and TiW are two preferred materials for adhesion / barrier.

  Referring to FIG. 4C, the desired thickness, for example, between 0.05 and 1 micrometer (and the optimum thickness is between 0.1 and 0.7 micrometers) is then determined. A seed layer 24 is formed on the adhesion / barrier layer 22. Similar to the seed layer 170 described above, the material used for the seed layer 24 can vary depending on the material of the metal layer formed thereafter. The material of the seed layer can be, for example, Cu, Au, or Ag. In this embodiment, Au is a preferred seed layer material.

  Referring to FIG. 4D, a photoresist layer 26 is formed on the seed layer 24, the photoresist layer 26 is patterned by spin coding, exposure, and development, and a number of photoresist layer openings 26a are formed in the photoresist layer 26. Form. These photoresist layer openings 26a expose portions of seed layer 24 that are on pads 166b.

  Referring to FIG. 4E, a bonding metal layer 400c is formed on the seed layer 24 by electroplating, electroless plating, sputtering, or CVD. The bonding metal layer 400c is in the photoresist layer opening 26a. The bonding metal layer 400c is made of a material such as aluminum, gold, copper, silver, palladium, rhodium, ruthenium, rhenium, or nickel, and may have a single metal layer structure or a multiple metal layer structure. The thickness of the bonding metal layer 400c is between 1 micrometer and 100 micrometers, and the optimum thickness is between 1.5 micrometers and 15 micrometers. The bonding metal layer 400c can also be configured by a combination of a number of metal layer structures, which include Cu / Ni / Au, Cu / Au, Cu / Ni / Pd, and Cu / Ni / Pt. It is. In this embodiment, the bonding metal layer 400c is preferably a single layer made of gold.

Referring to FIG. 4F, a removal process can be performed on the patterned photoresist layer 26 and portions of the seed layer 24 that are not under the metal layer 400c. As an example, if the seed layer 24 is made of gold, the seed layer 24 can be removed using a solution containing I ₂ and KI.

  Referring to FIG. 4G, a suitable thickness between, for example, 0.05 and 1 micrometer (optimum thickness is 0.1 micrometer and 0) over the adhesion / barrier layer 22 and the metal layer 400c. Seed layer 28 can be formed. In this embodiment, the material of the seed layer 28 is preferably copper (Cu). Similar to the seed layer 170 described above, the material used for the seed layer 28 varies depending on the material of the metal layer to be formed later.

  Referring to FIG. 4H, a photoresist layer 30 can be formed on the seed layer 28, patterned by spin coating, exposure, and development, and the photoresist layer 30 can be coated with a number of photoresists. A layer opening 30a is formed. These photoresist layer openings 30a expose portions of the seed layer 28 that are over the pads 166a.

  Referring to FIG. 4I, a metal layer 32 is formed on the seed layer 28 by electroplating. The metal layer 32 is in the photoresist layer opening 30a. The metal layer 32 can be made of copper and can have a desired thickness, eg, between about 1 micrometer and about 100 micrometers. A preferred thickness is between about 1.5 micrometers and about 15 micrometers.

  Referring to FIG. 4J, a metal layer 34 can be formed on the metal layer 32 by electroplating. The metal layer 34 is in the photoresist layer opening 30a. The metal layer 34 can be made of nickel and can have a desired thickness, for example, a thickness between about 0.1 micrometers and about 20 micrometers. A preferred thickness is between 1 and 5 micrometers.

  Referring to FIG. 4K, the metal layer 300 can be formed on the metal layer 34 by electroplating. The metal layer 300 is in the photoresist layer opening 30a. The metal layer 300 can be made of a material such as tin, Sn / Ag alloy, Sn / In alloy, Sn / Ag / Cu alloy, and any other lead-free solder material, with a desired thickness, eg, about 5 Having a thickness between micrometer and about 300 micrometers. A preferred thickness is between 20 and 150 micrometers.

FIG. 4L illustrates the removal process of the patterned photoresist layer 30 and portions of the seed layer 28 and the adhesion / barrier layer 22 that are not under the metal layer 300. To remove the seed layer 28 made of copper, NH ₃ ⁺ or SO ₄ ²⁺ can be used to etch the copper. Then, dry etching or wet etching can be used to remove the adhesion / barrier layer 22. Dry etching requires the use of reactive ion etching or argon sputter etching. On the other hand, when using wet etching, if the adhesion / barrier layer 22 is made of a Ti / W alloy, hydrogen peroxide can be used to remove this layer. If the adhesion / barrier layer 22 is made of Ti, this layer can be removed using an HF-containing solution. On the other hand, a number of metal layers, such as metal layer 34, metal layer 32, seed layer 28, and adhesion / barrier layer 22 below metal layer 300 are the under bump metal structure 250 shown in FIG. The seed layer 28 and the adhesion / barrier layer 24 under the metal layer 400c are each the under-bump metal structure 260 shown in FIG. In the manufacture of this embodiment, the under bump metal structure 250 can be a TiW / Cu / Ni structure and the under bump metal structure 260 can be a TiW / Au seed layer.

Referring to FIG. 4M, the reflow process in an environment containing less than 20 ppm oxygen causes the solder layer 300 to collate.
Referring to FIG. 4N, the external device 310 and the external device 320 are mounted on the solder layer 300. In this embodiment, external devices 310 and 320 can be passive devices and can include inductors, capacitors, resistors, and / or integrated passive devices. In example embodiments of the present disclosure, external devices 310 and 320 are two different passive devices. For example, the external device 310 may be a capacitor, while the external device 320 may be an inductor. Alternatively, the external device 310 may be an integrated passive device, while the external device 320 may be an inductor. External devices 310 and 320 can each have multiple contact points (not shown in the figure). On the surface of these many contact points, there is a metal suitable for mounting on the metal layer 300. For example, the surface of the contact point can have a solder material layer, such as a tin-containing layer, or a solder wet etch layer, such as a gold layer.

  The dimensions of external devices 310 and 320 may be selected from industry standard dimension 12101, dimension 0603, dimension 0402, or dimension 0201, for example, dimension 0201 represents 0.02 inch x 0.01 inch, dimension 1210, dimension 0603 and dimension 0402 can be estimated by the same standard. In general, external devices 310 and 320 may have a length between 0.2 mm and 5 mm, a width between 0.1 mm and 4 mm, and a height between 0.01 mm and 2 mm in the example embodiment. it can.

Subsequent steps can include a dicing procedure, where the substrate 100 is first sawed into a number of chips. Next, the wire 37 can be formed by wire bonding on the metal layer 400c on the pad 166b, and the wire 37 is used to connect to an external circuit or a power source. The wire 37 can be formed of copper or gold. For example, a copper wire or gold wire can be connected to the bonding metal layer 400c by wire bonding techniques. In this case, the bonding metal layer 400c is a copper pad, an aluminum pad, an aluminum cap, or a nickel cap.
The external devices 310 and 320 can also be mounted after performing a dicing procedure on the substrate 100.

Manufacturing method 2 of Embodiment 2:
Manufacturing method 2 differs from manufacturing method 1 in that solder layer 300 is provided during the mounting process of devices 310 and 320 by external devices 310 and 320 or by external addition. In other words, the structure does not have a solder layer 300 on the under bump metal structure 250 prior to mounting the external devices 310 and 320. Details of this manufacturing process will be described below.

  Continuing from FIG. 4B and with further reference to FIG. 4O, a seed layer 38 is deposited on the adhesion / barrier layer 22 to a desired thickness, for example, about 0.05 micrometers and about 1 micrometer (preferred optimal thicknesses are , Between 0.1 and 0.7 micrometers). In this embodiment, the seed layer 38 is made of Cu. Similar to the seed layer 170 described above, the material used for the seed layer 38 varies according to the material of the metal layer to be formed later.

  Referring to FIG. 4P, a photoresist layer 40 is formed on the seed layer 38, patterned by spin coating, exposure, and development, and a large number of photoresist layer openings are formed in the photoresist layer 40. 40a is formed. Photoresist layer opening 40a separately exposes pad 166b and the portion of seed layer 24 overlying pad 166a.

  Referring to FIG. 4Q, a metal layer 42 is formed on the seed layer 38 by electroplating. This metal layer 40 is in the photoresist layer opening 40a. The metal layer 42 is made of a material such as gold, copper, silver, palladium, rhodium, ruthenium, rhenium, or nickel, and may have a single metal layer structure or a multiple metal layer structure. The thickness of the metal layer 42 can be between about 1 micrometer and about 100 micrometers, with an optimal preferred thickness being between 1.5 micrometers and 15 micrometers. In this embodiment, the metal layer 42 can be made of copper.

  Referring to FIG. 4R, a metal layer 44 is formed on the metal layer 42 by electroplating. The metal layer 44 is in the photoresist layer opening 40a. The metal layer 44 can be made of nickel and can have a desired thickness, for example, between about 0.5 micrometers and about 100 micrometers, with an optimal preferred thickness of 1 micrometer. And between 5 micrometers.

  Referring to FIG. 4S, a metal layer 46 is formed on the metal layer 44 by electroplating, electroless plating, sputtering, or CVD. The metal layer 46 is in the photoresist layer opening 40a. The metal layer 46 can be made of a material such as aluminum, gold, silver, palladium, rhodium, ruthenium, or rhenium and has a desired thickness, eg, between about 0.03 micrometers and about 2 micrometers. Can have a thickness. The optimal preferred thickness is between 0.05 and 0.5 micrometers. In this embodiment, the material of the metal layer 46 can be gold (Au).

Referring to FIG. 4T, a removal process can be used to remove the patterned photoresist layer 40 and portions of the seed layer 44 and adhesion / barrier layer 22 that are not under the metal layer 46. To remove the seed layer 24 made of copper, the copper can be etched using NH ₃ ⁺ or SO ₄ ²⁺ containing solutions. Dry or wet etching can be used to remove the adhesion / barrier layer 22. Dry etching requires the use of reactive ion etching or argon sputter etching. On the other hand, when using wet etching, if the adhesion / barrier layer 22 is made of a Ti / W alloy, hydrogen peroxide can be used to remove this layer. If the adhesion / barrier layer 22 is made of Ti, this layer can be removed using an HF-containing solution.

  Referring to FIG. 4U, external device 310 and external device 320 may be separately connected on / to metal layer 46. External devices 310 and 320 can include a solder layer 300. Alternatively, the solder layer 300 can be formed on the metal layer 46 by a screen printing method. The external devices 310 and 320 are mounted on the metal layer 46 through the solder layer 400.

  In this embodiment, external devices 310 and 320 can be passive devices, such as inductors, capacitors, resistors, and / or integrated passive devices. In example embodiments of the present disclosure, external devices 310 and 320 are two different passive devices. For example, the external device 310 may be a capacitor, while the external device 320 may be an inductor. Alternatively, the external device 310 may be an integrated passive device, while the external device 320 may be an inductor. External devices 310 and 320 can each have multiple contact points (not shown in the figure). On the surface of these many contact points, there is a metal suitable for mounting on the metal layer 300. For example, the surface of the contact point can have a solder material layer or a solder wetting layer such as a gold layer.

  The dimensions of external devices 310 and 320 may be selected from industry standard dimension 12101, dimension 0603, dimension 0402, or dimension 0201, where dimension 0201 represents 0.02 inch x 0.01 inch, and dimension 1210, dimension 0603, And the dimension 0402 can be estimated by the same standard. In general, external devices 310 and 320 can be between 0.2 mm and 5 mm in length, between 0.1 mm and 4 mm in width, and between 0.01 mm and 2 mm in height.

  Subsequently, a dicing procedure can be performed and the substrate 100 is first sawed to obtain a large number of chips. The wire 47 can then be conducted on the metal layer 46 on the pad 166b by wire bonding, and the wire 47 can be used to connect to an external circuit or power source. The wire 47 can be formed of copper or gold. For example, a copper wire or gold wire can be connected to the bonding metal layer 400c by wire bonding techniques. In this case, the bonding metal layer 400c is a copper pad, an aluminum pad, an aluminum cap, or a nickel cap. The external devices 310 and 320 can be mounted after performing a dicing procedure on the substrate 100.

Manufacturing method 3 of Embodiment 2:
4A to 4AM show a third manufacturing method according to the second embodiment. 4AA is a cross-sectional view taken along line 2-2 in FIG. 4AB. Integrated circuit 20 represents all the structures underlying passivation layer 160. Also, integrated circuit 20 includes substrate 100, devices 110, 112, 114, first dielectric layer 150, metal layer 140, second dielectric layer 155, metal contact 120, and via 130 (shown in FIG. 4). Not included). A number of passivation layer openings 165a and openings 165b in the passivation layer 160 expose a number of pads 166a, pads 166b, and 166ab. A number of metal pads 166a and 116b are preferably designed in a rectangular configuration.

  Referring to FIG. 4AC, the adhesion / barrier layer 22 is formed on the passivation layer 160 and the pads 166a and 166b by using a sputtering method. The thickness of the adhesion / barrier layer 22 is selected as desired. For example, this thickness can be between 0.1 and 1 micrometer, with an optimum thickness between 0.3 and 0.8 micrometers. The adhesion / barrier can be selected from or consist of the following materials: Ti, TiW, TiN, Ta, TaN, Cr, and Mo. Ti and / or TiW are preferred materials for adhesion / barrier.

  Referring to FIG. 4AD, then, for example, a desired thickness between about 0.05 micrometers and about 1 micrometer (and an optimum thickness is between 0.1 micrometers and 0.7 micrometers) ) Is formed on the adhesion / barrier layer 22. Similar to the seed layer 170 described above, the material used for the seed layer 38 can vary depending on the material of the metal layer to be subsequently formed. The material of the seed layer 38 can be, for example, Cu, Au, or Ag. In this embodiment, Cu is a preferred seed layer material.

  Referring to FIG. 4AE, a photoresist layer 40 is formed on the seed layer 38, and the photoresist layer 40 is patterned by spin coating, exposure, and development, and a large number of photoresist layer openings are formed in the photoresist layer 40. 40a is formed. Photoresist layer opening 40a separately exposes the portion of seed layer 38 overlying pad 166a and pad 166b.

  Referring to FIG. 4AF, a metal layer 42 is formed on the seed layer 38 by electroplating. This metal layer 42 is in the photoresist layer opening 40a. The metal layer 42 can be made of a material such as gold, copper, silver, palladium, rhodium, ruthenium, or rhenium. The thickness of the metal layer 42 can be between about 1 micrometer and about 100 micrometers, with an optimal preferred thickness being between 1.5 micrometers and 15 micrometers. In this embodiment, the metal layer 42 is preferably a single layer of copper.

  Referring to FIG. 4AG, a metal layer 44 is formed on the metal layer 42 by electroplating. The metal layer 44 is in the photoresist layer opening 40a. The metal layer 44 can be made of nickel. The thickness of the metal layer 44 can have a thickness, for example, between about 0.1 micrometers and about 10 micrometers, as desired, with an optimal preferred thickness of 0.5 micrometers and 5 micrometers. Between micrometer.

  Referring to FIG. 4AH, a metal layer 46 is formed on the metal layer 44 by electroplating, electroless plating, sputtering, or CVD. The metal layer 46 is in the photoresist layer opening 40a. The metal layer 46 can be made of a material such as aluminum, gold, silver, palladium, rhodium, ruthenium, or rhenium. The thickness of the metal layer 46 can be selected as desired, for example, between about 0.03 micrometers and about 5 micrometers. The optimum preferred thickness is between 0.05 and 1.5 micrometers. In this embodiment, the material of the metal layer 46 is preferably a single layer of gold.

Referring to FIG. 4AI, a removal process can be used to remove the patterned photoresist layer 40 and portions of the seed layer 38 and adhesion / barrier layer 22 that are not under the metal layer 46. To remove the seed layer 38 made of copper, the copper can be etched using NH ₃ ⁺ or SO ₄ ²⁺ containing solutions. Dry or wet etching can be used to remove the adhesion / barrier layer 22. Dry etching requires the use of reactive ion etching or argon sputter etching. On the other hand, when using wet etching, if the adhesion / barrier layer 22 is made of a Ti / W alloy, hydrogen peroxide can be used to remove this layer. If the adhesion / barrier layer 22 is made of Ti, this layer can be removed using an HF-containing solution.

  Referring to FIG. 4AJ, external device 310 may be separately connected on / on metal layer 46 above pad 166a. The external device 310 can include a solder layer 300. Alternatively, the solder layer 300 can be formed on the metal layer 46 by a screen printing method. The external device 310 can be mounted on the metal layer 46 through the solder layer 300.

  Referring to FIGS. 4AK to 4AM, FIG. 4AL is a cross-sectional view taken along line 2-2 'in FIG. 4AK, and FIG. 4AM is a cross-sectional view taken along line 2-2 in FIG. 4AK. An external device 320 can be connected on the metal layer 46 on the pad 166ab. The external device 320 is above the external device 310. The external device 320 can have a solder layer 301. Alternatively, the solder layer 301 can be formed on the metal layer 46 by a screen printing method. The external device 320 can be mounted on the metal layer 46 through the solder layer 301.

  Referring to FIG. 4AM, a dicing process can be performed to individualize each chip. Here, the substrate 100 is sawed to obtain a large number of chips. A wire 47 can then be formed by wire bonding on the metal layer 46 overlying the pad 166b, and the wire 47 can be used to connect to an external circuit or power source. The wire 47 can be formed of copper or gold. For example, copper wires or gold wires can be connected to the bonding metal layer 400c (FIG. 4) by wire bonding techniques. In this case, the bonding metal layer 400c is a copper pad, an aluminum pad, an aluminum cap, or a nickel cap. The external devices 310 and 320 can be mounted after performing a dicing procedure on the substrate 100.

Embodiment 3
Referring to FIG. 5, a third embodiment (“Embodiment 3”) is shown. 3rd Embodiment is the same as that of Embodiment 2, and the material and thickness of the connection metal layer 400 differ. In the third embodiment, the solder layer 400 is configured on the pads 166a and 166b. Hereinafter, the formation of the structure of the third embodiment will be described.
Manufacturing method of Embodiment 3:
The third embodiment can be continued from FIG. 4R of the manufacturing method 2 of the second embodiment. Referring to FIG. 5A, a solder layer 400 is formed on the metal layer 44 in the photoresist layer opening 40a by electroplating. The thickness of the solder layer 400 can be selected, for example, between about 30 micrometers and about 350 micrometers, as desired. Preferred materials for the solder layer 400 include tin / silver, tin / copper / silver, and tin / lead alloys.

Referring to FIG. 5B, a removal process can be applied to remove the patterned photoresist layer 40 and portions of the seed layer 38 and adhesion / barrier layer 22 that are not under the solder layer 400. To remove the seed layer 38 made of copper, the copper can be etched using NH ₃ ⁺ or SO ₄ ²⁺ containing solutions.

  Referring to FIG. 5C, a reflow process similar to that previously described for FIG. 4M can be used so that the solder layer 400 reaches the melting point and aggregates into a hemispherical shape as shown.

Referring to FIG. 5D, the external device 310 and the external device 320 are separately mounted on the solder layer 400 above the pad 166a. In this embodiment, external devices 310 and 320 are passive devices. Passive devices include inductors, capacitors, and integrated passive devices. In the present disclosure, external devices 310 and 320 are two different passive devices. For example, the external device 310 may be a capacitor, while the external device 320 may be an inductor. Alternatively, the external device 310 may be an integrated passive device, while the external device 320 may be an inductor.
The dimensions of external devices 310 and 320 may be selected from industry standard dimension 1210, dimension 0603, dimension 0402, or dimension 0201, where dimension 0201 represents 0.02 inch x 0.01 inch, dimension 1210, dimension 0603, And the dimension 0402 can be estimated by the same standard. In general, external devices 310 and 320 can be between 0.2 mm and 5 mm in length, between 0.1 mm and 4 mm in width, and between 0.01 mm and 2 mm in height.

Embodiment 4
Referring to FIG. 6, the first polymer layer 200 can optionally be formed on the passivation layer 160 in the semiconductor chip structure revealed by this embodiment. The first polymer layer 200 can have a desired thickness, for example, a thickness between about 3 micrometers and about 25 micrometers. The polymer layer can be made of one or more suitable materials, such as polyimide (PI), benzocyclobutene (BCB), parylene, epoxy resin, elastomer, and / or porous dielectric material. Hereinafter, the formation of the structure of the fourth embodiment will be described.
Manufacturing method of Embodiment 4:
Referring to FIG. 6A, an integrated circuit 20 is used to represent various structures under the passivation layer 160. Integrated circuit 20 includes substrate 100, devices 110, 112, 114, first dielectric layer 150, metal layer 140, second dielectric layer 155, metal contact 120, and metal via 130 (not shown in FIG. 6). The passivation layer 160 has a number of openings 165 that expose a number of pads 166.

Referring to FIG. 6B, a photosensitive polymer layer 200 having a desired thickness, for example, between about 3 micrometers and about 25 micrometers, can be formed on the passivation layer 160. The polymer layer 200 is patterned by spin coating, exposure and development, and O ₂ plasma ash or etching to form many openings 200a in the polymer layer 200. These openings 200a expose the pads 166. The polymer layer 200 is then heated, for example, to heat the polymer layer 200 to a temperature between about 150 and 390 degrees C. so that the polymer layer 200 hardens. The material example of the polymer layer 200 can be selected from the following. Polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), parylene, epoxy resin or an epoxy-based material such as photoepoxy SU-8 provided by Sotec Microsystems of Renens, Switzerland, or silicone, Or an elastomer such as AL-2000 provided by Asahi glass Co. Alternatively, the polymer layer 200 may be a fluorine-containing polymer having a cure temperature between about 130 and about 200 degrees C, or preferably between 150 and 190 degrees C.

In the example embodiment, the polymer layer 200 is formed by applying a negative photosensitive polyimide layer having a desired thickness, eg, about 6 and about 50 micrometers, onto the passivation layer 160 and the contact pad 166 by spin-on coating. By doing so, it can be formed. The spin-on coated polyimide layer can then be baked and exposed. Exposure of the baked polyimide layer is done in the example embodiment by using a 1X stepper or 1X contact aligner having at least two of the following lines from the mercury vapor lamp. G-line having a wavelength in the range of 434 to 438 nm, h-line having a wavelength in the range of 403 to 407 nm, and i-line having a wavelength in the range of 363 to 367 nm. Next, illuminate the baked polyimide layer with illumination of the desired wavelength, e.g. g-line and h-line, g-line and i-line, h-line and i-line, or g-line, h-line, and i-line. Can do. The exposed polyimide layer can be developed to form a number of openings that expose the contact pads 166. The developed polyimide layer can then be heated or heat treated in a nitrogen or oxygen-free atmosphere, for example, at a temperature between 130 and 400 ° C. for a time between 20 and 150 minutes. The heat-treated polyimide layer can have a thickness between about 3 and about 25 micrometers in example embodiments. Residual polymer material or other contaminants can then be removed from contact pad 166, for example, with an O ₂ plasma or a plasma containing less than 200 PPM fluorine and oxygen. As a result, the polymer layer 200 can be formed on the passivation layer 160, and the opening 200 a formed in the polymer layer 200 exposes the contact pad 166.

  For example, the developed polyimide layer can be heated or heat treated in a nitrogen or oxygen-free atmosphere at a temperature between 180 and 250 ° C. for a period of 20 and 150 minutes. Alternatively, the developed polyimide layer can be heated or heat treated in a nitrogen or oxygen-free atmosphere at a temperature between 250 and 290 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heated or heat treated in a nitrogen or oxygen-free atmosphere at a temperature between 290 and 400 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heated or heat treated in a nitrogen or oxygen-free atmosphere at a temperature between 200 and 390 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heated or heat treated in a nitrogen or oxygen-free atmosphere at a temperature between 130 and 220 ° C. for a time between 20 and 150 minutes.

In other embodiments, the polymer layer 200 is spin-on coated with a positive photosensitive polybenzoxazole layer having a thickness between about 3 and about 25 micrometers on the passivation layer 160 and the contact pad 166. Can be formed. The spin-on coated polybenzoxazole layer can then be baked and exposed. For exposing the baked polybenzoxazole layer, the g-line has a wavelength in the range of 434 to 438 nm, the h-line has a wavelength in the range of 403 to 407 nm, and the i-line has a wavelength in the range of 363 to 367 nm. It may include using a 1X stepper or 1X contact aligner with at least two. Subsequent illumination of the baked polybenzoxazole layer can include g and h line, g and i line, h and i line, or g, h and i line illumination. The exposed polybenzoxazole layer can then be developed to form a number of openings that expose the contact pads 166. The developed polybenzoxazole layer is then subjected to, for example, a temperature between about 150 and about 250 ° C, preferably between 180 and 250 ° C, or between 200 and 300 ° C, preferably 250 and 350 °. Heating or heat treatment can be performed in a nitrogen or oxygen-free atmosphere at a temperature between C for a time between about 5 and 180 minutes, preferably between 30 and 120 minutes. The heat treated polybenzoxazole layer preferably has a thickness between about 3 and about 25 μm. For example, residual polymer material or other contaminants can be removed from contact pad 166 by O ₂ plasma or plasma containing less than 200 PPM fluorine and oxygen. As a result, the polymer layer 200 can be formed on the passivation layer 160, and the opening 200a exposing the contact pad 166 can be formed in the polymer layer 200.

  Referring to FIG. 6C, the adhesion / barrier layer 48 can be formed on the polymer layer 200 and the pad 166 by a sputtering method. The thickness of the adhesion / barrier layer 48 is preferably between about 0.1 micrometers and about 1 micrometer with the optimum thickness being between 0.2 micrometers and 0.5 micrometers. The material of the adhesion / barrier layer 48 can be Ti, TiW, TiN, Ta, TaN, or a composite of the above materials.

  Referring to FIG. 6D, a seed layer 50 is shown. The seed layer is of a suitable thickness, for example, between about 0.05 micrometers and about 1 micrometer (preferred thickness is between 0.08 micrometers and 0.5 micrometers). Can have. A seed layer 50 layer is formed over the adhesion / barrier layer 48. In this embodiment, the material of the seed layer 50 is preferably gold (Au), but the material of the seed layer 50 is a metal layer to be formed later, as in the description of the seed layer 170 above. Depending on the material, it can vary.

  Referring to FIG. 6E, a photoresist layer 52 is formed on the seed layer 50, and a patterned photoresist layer 52 is formed by spin coating, exposure, and development. There are a number of photoresist openings 52 a on the photoresist layer 52 that expose the seed layer 50 on the pad 166.

  Referring to FIG. 6F, a metal layer 220 is formed on the seed layer 50 in the photoresist layer opening 52a by electroplating, electroless plating, sputtering, or CVD. The material of the metal layer 220 includes aluminum, gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium, or nickel, and may have a single metal layer structure or a multiple metal layer structure. The thickness of the metal layer 42 can be between about 2 micrometers and about 25 micrometers, with an optimal preferred thickness being between 3 micrometers and 10 micrometers. The structure of the metal layer 220 can include combinations such as Cu / Ni / Au, Cu / Au, Cu / Ni / Pd, and Cu / Ni / Pt when formed as a multiple metal layer structure. In this embodiment, the metal layer 220 is preferably a single gold layer.

Referring to FIG. 6G, the removal process can be applied to the patterned photoresist layer 52 and portions of the seed layer 50 and adhesion / barrier layer 48 that are not under the metal layer 220. If the seed layer 50 is made of gold, the seed layer 50 can be removed by using a solution of I ₂ and KI. On the other hand, when the material of the adhesion / barrier layer 48 is TiW, the adhesion / barrier layer 48 can be removed using hydrogen peroxide (H ₂ O ₂ ). The portions of seed layer 50 and adhesion / barrier layer 48 that underlie metal layer 220 correspond to reference numeral 210 in FIG.

Referring to FIG. 6H, a photosensitive polymer layer 230 can be formed having a desired thickness, eg, between about 3 micrometers and about 25 micrometers. Many openings 240a can be formed in the polymer layer 230 by spin coating, exposure, development, and O ₂ plasma ash or etching. These openings 240a expose the metal layer 220. The polymer layer 230 can then be heated and heat treated. A suitable heat treatment process can proceed at a temperature between about 150 and about 380 degrees Celsius. The material of the polymer layer 230 is polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), parylene, epoxy resin or epoxy such as photoepoxy SU-8 provided by Sotec Microsystems of Renens, Switzerland. The material can be selected from silicones or elastomers such as AL-2000 provided by Asahi glass Co. Alternatively, the polymer layer 230 may be a fluorine-containing polymer with a curing temperature between about 130 and about 200 degrees C, or preferably between 150 and 190 degrees C.

The polymer layer 230 can be formed by spin-on coating a negative photosensitive polyimide layer having a thickness of 6 and about 50 micrometers on the polymer layer 200 and the metal layer 220. The spin-on coated polyimide layer can then be baked and exposed. To expose the baked polyimide layer, at least two of g-line having a wavelength in the range of 434 to 438 nm, h-line having a wavelength in the range of 403 to 407 nm, and i-line having a wavelength in the range of 363 to 367 nm. Using a 1X stepper or 1X contact aligner with two. The baked polyimide layer can then be illuminated. Illuminating the baked polyimide layer can include g-line and h-line, g-line and i-line, h-line and i-line, or g-line, h-line, and i-line illumination of the baked polyimide layer. . The exposed polyimide layer can then be developed to form a number of openings that expose the metal layer 220. The developed polyimide layer can then be heated or heat treated, for example, at a temperature between about 130 ° C. and about 400 ° C. for a time between 20 and 150 minutes in a nitrogen or oxygen-free atmosphere. The heat-treated polyimide layer can have a thickness between about 3 and about 25 micrometers in example embodiments. The remaining polymer material or other contaminants can then be removed from the exposed metal layer 220, for example, by an O ₂ plasma or a plasma containing less than 200 PPM fluorine and oxygen.

  The polymer layer 230 can be formed on the polymer layer 200 and the metal layer 220, and the opening 240 a formed in the polymer layer 230 can expose the metal layer 220. For example, the developed polyimide layer can be heated or heat treated in a nitrogen or oxygen-free atmosphere at a temperature between 180 and 250 ° C. for a period of 20 and 150 minutes. Alternatively, the developed polyimide layer can be cured or heated in a nitrogen or oxygen-free atmosphere at a temperature between 250 and 290 ° C. for a period of 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 290 and 400 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 200 and 390 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 130 and 220 ° C. for a time between 20 and 150 minutes.

The polymer layer 230 can be formed by spin-on coating a positive photosensitive polybenzoxazole layer having a thickness between 3 and 25 micrometers on the polymer layer 200 and the metal layer 220. The spin-on coated polybenzoxazole layer can then be baked and subsequently exposed. To expose the baked polybenzoxazole layer, at least of g having a wavelength in the range of 434 to 438 nm, h-line having a wavelength in the range of 403 to 407 nm, and i-line having a wavelength in the range of 363 to 367 nm. Using a 2X 1X stepper or 1X contact aligner can be included. The baked layer can then be illuminated. Illuminating the baked polybenzoxazole layer can include g-line and h-line, g-line and i-line, h-line and i-line, or g-line, h-line, and i-line illuminations. The exposed polybenzoxazole layer can then be developed to form a number of openings that expose the metal layer 220. Next, a heat treatment or heating of the developed polybenzoxazole layer is performed, for example, at a temperature between about 150 and about 250 ° C, preferably between 180 and 250 ° C, or between about 200 and about 400 ° C. It can be carried out at a temperature preferably between 250 and 350 ° C. for a time between about 5 and about 180 minutes, preferably between 30 and 120 minutes in a nitrogen or oxygen-free atmosphere. In example embodiments, the heat-treated polybenzoxazole layer can have a thickness between about 3 and about 25 μm. Residual polymeric material or other contaminants can be removed from the exposed metal layer 220 by a suitable process. For example, O ₂ plasma or plasma containing less than 200 PPM fluorine and oxygen is used. As a result, the polymer layer 230 can be formed on the metal layer 220 and the polymer layer 200, and the opening 240a exposing the metal layer 220 can be formed in the polymer layer 230.

  Still referring to FIG. 6H, the metal layer 220 exposed by the opening 240a can form a number of pads 220a and a single wire bonding pad 220b. The pad 220a can be used to connect to the external device 310 and the external device 320, and the wire bonding pad 220b can be connected to an external circuit or a power source through a wire formed by a wire binding method. In this embodiment, external devices 310 and 320 may be passive devices. Passive devices include inductors, capacitors, and integrated passive devices. In the present disclosure, external devices 310 and 320 are two different passive devices. For example, the external device 310 may be a capacitor, while the external device 320 may be an inductor. Alternatively, the external device 310 may be an integrated passive device, while the external device 320 may be an inductor. The dimensions of external devices 310 and 320 may be selected from industry standard dimension 1210, dimension 0603, dimension 0402, or dimension 0201, where dimension 0201 represents 0.02 inch x 0.01 inch, dimension 1210, dimension 0603, And the dimension 0402 can be estimated by the same standard. In general, external devices 310 and 320 can be between 0.2 mm and 5 mm in length, between 0.1 mm and 4 mm in width, and between 0.01 mm and 2 mm in height.

  Referring to FIG. 6I, external device 310 and external device 320 may be separately connected to pad 220a. External devices 310 and 320 can include a solder layer 400 having a thickness between 30 and 350 micrometers, Sn / Ag, Sn / Cu / Ag, Sn / Au alloy, or other related It can be made of materials such as materials. The solder layer 400 can be provided by a screen printing process instead of being included in an external device. External devices 310 and 320 can be connected to pads 220a through solder layer 400 by using surface mount technology.

The next step can include a dicing procedure where the substrate 100 is sawed to obtain multiple chips. Next, the wire 56 is formed on the wire bonding pad 220b by wire bonding, and the wire 56 is used to connect the wire bonding pad 220b to an external circuit or a power source. The wire 56 can be formed of copper or gold. For example, a copper or gold wire can be connected to the wire bonding pad 220b by wire bonding techniques. In this case, the wire bonding pad 220b is a copper pad, an aluminum pad, an aluminum cap, or a nickel cap. Further, the external devices 310 and 320 can be mounted by using a surface mounting technique after the dicing procedure is performed on the substrate 100.
Embodiment 5
Referring to FIG. 7A, the pad metal 166 of the circuit structure in the four embodiments described above can be made of aluminum. In the fifth embodiment of the present disclosure (“Embodiment 5”), the pad metal 166 can be made of copper. When the pad metal 166 is made of copper, it protects the pad 166 exposed by the opening in the passivation layer 160 so that the pad 166 is not damaged by oxidation and later withstands in processes such as wire bonding and flip chip. It may be desirable to include a metal cap layer 170 so that the The metal cap layer 170 can be an aluminum-copper layer, a gold layer, a titanium (Ti) layer, a titanium-tungsten alloy layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, or a nickel (Ni) layer. . If the metal cap is an aluminum-copper layer, a barrier layer (not shown) can be formed between the copper pad 166 and the metal cap layer 170. In example embodiments, the barrier layer can be titanium, titanium-tungsten alloy, titanium nitride, tantalum, tantalum nitride, chromium, or nickel.
The fabrication of the under bump metal structure and the mounting of the external device in FIG. 7A can be the same as described for the fourth embodiment.

Embodiment 6
Referring to FIG. 7B, a sixth embodiment (“Embodiment 6”) of the present disclosure is shown. The difference between the sixth embodiment and the first to fifth embodiments is that the external device is integrated into one external device 330. For example, the external device 330 may be a capacitor and inductor integrated passive device. Except for the external device 330, the manufacturing process and materials are all the same as those of the first to fifth embodiments. Therefore, the manufacturing process and materials for the same device will not be repeated.

  All of the semiconductor chip structures described in the previous six embodiments can be packaged in a ball grid array (BGA) as shown in FIGS. 8 to 11 reveal the packaging structure of a semiconductor chip package structure having only one semiconductor device.

  8 shows the chip structure of the present disclosure, for example, the first embodiment shown in FIG. 3, the second embodiment shown in FIG. 4, the fourth embodiment shown in FIG. 6, and / or the fifth embodiment shown in FIG. 7A. A packaging structure useful for housing or packaging is shown. The packaging structure of FIG. 8 includes an integrated circuit 20 (100) that is electrically connected to the BGA substrate 500 through wires 510. Further, as shown in the figure, the above-described chip device can be sealed with a molding material 520. The illustrated BGA substrate 500 has a large number of solder balls 530, and is electrically connected to an external circuit through these solder balls 530.

  FIG. 9 shows another embodiment of a packaging structure useful for holding or packaging a chip package according to embodiment 3 shown in FIG. The integrated circuit 20 (100) is electrically connected to the BGA substrate 500 through the solder layer 400a. Then, the aforementioned device is sealed with a molding material 520, and the BGA substrate 500 is electrically connected to an external circuit through a solder ball 530. Molding material 520 can be a polymer such as an epoxy resin or a polyimide composite.

  In FIGS. 10 and 11, the external devices 310 and 320 in FIGS. 8 and 9 have been replaced by integrated passive devices 330 (as in Embodiment 6). In FIG. 10, the integrated circuit 20 (100) is electrically connected to the BGA substrate 500 through the wire 510, and in FIG. 11, the integrated circuit 20 (100) is electrically connected to the BGA substrate 500 through the solder layer 400a. ing.

  In addition to the BGA packaging structure described above, the present disclosure includes a thin small outline package (“TSOP”), a small outline J-lead (“SOJ”), a quad flat package (“QFP”), a thin Common packaging formats such as quad flat package ("TQFP") or other widely popular lead frame packaging configurations can be accommodated or adapted. As shown in FIGS. 12A-12F and 13A-13F, the integrated circuit 20 (100) may be configured on a lead frame 600. FIG. The lead frame 600 can be made of copper or a copper alloy and can have a thickness between about 100 micrometers and about 2000 micrometers.

  12A to 12C show packaging structures suitable for packaging the chip structure according to Embodiment 1 of FIG. 3, Embodiment 2 of FIG. 4, Embodiment 4 of FIG. 5, and Embodiment 5 of FIG. 6A. Show. As shown in FIGS. 12A to 12C, the integrated circuit 20 (100) is electrically connected to the lead frame 600 through the wire 610. The device described above is then encapsulated with the molding material 620, exposing the leads of the lead frame 600. These leads are then connected to external circuitry.

12D-12F, external devices 310 and 320 in FIGS. 12A-12C are replaced by integrated device 330 (as in embodiment 6).
13A to 13C show another packaging structure of the third embodiment shown in FIG. The integrated circuit 20 (100) is electrically connected to the lead frame 600 through the solder layer 400b, and the aforementioned device is then sealed by the molding material 620, but exposing the leads of the lead frame 600. . These leads are then connected to external circuitry. The molding material 620 is a polymer such as an epoxy resin or a polyimide composite.

  In FIGS. 13D-13F, external devices 310 and 320 in FIGS. 14A-14C are replaced by integrated device 330 (as in embodiment 6).

  The description up to this point was about the semiconductor chip structure. The application circuit corresponding to the semiconductor chip structure will be described and explained below. Application circuits include internal circuits, external circuits, and metal connections, all of which are integrated on a single semiconductor chip.

  In FIG. 14, a simplified equivalent circuit is shown. A voltage feedback device 1112 and a switch circuit including a switch controller 1114a and switch MOSs 1114b, 1114e are shown in FIG. Inductor 1320 and capacitor 1310 are also shown in FIG. 14, where inductor 1320 and capacitor 1310 are connected, and voltage feedback device 1112 is electrically connected between inductor 1320 and capacitor 1310. The voltage feedback device 1112 can feed back a voltage signal between the inductor 1320 and the capacitor 1310.

  In the circuit revealed by FIG. 14, power input 1311 inputs power to MOS 1114b using wire bonds / leads or solder layers on the contact pads of the semiconductor chip. The MOS 1114b is under the passivation layer of the semiconductor chip. The feedback device 1112 then takes a voltage signal that passes between the inductor 1320 and the capacitor 1310 and this voltage signal is sent back to the switch controller 1114a. Next, the switch controller 1114a uses this signal to determine the on and off timings of the two MOSs 1114b and 1114e located on the semiconductor chip. This allows switch controller 1114a to regulate the duty cycle of MOSs 1114b and 1114e and thus regulate the voltage at output 1313. In this disclosure, inductor 1320, capacitor 1310, switch controller 1114a, and voltage feedback device 1112 form a voltage regulator or converter. Therefore, according to the different operating voltage range of the semiconductor chip, the voltage regulator integrated with the semiconductor chip immediately regulates the voltage using the mechanism explained above and transfers the power to the semiconductor chip using the shortest transfer path In addition, it becomes possible to quickly regulate the voltage level of the power source of the semiconductor chip to a specific voltage range. The MOS 1114b can be replaced with a DMOS, LDMOS, or bipolar transistor. The MOS 1114e can also be replaced with a DMOS, LDMOS, or bipolar transistor. The voltage feedback device 1112 may also feature a dynamic voltage scaling function. The switch controller 1114a may comprise a pulse-frequency-modulator or a pulse-width-modulator to control the duty cycle, and the modulation frequency of the switch controller 1114a suitable for duty cycle control is 1 KHz. And between 300 MHz and preferably between 1 MHz and 100 MHz.

  Further, according to the electric circuit structure shown in FIG. 14 and the semiconductor chip structure disclosed by the present disclosure, all the passive components in the present disclosure are integrated on the semiconductor substrate together with the active device, and therefore, a large number of the passive components are disclosed. The electronic devices can be easily connected to each other.

  FIG. 15 shows an equivalent circuit of a large number of passive devices and semiconductor chips connected to each other. All switch MOSs 1114f, 1114h, 1114j, 1114g, 1114i, 1114k, and inductors 1320a, 1320b, and 1320c , Voltage feedback device 1112 and switch controller 1114a. Thus, when input pad 1110 receives power, voltage feedback device 1112 captures the voltage signal between inductors 1320a, 1320b, 1320c and capacitor 1310 and sends the voltage feedback signal to switch controller 1114a. The switch controller 1114a then determines separately when to switch the MOSs 1114f, 1114g, 1114h, 1114i, 1114j, 1114k on or off. The switch controller 1114a finely adjusts the voltage level at the output 1313 by controlling the duty cycle and on-off phase of the MOSs 1114f, 1114g, 1114h, 1114i, 1114j, 1114k. When the switch controller 1114a controls the MOSs 1114f, 1114g, 1114h, 1114i, 1114j, 1114k, at least two different on-off phases occur.

  As shown in FIG. 16, as a result of the output of the circuit of FIG. 15 when different switching phases are set for each switch MOS, the output voltage ripple is minimized by the different on-off phases of the switching MOS. Therefore, the embodiment of the present disclosure provides a semiconductor chip in which the power supply voltage is further stabilized. All of the MOSs 1114f, 1114h, 1114j, 1114g, 1114i, 1114k can be replaced with DMOS, LDMOS, or bipolar transistors.

Embodiment 7
17A-17L show the manufacturing process of an on-chip regulator or converter with inductor and capacitor, where the inductor is made by using a post-passivation embossing process, where the capacitor is Attached by using surface mount technology.

  Referring to FIG. 17A, the integrated circuit 20 represents all the structures underlying the passivation layer 160. In addition, the semiconductor circuit 20 includes a substrate 100, devices 110, 112, and 114, a first dielectric layer 150, a metal layer 140, a second dielectric layer 155, a metal contact 120, and a metal via 130 (see, for example, FIG. 7A). As shown, multiple passivation layer openings 165a in the passivation layer 160 expose multiple pads 166a, 166b, and 166c.

  Referring to FIG. 17B, an adhesion / barrier layer 401 is formed on the passivation layer 160 and the contact pads 166a, 166b, and 166c by sputtering. The thickness of the adhesion / barrier layer 401 can be between about 0.1 micrometers and about 1 micrometer, with a preferred optimal thickness being between 0.3 micrometers and 0.8 micrometers. . The material of the adhesion / barrier 401 is preferably TiW or Ti or Ti / TiW.

  Referring to FIG. 17C, a desired thickness, for example, a thickness between about 0.05 micrometers and about 1 micrometer (a preferred optimal thickness is between 0.08 micrometers and 0.7 micrometers). The seed layer 402 is formed. The seed layer 402 can be formed on the adhesion / barrier layer 401 by sputtering. In this embodiment, seed layer 402 is preferably made of gold. However, as described above, the material of the seed layer 402 can vary according to the material of the metal layer that will be formed later.

  Referring to FIG. 17D, a photoresist layer 404 is formed on the seed layer 402, and patterned by spin coating, exposure, and development, and the photoresist layer 404 has a number of photoresist layer openings 404a. Form. Photoresist layer opening 404a separately exposes the portion of seed layer 402 overlying pads 166a, 166b, and 166c.

  Referring to FIG. 17E, a bonding metal layer 406 is formed on the seed layer 402 by electroplating, electroless plating, sputtering, or CVD. The bonding metal layer 406 is in the photoresist layer opening 404a. The bonding metal layer 406 is made of a material such as aluminum, gold, copper, silver, palladium, rhodium, ruthenium, rhenium, or nickel, and may have a single metal layer structure or a multiple metal layer structure. The thickness of the bonding metal layer 406 is selected as desired, for example, between about 1 micrometer and about 100 micrometers, with an optimal preferred thickness being between 1.5 micrometers and 15 micrometers. is there. Combinations of multiple metal layer structures can include Cu / Ni / Au, Cu / Au, Cu / Ni / Pd, and Cu / Ni / Pt. In this embodiment, the bonding metal layer 406 is preferably a single layer made of gold.

Referring to FIG. 17F, a removal process can be applied to remove the patterned photoresist layer 404 and portions of the seed layer 402 and adhesion / barrier layer 401 that are not under the metal layer 406. The portion of seed layer 402 made of gold can be removed by using a solvent containing I ₂ and KI solutions. On the other hand, when the material of the adhesion / barrier layer 401 is TiW, the adhesion / barrier layer 401 can be removed using a solvent containing hydrogen peroxide (H ₂ O ₂ ).

  Referring to FIG. 17G, after removing the patterned photoresist layer 404 and portions of the seed layer 402 and the adhesion / barrier layer 401 that are not under the metal layer 406, the bonding metal layer 406 includes one inductor device 408, A number of wire bonding pads 410 and a number of contact pads 412 are formed on the passivation layer 160 at least. Wire bond pad 410 is formed on pad 166a, while contact pad 412 is formed on pad 166c, and inductor device 408 is formed on passivation layer 160 and pad 166b. FIG. 17F is a cross-sectional view of FIG. 17G along the horizontal line 2-2. As shown in FIG. 17H, a number of inductor devices 408 can be formed on or over the passivation layer 160, but only one inductor device 408 is shown in the view of FIG. 17F.

  Referring to FIGS. 17I and 17J, a number of wire bonding pads 410, a number of contact pads 412, and a passivation may be achieved by processes including spin-on coating processes, lamination processes, screen printing processes, or spray processes. A polymer layer 414 can be formed over the layer 160 and the inductor 408, with multiple openings in the polymer layer 414 above the pad 410, exposing the pads 410 and 412. The polymer layer 414 can have a thickness as desired, for example, between about 3 and about 25 micrometers, and preferably between 5 and 15 micrometers, The material can include benzocyclobutane (BCB), polyimide (PI), polybenzoxazole (PBO), or epoxy resin.

Referring to FIG. 17J, a polymer layer 414 is formed by spin coating, exposure and development, etching, and O ₂ plasma ash, and patterned to form a number of openings 414a. These openings 414a expose a number of wire bonding pads 410, a number of contact pads 412 and cover the inductor device 408. The polymer layer 414 is then heat treated to a temperature between 150 and 380 degrees Celsius. The material of the polymer layer 414 is an epoxy such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), parylene, epoxy resin or photoepoxy SU-8 provided by Sotec Microsystems of Renens, Switzerland. The material can be selected from silicones or elastomers such as AL-2000 provided by Asahi glass Co. When the polymer layer 414 is made of polyimide, it is preferably an ester type polyimide. The polymer layer 414 is preferably photosensitive so that the polymer layer 414 can be patterned using lithography. The polymer layer 414 can have a desired thickness, for example, between about 5 micrometers and about 50 micrometers, with an optimal preferred thickness being between 10 micrometers and 20 micrometers. Alternatively, the polymer layer 414 may be a fluorine-containing polymer with a curing temperature between about 130 and about 200 degrees C, or preferably between 150 and 190 degrees C.

Depending on the application, a negative photosensitive polyimide layer having a thickness between 6 and 150 micrometers may be spin-on coated on the wire bonding pad 410, contact pad 412, passivation layer 160, and inductor 408. In some cases, the polymer layer 414 may be formed. The spin-on coated polyimide layer can then be baked and exposed. To expose the baked polyimide layer, at least two of g-line having a wavelength in the range of 434 to 438 nm, h-line having a wavelength in the range of 403 to 407 nm, and i-line having a wavelength in the range of 363 to 367 nm. Using a 1X stepper or 1X contact aligner with two. The baked polyimide layer can then be illuminated. Illuminating the baked polyimide layer can include g-line and h-line, g-line and i-line, h-line and i-line, or h-line and i-line illumination of the baked polyimide layer. The exposed polyimide layer can then be developed to form a number of openings that expose the pads 410 and 412. The polyimide layer can then be heat treated or heated. Heat treatment or heating of the developed polyimide layer can be performed, for example, at a temperature between 130 and 400 ° C. for a time between 20 and 150 minutes in a nitrogen or oxygen-free atmosphere. The heat-treated polyimide layer can have a thickness between about 3 and about 25 micrometers in example embodiments. The remaining polymer material or other contaminants can then be removed from pads 410 and 412 by, for example, an O ₂ plasma or a plasma containing less than 200 PPM fluorine and oxygen.

  A polymer layer 414 can be formed over the passivation layer 160 and the inductor 408, and an opening 414 a formed in the polymer layer 414 can expose the pads 410 and 420. For example, the developed polyimide layer can be heated or heat treated in a nitrogen or oxygen-free atmosphere at a temperature between 180 and 250 ° C. for a period of 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 250 and 290 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 290 and 400 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 200 and 390 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 130 and 220 ° C. for a time between 20 and 150 minutes.

In other applications, the polymer layer 414 comprises a positive photosensitive polybenzoxazole layer having a thickness between about 3 and about 25 micrometers, a wire bonding pad 410, a contact pad 412, a passivation layer 160, And by spin-on coating on inductor 408. The spin-on coated polybenzoxazole layer can then be baked and exposed. To expose the baked polybenzoxazole layer, g-line having a wavelength in the range of 434 to 438 nm, h-line having a wavelength in the range of 403 to 407 nm, and i-line having a wavelength in the range of 363 to 367 nm. It may include using a 1X stepper or 1X contact aligner with at least two. The baked layer can then be illuminated. Illuminating the baked polybenzoxazole layer can include g-line and h-line, g-line and i-line, h-line and i-line, or g-line, h-line, and i-line illuminations. The exposed polybenzoxazole layer can then be developed to form a number of openings that expose pads 410 and 412. The developed polybenzoxazole layer can then be heated or heat treated. For example, the heating or heat treatment is performed at a temperature between about 150 and about 250 ° C, preferably between 180 and 250 ° C, or between 200 and 400 ° C, preferably between 250 and 350 ° C. A time between about 5 and 180 minutes, preferably between 30 and 120 minutes, in a nitrogen or oxygen-free atmosphere. In example embodiments, the heat-treated polybenzoxazole layer can have a thickness between about 3 and about 25 μm. For example, residual polymer material or other contaminants can be removed from pads 410 and 412 by O ₂ plasma or plasma containing less than 200 PPM fluorine and oxygen. As a result, a polymer layer 414 can be formed over the passivation layer 160 and the inductor 408, and an opening 414 a exposing the pads 410 and 412 can be formed in the polymer layer 414.

  Referring to FIGS. 17K and 17L, the substrate 100, the passivation layer 160, and the polymer layer 414 can be cut using a dicing procedure to obtain a large number of semiconductor chips 600. A number of wire bonding pads 410 on the semiconductor chip 600 can be connected to an external circuit or power source through wires 416 formed by a wire bonding process. The wire 416 can be formed of copper or gold. For example, a copper or gold wire can be connected to the wire bonding pad 410 by wire bonding techniques. In this case, the wire bonding pad 410 is a copper pad, an aluminum pad, an aluminum cap, or a nickel cap. The solder layer 420 can then connect the contact pads 412 to the capacitor device 418 using surface mount techniques (SMT), which pass through the metal layer 140 in the integrated circuit 20 and the inductor. Connected to device 408 Of course, a dicing procedure can also be performed after mounting the capacitor.

Manufacturing method and structure 1 of Embodiment 8
18A to 18M show a manufacturing process of another on-chip regulator or converter having an inductor and a capacitor according to the eighth embodiment of the present disclosure (“Embodiment 8”). Inductors are made by using a post-passivation embossing process, and capacitors are attached by using surface mount technology.

  Referring to FIG. 18A, the integrated circuit 20 represents all the structures underneath the passivation layer 160. The semiconductor circuit 20 also includes a substrate 100, devices 110, 112, and 114, a first dielectric layer 150, a metal layer 140, a second dielectric layer 155, a metal contact 120, and a via 130 (eg, as shown in FIG. 7A). And a number of passivation layer openings 165a in the passivation layer 160 expose a number of pads 166a, 166b, and 166c.

Referring to FIG. 18B, a polymer layer 421 can be formed on the passivation layer 160 and the pads 166a, 166b, and 166c. A polymer layer 421 is formed by spin coating, exposure and development, etching, and O ₂ plasma ash, and is patterned to form a number of openings 421a. These openings 421a expose a number of pads 166a, 166b, and 166c. The polymer layer 421 is then heat treated, for example, at a temperature between about 150 and 380 degrees Celsius. The material of the polymer layer 421 is polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), parylene, epoxy resin or epoxy such as photoepoxy SU-8 provided by Sotec Microsystems of Renens, Switzerland. The material can be selected from silicones or elastomers such as AL-2000 provided by Asahi glass Co. When the polymer layer 421 is made of polyimide, it is preferably an ester type polyimide. The polymer layer 421 is preferably photosensitive so that the polymer layer 421 can be patterned using lithography. The polymer layer 421 can have a desired thickness, for example, between about 5 micrometers and about 50 micrometers, with an optimal preferred thickness being between 10 micrometers and 25 micrometers. Alternatively, the polymer layer 421 may be a fluorine-containing polymer with a curing temperature between about 130 and about 200 degrees C, and preferably between 150 and 190 degrees C.

In some applications, a negative photosensitive polyimide layer having a thickness between 6 and 50 micrometers is spin-on coated on the passivation layer 160 and pads 166a, 166b, and 166c to form the polymer layer 421. Sometimes you can do it. The spin-on coated polyimide layer can then be baked and exposed. To expose the baked polyimide layer, at least two of g having a wavelength in the range of 434 to 438 nm, h-line having a wavelength in the range of 403 to 407 nm, and i-line having a wavelength in the range of 363 to 367 nm. Using a 1X stepper or a 1X contact aligner. The baked polyimide layer can then be illuminated. Illuminating the baked polyimide layer can include g-line and h-line, g-line and i-line, h-line and i-line, or g-line, h-line, and i-line illuminations. Next, the exposed polyimide layer can be developed to form a number of openings that expose the pads 166a, 166b, 166c. The polyimide layer can then be heat treated or heated. Heat treatment or heating of the developed polyimide layer can include using a temperature between 130 and 400 ° C. in a nitrogen or oxygen-free atmosphere for a time between 20 and 150 minutes. In example embodiments, the heat-treated polyimide layer can have a thickness between about 3 and about 25 micrometers. The remaining polymer material or other contaminants can then be removed from the pads 166a, 166b, 166c, for example, with an O ₂ plasma or a plasma containing less than 200 PPM fluorine and oxygen. In this manner, the polymer layer 412 can be formed on the passivation layer 160, and the opening 421a formed in the polymer layer 421 exposes the pads 166a, 166b, 166c.

  As an example of the heat treatment process of Embodiment 8, the developed polyimide layer can be heated or heat treated in a nitrogen or oxygen-free atmosphere at a temperature between 180 and 250 ° C. for a time between 20 and 150 minutes. . Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 250 and 290 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 290 and 400 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 200 and 390 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 130 and 220 ° C. for a time between 20 and 150 minutes.

In other applications, the polymer layer 421 can be formed by applying a positive photosensitive polybenzoxazole layer having a thickness between about 3 and about 25 micrometers on the passivation layer 160 and the pads 166a, 166b, and 166c. It can be formed by coating. The spin-on coated polybenzoxazole layer can then be baked. The spin-on coated polybenzoxazole layer can be baked and then exposed. To expose the baked polybenzoxazole layer, g-line having a wavelength in the range of 434 to 438 nm, h-line having a wavelength in the range of 403 to 407 nm, and i-line having a wavelength in the range of 363 to 367 nm. It may include using a 1X stepper or 1X contact aligner with at least two. The baked layer can then be illuminated. Illuminating the baked polybenzoxazole layer includes, for example, g- and h-line, g- and i-line, h- and i-line, or g-line, h-line and i-line illumination from a mercury lamp be able to. The exposed polybenzoxazole layer can then be developed to form a number of openings that expose the pads 166a, 166b, and 166c. Next, heat treatment can be performed. To heat or heat-treat the developed polybenzoxazole layer, a temperature between about 150 and about 250 ° C, preferably between 180 and 250 ° C, or between 200 and 300 ° C, preferably 250 and 350 It can be carried out at a temperature between 0 ° C. for a time between about 5 and 180 minutes, preferably between 30 and 120 minutes, in a nitrogen or oxygen-free atmosphere. The heat treated polybenzoxazole layer preferably has a thickness between about 3 and about 25 μm. For example, residual polymer material or other contaminants can be removed from pads 166a, 166b, and 166c by O ₂ plasma or plasma containing less than 200 PPM fluorine and oxygen. By this process, a polymer layer 421 can be formed on the passivation layer 160, and an opening 421a exposing the pads 166a, 166b, and 166c can be formed in the polymer layer 421.

  Referring to FIG. 18C, the adhesion / barrier layer 422 can be formed by sputtering on the polymer layer 421 and the pads 166a, 166b, 166c. The thickness of the adhesion / barrier layer 422 can be between about 0.1 micrometers and about 1 micrometer with a preferred optimal thickness being between 0.3 micrometers and 0.8 micrometers. . The material of the adhesion / barrier layer 422 includes titanium, titanium-tungsten alloy, titanium nitride, chromium, tantalum, tantalum nitride, or a composite of the aforementioned materials. The material of the adhesion / barrier 422 is preferably TiW or Ti or Ti / TiW.

  Referring to FIG. 18D, for example, a seed layer having a thickness between about 0.05 micrometers and about 1 micrometer (preferred thickness is between 0.08 micrometers and 0.7 micrometers). 424 is then formed on the adhesion / barrier layer 422 by sputtering. In this embodiment, the material from which the seed layer 424 is made is preferably gold. However, as described above, the material of the seed layer 424 can vary depending on the material of the metal layer that is subsequently formed thereon.

  Referring to FIG. 18E, a photoresist layer 426 is formed on the seed layer 424, and the photoresist layer 426 is patterned by spin coating, exposure, and development, and a plurality of photoresist layer openings 426a are formed in the photoresist layer 426. Form. Photoresist layer opening 426a separately exposes the portion of seed layer 424 overlying pads 166a, 166b, and 166c.

  Referring to FIG. 18F, a bonding metal layer 428 is formed on the seed layer 424 in the photoresist layer opening 426a by electroplating, electroless plating, sputtering, or CVD. The bonding metal layer 428 can be made of aluminum, gold, copper, silver, palladium, rhodium, ruthenium, rhenium, and / or nickel and can have a single metal layer structure or a multiple metal layer structure. The thickness of the bonding metal layer 428 can be, for example, between about 1 micrometer and about 100 micrometers, with an optimal preferred thickness being between about 1.5 micrometers and about 15 micrometers. . Layer 428 can be made of a combination of multiple metal layers forming a multi-layered structure such as Cu / Ni / Au, Cu / Au, Cu / Ni / Pd, and Cu / Ni / Pt. In this embodiment, the bonding metal layer 428 is preferably a single layer of gold.

Referring to FIG. 18G, a removal process can be applied to the patterned photoresist layer 426 and portions of the seed layer 424 and the adhesion / barrier layer 422 that are not under the metal layer 428. If the seed layer 424 is made of gold, the seed layer 424 can be removed by using a solution of I ₂ and KI. On the other hand, when the material of the adhesion / barrier layer 422 includes TiW, the adhesion / barrier layer 422 can be removed by using a solvent containing hydrogen peroxide (H ₂ O ₂ ).

  Referring to FIG. 18H, after removing the patterned photoresist layer 426 and portions of the seed layer 424 and the adhesion / barrier layer 422 that are not under the metal layer 428, the bonding metal layer 428 may include one or more inductor devices. 430 (only one shown), multiple wire bond pads 432, and multiple contact pads 434 can be formed on the polymer layer 421. Wire bond pad 432 is formed on pad 166a, while contact pad 434 is formed on pad 166c, and inductor device 430 is formed on or above passivation layer 160 and pad 166b. 18G is a cross-sectional view of FIG. 18H in the direction of the cut plane indicated by horizontal line 2-2. A number of inductor devices 430 can also be formed on the polymer 421 as shown in FIG.

  Referring to FIG. 18J, polymer layer 436 is formed over inductor device 430, multiple wire bonding pads 432, multiple contact pads 434, and polymer layer 421 by using spin coating. Can do.

Referring to FIG. 18K, the polymer layer 436 can form multiple openings 436a by exposure and development, and O ₂ plasma ash. These openings 436a expose a large number of wire bonding pads 432, a large number of contact pads 434 and conceal the inductor device 430. The polymer layer 436 can then be heat treated under a temperature between about 150 and 380 degrees Celsius. The material of the polymer layer 436 is polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), parylene, epoxy resin or epoxy such as photoepoxy SU-8 provided by Sotec Microsystems of Renens, Switzerland. The material can be selected from silicones or elastomers such as AL-2000 provided by Asahi glass Co. When the polymer layer 436 is made of polyimide, it is preferably an ester type polyimide. The polymer layer 436 is preferably photosensitive so that the polymer layer 436 can be patterned using lithography. The polymer layer 436 can have a thickness between about 5 micrometers and about 50 micrometers in example embodiments. The optimum thickness is between 10 and 20 micrometers. The polymer layer 436 may be a fluorine-containing polymer having a cure temperature between about 130 and about 200 degrees C, and preferably between 150 and 190 degrees C.

In some applications, polymer layer 436 is formed by spin-on coating a negative photosensitive polyimide layer having a thickness between 6 and 150 micrometers on metal layer 428, inductor 430, and polymer layer 421. Sometimes it is possible. The spin-on coated polyimide layer can then be baked. The spin-on coated polyimide layer can then be exposed. To expose the baked polyimide layer, at least two of g-line having a wavelength in the range of 434 to 438 nm, h-line having a wavelength in the range of 403 to 407 nm, and i-line having a wavelength in the range of 363 to 367 nm. Using a 1X stepper or 1X contact aligner with two. The polyimide layer can then be illuminated. To illuminate the baked polyimide layer, for example, using g- and h-line, g- and i-line, h- and i-line, or g-line, h-line, and i-line illumination from a mercury lamp light source Can be included. The baked polyimide layer can then be developed and then exposed to form multiple openings that expose the pads 432 and 434. Next, heat treatment can be performed. Heat treatment or heating of the developed polyimide layer can be performed, for example, at a temperature between 130 and 400 ° C. for a time between 20 and 150 minutes in a nitrogen or oxygen-free atmosphere. In example embodiments, the heat-treated polyimide layer can have a thickness between about 3 and about 25 micrometers. Residual polymer material or other contaminants can then be removed from pads 432 and 434, for example, by O ₂ plasma or plasma containing less than 200 PPM fluorine and oxygen. In this manner, the polymer layer 436 can be formed on the metal layer 428, the inductor 430, and the polymer layer 421, and the opening 436a formed in the polymer layer 436 exposes the pads 432 and 434.

  As an example of a suitable heat treatment process, the developed polyimide layer can be heated or heat treated in a nitrogen or oxygen-free atmosphere at a temperature between 180 and 250 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 250 and 290 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 290 and 400 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 200 and 390 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 130 and 220 ° C. for a time between 20 and 150 minutes.

In other applications, the polymer layer 436 is a spin-on coating of a positive photosensitive polybenzoxazole layer having a thickness between about 3 and about 25 micrometers on the metal layer 428, the inductor 430, and the polymer layer 421. Can be formed. The spin-on coated polybenzoxazole layer can then be baked and exposed. For exposing the baked polybenzoxazole layer, the g-line has a wavelength in the range of 434 to 438 nm, the h-line has a wavelength in the range of 403 to 407 nm, and the i-line has a wavelength in the range of 363 to 367 nm. It may include using a 1X stepper or 1X contact aligner with at least two. The baked polybenzoxazole layer can be illuminated. Illuminating the baked polybenzoxazole layer can include g-line and h-line, g-line and i-line, h-line and i-line, or g-line, h-line, and i-line illuminations. The exposed polybenzoxazole layer can be developed to form multiple openings that expose pads 432 and 434. A heat treatment step / process can then be applied to the developed polybenzoxazole. To heat or heat-treat the developed polybenzoxazole layer, a time between about 5 and 180 minutes, preferably a time between 30 and 120 minutes, about 150 and about 250 ° in a nitrogen or oxygen-free atmosphere. It may include using a temperature between C, preferably between 180 and 250 ° C, or between 200 and 400 ° C, preferably between 250 and 350 ° C. In example embodiments, the heat-treated polybenzoxazole layer can have a thickness between about 3 and about 25 μm. For example, residual polymer material or other contaminants can be removed from pads 432 and 434 by O ₂ plasma or plasma containing less than 200 PPM fluorine and oxygen. By such a process, polymer layer 436 can be formed on metal layer 428, inductor 430, and polymer layer 421, and openings 436a exposing pads 432 and 434 can be formed in polymer layer 436.

Referring to FIGS. 18L and 18M, the substrate 100, the passivation layer 160, the polymer layer 421, and the polymer layer 436 can be cut to obtain a large number of semiconductor chips 600 using a dicing procedure. A number of wire bonding pads 432 on the semiconductor chip 600 can be connected to an external circuit or power source through wires 416 formed by a wire bonding process. The wire 416 can be formed of copper or gold. For example, a copper or gold wire can be connected to the wire bonding pad 432 by wire bonding techniques. In this case, the wire bonding pad 432 is a copper pad, an aluminum pad, an aluminum cap, or a nickel cap. The solder layer 420 can then connect the contact pads 434 to the capacitor device 418 using surface mount techniques (SMT), which pass through the metal layer 140 in the integrated circuit 20 and the inductor. Connected to device 430 Of course, a dicing procedure can also be performed after mounting the capacitor.
Manufacturing method and structure 2 of Embodiment 8
With continued reference to FIG. 18K, and with further reference to FIGS. 18N and 18O, inductor 430 and pad 166b may be disposed between contact pad 434 and pad 166c.

  Referring to FIGS. 18P and 18Q, a dicing procedure can be used to cut the substrate 100, the passivation layer 160, the polymer layer 421, and the polymer layer 436 to obtain a large number of semiconductor chips 600. A number of wire bonding pads 432 on the semiconductor chip 600 can be connected to an external circuit or power source through wires 416 formed by a wire bonding process. The wire 416 can be formed of copper or gold. For example, a copper or gold wire can be connected to the wire bonding pad 432 by wire bonding techniques. In this case, the wire bonding pad 432 is a copper pad, an aluminum pad, an aluminum cap, or a nickel cap. The solder layer 420 can then use surface mount techniques (SMT) to connect the contact pads 434 to the capacitor device 418, which is connected to the metal layer 428 or the metal layer in the integrated circuit 20. 140 is connected to the inductor device 430. Of course, a dicing procedure can also be performed after mounting the capacitor.

Embodiment 9
Referring to FIGS. 19A and 19B, a ninth embodiment (“Embodiment 9”) is shown. The ninth embodiment is similar to the eighth embodiment, the main difference being the position of the wire bonding pad 432 and pad 166a. In the eighth embodiment, the wire bonding pad 432 is shown directly above the pad 166a, but in this embodiment ("Embodiment 9"), the wire bonding pad 432 is directly above the pad 166a. Not. Thus, the position of the wire bonding pad 432 is not limited to the area directly above the pad 166a and can be adjusted according to requirements.

Embodiment 10
Referring to FIGS. 20A and 20B, a tenth embodiment (“Embodiment 10”) is shown. This embodiment is similar to embodiment 8, with the difference being in the inductor device connection pads 438 exposed by multiple openings 436a in the polymer layer 436. The connection pad 438 can be connected to an external circuit or power source using wires 416 made by a wire bonding process.

Embodiment 11
Referring to FIGS. 21A to 21K, an eleventh embodiment (“Embodiment 11”) is shown. In these figures, the integrated circuit 20 represents all the structures underlying the passivation layer 160. Also, the integrated circuit 20 includes a substrate 100, devices 110, 112, 114, a first dielectric layer 150, a metal layer 140, a second dielectric layer 155, a metal contact 120, and a metal via 130 (see, for example, FIG. 7A). As shown), and a number of passivation layer openings 165a in the passivation layer 160 expose a number of pads 166a, 166b, and 166c (pads 166a not shown).

  Referring to FIG. 21B, the adhesion / barrier layer 401 can be formed by sputtering on the passivation layer 160 and the contact pads 166a, 166b, 166c. The thickness of the adhesion / barrier layer 401 is between about 0.1 micrometers and about 1 micrometer with the optimum thickness being between 0.3 micrometers and 0.8 micrometers. The material of the adhesion / barrier layer 401 is preferably TiW or Ti or Ti / TiW.

  Referring to FIG. 21C, for example, a seed layer having a thickness between about 0.05 micrometers and about 1 micrometer (preferred thickness is between 0.08 micrometers and 0.7 micrometers). 402 can then be formed on the adhesion / barrier layer 401 by sputtering. In this embodiment, the seed layer 402 is preferably made of gold. However, the material of the seed layer 402 can vary depending on the material of the metal layer that is subsequently formed thereon.

  Referring to FIG. 21D, a photoresist layer 404 is formed on the seed layer 402, and the photoresist layer 404 is patterned by spin coating, exposure, and development, and a plurality of photoresist layer openings 404a are formed in the photoresist layer 404. Form. Photoresist layer opening 404a separately exposes the portion of seed layer 402 overlying pads 166a, 166b, and 166c.

  Referring to FIG. 21E, a bonding metal layer 406 is formed on the seed layer 402 by electroplating, electroless plating, sputtering, or CVD. This is in the photoresist layer opening 404a. The bonding metal layer 406 can be made of aluminum, gold, copper, silver, palladium, rhodium, ruthenium, rhenium, and / or nickel, and can have a single metal layer structure or a multiple metal layer structure. The thickness of the bonding metal layer 406 can preferably be between about 1 micrometer and about 100 micrometers, with an optimal preferred thickness being between 1.5 micrometers and 15 micrometers. Layer 406 can be made of a combination of multiple metal layers forming a multi-layered structure including, for example, Cu / Ni / Au, Cu / Au, Cu / Ni / Pd, and / or Cu / Ni / Pt. . In this embodiment, the bonding metal layer 406 is preferably a single layer made of gold.

Referring to FIG. 21F, a removal process can be applied to the patterned photoresist layer 404 and portions of the seed layer 402 and adhesion / barrier layer 401 that are not under the metal layer 406. The portion of the seed layer 402 made of gold can be removed by using a solvent containing I ₂ . When the material of the layer 401 is TiW, the adhesion / barrier layer 401 can be removed by using a solvent containing hydrogen peroxide (H ₂ O ₂ ). After removing the patterned photoresist layer 404 and portions of the seed layer 402 and the adhesion / barrier layer 401 that are not under the bonding metal layer 406, the bonding metal layer 406 includes a number of wire bonding pads 440, and a number of bonding layers. Contact pads 442 can be formed. Wire bond pad 440 and contact pad 442 may be connected through bonding metal layer 406.

  Referring to FIG. 21G, a polymer layer 444 can be formed over a number of wire bonding pads 440, a number of contact pads 442, and a passivation layer 160, for example, by using spin coating.

Referring to FIG. 21H, a number of openings 444a can be patterned in the polymer layer 444 by exposure and development, and O ₂ plasma ash. These openings 444a expose a number of wire bonding pads 440 and a number of contact pads 442. The polymer layer 444 can then be heat treated, for example, at a temperature between about 150 and 380 degrees Celsius. The material of the polymer layer 444 is polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), parylene, epoxy resin or an epoxy such as photoepoxy SU-8 provided by Sotec Microsystems of Renens, Switzerland. The material can be selected from silicones or elastomers such as AL-2000 provided by Asahi glass Co. When the polymer layer 444 is made of polyimide, it is preferably an ester type polyimide. The polymer layer 444 is preferably photosensitive so that the polymer layer 444 can be patterned using lithography (this eliminates the need for an etching process). In example embodiments, the polymer layer 444 can have a thickness between about 5 micrometers and about 50 micrometers. The optimum thickness is between 10 and 20 micrometers. The polymer layer 444 may be a fluorine-containing polymer having a curing temperature between about 130 and about 200 degrees C, and preferably between 150 and 190 degrees C.

In some applications, the polymer layer 444 can be formed by spin-on coating a negative photosensitive polyimide layer having a thickness between 6 and 150 micrometers on the passivation layer 160 and the metal layer 406. is there. The polyimide layer can then be baked and exposed. To expose the baked polyimide layer, at least two of g-line having a wavelength in the range of 434 to 438 nm, h-line having a wavelength in the range of 403 to 407 nm, and i-line having a wavelength in the range of 363 to 367 nm. Using a 1X stepper or 1X contact aligner with two. The baked polyimide layer can then be illuminated. To illuminate the baked polyimide layer, for example, use g-line and h-line, g-line and i-line, h-line and i-line, or g-line, h-line, and i-line illumination from a mercury lamp light source. Can be included. The exposed polyimide layer can then be developed to form a number of openings that expose the pads 440 and 442. Next, heat treatment can be performed. Heat treatment or heating of the developed polyimide layer can be performed at a temperature between about 130 and about 400 ° C. for a time between 20 and 150 minutes in a nitrogen or oxygen-free atmosphere. In an example embodiment, the heat treated polyimide layer can have a thickness between 3 and 25 micrometers. Residual polymer material or other contaminants can then be removed from pads 440 and 442, for example, by an O ₂ plasma or a plasma containing less than 200 PPM fluorine and oxygen. By such a process, the polymer layer 444 can be formed on the passivation layer 160 and the metal layer 406, and the openings 444a formed in the polymer layer 444 expose the pads 440 and 442.

  In an example of a suitable heat treatment process, the developed polyimide layer may comprise heating or heat treating at a temperature between 180 and 250 ° C. for a time between 20 and 150 minutes in a nitrogen or oxygen-free atmosphere. it can. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 250 and 290 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 290 and 400 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 200 and 390 ° C. for a time between 20 and 150 minutes. Alternatively, the developed polyimide layer can be heat treated or heated in a nitrogen or oxygen-free atmosphere at a temperature between 130 and 220 ° C. for a time between 20 and 150 minutes.

In other applications, the polymer layer 444 is formed by spin-on coating a positive photosensitive polybenzoxazole layer having a thickness between about 3 and about 25 micrometers on the passivation layer 160 and the metal layer 406. can do. The spin-on coated polybenzoxazole layer can then be baked and exposed. For exposing the baked polybenzoxazole layer, the g-line has a wavelength in the range of 434 to 438 nm, the h-line has a wavelength in the range of 403 to 407 nm, and the i-line has a wavelength in the range of 363 to 367 nm. It may include using a 1X stepper or 1X contact aligner with at least two. The baked layer can be illuminated. To illuminate the baked polybenzoxazole layer, for example, using a mercury lamp light source, g-line and h-line, g-line and i-line, h-line and i-line, or g-line, h-line, and i-line illumination Can be included. Other radiation sources can of course be used for this and other embodiments of the present disclosure. The exposed polybenzoxazole layer can be developed to form multiple openings exposing pads 440 and 442. A heat treatment process can then be applied. To heat or heat-treat the developed polybenzoxazole layer, a time between about 5 and 180 minutes, preferably a time between 30 and 120 minutes, about 150 and about 250 ° in a nitrogen or oxygen-free atmosphere. It may include using a temperature between C, preferably between 180 and 250 ° C, or between 200 and 400 ° C, preferably between 250 and 350 ° C. In example embodiments, the heat-treated polybenzoxazole layer can have a thickness between about 3 and about 25 μm. For example, residual polymer material or other contaminants can be removed from pads 440 and 442 by an O ₂ plasma or a plasma containing less than about 200 PPM fluorine and oxygen. By such a process, a polymer layer 444 can be formed on the passivation layer 160 and the metal layer 406, and an opening 444a exposing the pads 440 and 442 can be formed in the polymer layer 444.

  Referring to FIG. 21I and FIG. 21J, a substrate 100, the passivation layer 160, and the polymer layer 444 can be cut using a dicing procedure to obtain a large number of semiconductor chips 600. A number of wire bonding pads 440 on the semiconductor chip 600 can be connected to an external circuit or power source through wires 416 formed by a wire bonding process. The wire 416 can be formed of copper or gold. For example, a copper or gold wire can be connected to the wire bonding pad 440 by wire bonding techniques. In this case, the wire bonding pad 440 is a copper pad, an aluminum pad, an aluminum cap, or a nickel cap. The solder layer 420 can then connect the contact pads 440 to the capacitor device 446 using surface mount techniques (SMT), which pass through the metal layer 140 in the integrated circuit 20 and the inductor. Connected to device 448 FIG. 21J shows a cross-sectional view of FIG. 21K along the cut plane indicated by line 2-2. Of course, a dicing procedure can also be performed after mounting the capacitor.

  The device and the structure according to the tenth and eleventh embodiments can be used for a device for setting a voltage, as shown in the circuit diagrams of FIGS. In FIG. 22, the power input 2240 is connected to the inductor 2320, the inductor 2320 is connected to the capacitor 2310 via the transistor 2114d, the voltage feedback circuit 2112 is connected to the power output 2110, and the switch controller 2114a. Is connected to the voltage feedback device 2112 and the switch transistor 2114b. In operation, when power enters through the power input 2240, the switch controller 2114a receives the voltage signal of the voltage feedback device 2112, controls the on and off timing of the switch transistor 2114b, and sets the voltage level of the power output 2110. Boost the pressure. Inductor 2320, together with capacitor 2310, voltage feedback device 2112, switch transistor 2114b, and transistor 2114d, forms an on-chip voltage regulator or converter according to the manufacturing process already described. The MOS device 2114b can be replaced with a DMOS, LDMOS, or bipolar transistor. The MOS device 2114d can also be replaced with a DMOS, LDMOS, or bipolar transistor. The voltage feedback device 2112 may provide a dynamic voltage scaling function.

  23 and FIG. 22 is that the circuit diagram of FIG. 23 is made up of a number of inductors 2320, capacitors 2310, switch transistors 2114g, switch transistors 2114i, transistors 2114h, and transistors 2114f. Switch controller 2114a receives the voltage signal of voltage feedback device 2112 and is used to control the duty cycle and phase of switch transistor 2114g and switch / transistor 2114i, thus boosting the voltage level of power output 2110 To do. Compared with the circuit diagram of FIG. 22, the circuit diagram of FIG. 23 can regulate the output voltage with higher accuracy and efficiency. Transistor 2114g can be replaced with a DMOS, LDMOS, or bipolar transistor. Transistor 2114i can be replaced with a DMOS, LDMOS, or bipolar transistor. Transistor 2114f can be replaced with a DMOS, LDMOS, or bipolar transistor. Transistor 2114h can be replaced with a DMOS, LDMOS, or bipolar transistor.

  24 and 25, an N-type DMOS device according to one embodiment of the present disclosure is shown. FIG. 24 shows a cross-sectional view of an N-type DMOS device, and FIG. 25 shows a top view of the N-type DMOS device.

The elements shown in FIGS. 24 and 25 will be described as follows.
3110: N-well or lightly doped N-type semiconductor region,
3115: lightly doped P-type semiconductor region,
3120: Field isolation region, shallow trench isolation filled with oxide or LOCOS isolation,
3125: DMOS source, heavily doped P-type semiconductor region,
3130: DMOS drain, heavily doped N-type semiconductor region,
3135: DMOS source, heavily doped N-type semiconductor region 3140: DMOS source, lightly doped N-type semiconductor region 3145: Metal silicate on the source of DMOS And Ni-silicate, Co-silicate, or Ti-silicate.

3150: DMOS gate oxide.
3155: Gate spacer, comprising silicon oxide, nitrogen doped silicon oxide, or silicon nitride,
3160: Metal silicate on the drain of the DMOS, including Ni-silicate, Co-silicate, or Ti-silicate
3165: Metal contact point of DMOS,
3170: DMOS gate, silicon, Ni-silicate, Co silicate, Ti-silicate, W-silicate, Mo-silicate, TiN, Ta, TaN, Al, AIN, W, WN, or Ti is included.

  26A and 26B illustrate a side view of a system in / package or module including a power management IC chip 3210a or 3210b having an on-chip passive device, according to an example embodiment of the present disclosure.

  27A and 27B illustrate a system-in-package or module that includes a power management IC chip 3210a or 3210b having an on-chip passive device, according to an example embodiment of the present disclosure.

  28A and 28B illustrate a system-in-package or module that includes a power management IC chip 3210a or 3210b having an on-chip passive device, according to an example embodiment of the present disclosure.

  29A and 29B illustrate a system-in-package or module that includes a power management IC chip 3210a or 3210b with an on-chip passive device, according to an example embodiment of the present disclosure.

  30A and 30B illustrate a system-in-package or module that includes a power management IC chip 3210a or 3210b having an on-chip passive device, according to an example embodiment of the present disclosure.

  31A and 31B illustrate a system-in-package or module that includes a power management IC chip 3210a or 3210b having an on-chip passive device, according to an example embodiment of the present disclosure.

  32A and 32B illustrate a system-in-package or module that includes a power management IC chip 3210a or 3210b having an on-chip passive device, according to an example embodiment of the present disclosure.

  33A and 33B illustrate a system-in-package or module that includes a power management IC chip 3210a or 3210b having an on-chip passive device, according to an example embodiment of the present disclosure. Elements shown in FIGS. 26A-33B include:

3000: Package or module substrate. It can be made of BT, FR4, glass, silicon, ceramic, Cu wiring, Ni / Au pad or polyimide.
3210a: A power management chip in combination with an on-chip passive device, with voltage regulation, voltage conversion, dynamic voltage scaling, battery management, or charging functions. On-chip passive devices include inductors, capacitors, or resistors. Chip 3210a can be used in a wire bonding process.

  3210b: A power management chip in combination with an on-chip passive device, with voltage regulation, voltage conversion, dynamic voltage scaling, battery management, or charging functions. On-chip passive devices include inductors, capacitors, or resistors. Chip 3210b can be used in a flip chip process.

3230: Bonding wire formed by a wire bonding process. This wire may be an Au wire, a Cu wire, or an Al wire.
3235: Encapsulant, such as molding material, epoxy, or polyimide.

3240: IC chip such as a logic chip, DRAM chip, SRAM chip, FLASH chip, or analog chip.
3245: IC chip such as logic chip, DRAM chip, SRAM chip, FLASH chip, or analog chip.

3250: Adhesive such as silver epoxy or polyimide 3255: BGA solder ball, such as tin-lead alloy, tin-silver alloy, tin-silver-copper alloy, tin-bismuth alloy, or tin-indium alloy.

  3310: Power management chip package substrate, including lead frame, BT, FR4, glass, silicon, ceramic, Cu wiring, Ni / Au pad, or polyimide.

  3320: Metal with solder layer, such as Cu layer, Ni layer, Au layer, or tin-lead alloy, tin-silver alloy, tin-silver-copper alloy, tin-bismuth alloy, or tin-indium alloy Connection part.

3330: IC chip such as logic chip, DRAM chip, SRAM chip, FLASH chip, or analog chip.
3335: Encapsulant, such as molding material, epoxy, or polyimide.

3340: IC chip such as a logic chip, DRAM chip, SRAM chip, FLASH chip, or analog chip.
3350: Underfill material including epoxy or polyimide.

  3360: an electroplated copper layer with a thickness between 10 and 100 micrometers, a gold layer with an electroplated gold layer with a thickness between 5 and 30 micrometers, or a thickness between 10 and 350 micrometers A metal bump comprising a solder layer, such as a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy, a tin-bismuth alloy, or a tin-indium alloy. This metal bump is on an overlying chip, such as an adhesive layer such as titanium, titanium nitride, or titanium-tungsten alloy, a copper seed layer on the adhesive layer, and a copper seed layer. An electroplated copper layer having a thickness between 10 and 100 micrometers; an electroplated or electroless plated nickel layer on the electroplated copper layer and the solder layer; and a thickness between 10 and 100 micrometers A solder layer, such as a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy, a tin-bismuth alloy, or a tin-indium alloy, having a thickness on an electroplated or electrolessly plated nickel layer; The solder layer is bonded to the underlying substrate.

  FIG. 34 illustrates a step-down DC-DC switching voltage regulator or converter according to an example embodiment of the present invention, including an on-chip capacitor 1310, an on-chip inductor 1320, an on-chip input capacitor 32u for input power, It includes a switch controller or circuit 1114a having N-type switching DMOS devices 3114b and 3114e.

  As described above, FIG. 34 illustrates a switch controller or circuit 1114a having an on-chip capacitor 1310, an on-chip inductor 1320, an on-chip input capacitor 32u for input power, and two N-type switching DMOS devices 3114b and 3114e. FIG. 5 illustrates a step-down DC-DC switching voltage regulator or converter including. If the elements shown in FIG. 34 have the same reference numbers as shown in FIG. 14, they can be cited in the previous discussion regarding FIG. The arrangement of the on-chip capacitor 1310 and the on-chip inductor 1320 formed on the passivation layer 160 is shown in FIGS. 3, 4, 4N, 4U, 4AJ, 4AK, 4AL, 4AM, FIG. 5D, FIG. 6, FIG. 6I, and FIG. 7A, an array of surface mount capacitors 310 and inductors 320, an array of surface mount integrated passive devices 330 shown in FIG. 7B, FIG. 17F to FIG. 17L, FIG. 18Q, described in all embodiments, such as the array of built-in inductors 418 or 430 and surface mount capacitors 418 shown in FIGS. 19A and 20A, and the array of surface mount capacitors 446 and inductors 448 shown in FIG. 21J. It can be cited in the previous discussion. The output pad 1313 corresponding to the pad 440 in FIG. 21H has a metal trace (FIG. 21H and FIG. 21) above the passivation layer 160 to the inductor 1320 corresponding to the inductor 448 in FIG. 21J and the capacitor 1310 corresponding to the inductor 446 in FIG. Through the left segments of the metal layers 401, 402, and 406 shown in 21J. Output pad 1313 can also be connected to inductor 1320 and capacitor 1310 through metal traces made of copper or sputtered aluminum electroplated under passivation layer 160. The placement of the on-chip input capacitor 32u for input power is as shown in FIGS. 3, 4, 4N, 4U, 4AJ, 4AK, 4AL, 4AM, 5, 5D, 6, 6I, and 7A to 17L, FIG. 18M, FIG. 18Q, FIG. 19A, an arrangement of the surface mount integrated passive device 330 shown in FIG. 7B in which the surface mount capacitor 310, inductor 1320 and capacitors 1310 and 32u shown in FIG. 7A are integrated. 20A, and the placement of the on-chip capacitor 1310, such as the placement of the surface mount capacitor 446 shown in FIG. 21J.

  FIG. 35 illustrates a step-down DC-DC switching voltage regulator or converter according to an example embodiment of the present invention, with an on-chip capacitor 1310, an on-chip inductor 1320, an on-chip input capacitor 32u for input power, P- A switch controller or circuit 1114a having a n-type switching DMOS device 3115b and an n-type switching DMOS device 3115e.

  As described above, the step-down DC-DC switching voltage regulator or converter in FIG. 35 includes an on-chip capacitor 1310, an on-chip inductor 1320, an on-chip input capacitor 32u for input power, and a P-type switching DMOS device 3115b. And a switch controller or circuit 1114a having an N-type switching DMOS device 3115e. If the elements shown in FIG. 35 have the same reference numbers as shown in FIG. 14, they can be cited in the previous discussion regarding FIG. The arrangement of the on-chip capacitor 1310 and the on-chip inductor 1320 formed on the passivation layer 160 is shown in FIGS. 3, 4, 4N, 4U, 4AJ, 4AK, 4AL, 4AM, FIG. 5D, FIG. 6, FIG. 6I, and FIG. 7A, an array of surface mount capacitors 310 and inductors 320, an array of surface mount integrated passive devices 330 shown in FIG. 7B, FIG. 17F to FIG. 17L, FIG. 18Q, described in all embodiments, such as the array of built-in inductors 418 or 430 and surface mount capacitors 418 shown in FIGS. 19A and 20A, and the array of surface mount capacitors 446 and inductors 448 shown in FIG. 21J. It can be cited in the previous discussion. The illustrated output pad 1313 can correspond to the pad 440 in FIG. 21H, the inductor 1320 corresponding to the inductor 448 in FIG. 21J, and the capacitor 1310 corresponding to the inductor 446 in FIG. 21J to the metal above the passivation layer 160. The traces (provided by the left segment of the metal layers 401, 402, and 406 shown in FIGS. 21H and 21J) can be connected. Output pad 1313 can also be connected to capacitor 1310 and inductor 1320 through metal traces made of copper or sputtered aluminum electroplated under passivation layer 160. The placement of the on-chip input capacitor 32u for input power is as shown in FIGS. 3, 4, 4N, 4U, 4AJ, 4AK, 4AL, 4AM, 5, 5D, 6, 6I, and 7A to 17L, FIG. 18M, FIG. 18Q, FIG. 19A, an arrangement of the surface mount integrated passive device 330 shown in FIG. 7B in which the surface mount capacitor 310, inductor 1320 and capacitors 1310 and 32u shown in FIG. , Similar to the placement of the on-chip capacitor 1310, such as the placement of the surface mount capacitor 418 shown in FIG. 20A, and the placement of the surface mount capacitor 446 shown in FIG. 21J. Can do).

  FIG. 36 illustrates a step-up DC-DC switching voltage regulator or converter according to an example embodiment of the present invention, including an on-chip capacitor 2310, an on-chip inductor 2320, an on-chip input capacitor 32u for input power, It includes a switch controller or circuit 2114a having N-type switching DMOS devices 3116b and 3116e.

  As described above, the step-up DC-DC switching voltage regulator or converter in FIG. 36 includes an on-chip capacitor 2310, an on-chip inductor 2320, an on-chip input capacitor 32u for input power, and two N-type switching DMOSs. It includes a switch controller or circuit 2114a having devices 3116b and 3116e. The elements shown in FIG. 36 are similar to the elements shown in FIG. 22 and are indicated with the same reference numerals. The arrangement of the on-chip capacitor 2310 and the on-chip inductor 2320 formed on the passivation layer 160 is as shown in FIGS. 3, 4, 4N, 4U, 4AJ, 4AK, 4AL, 4AM, FIG. 5D, FIG. 6, FIG. 6I, and FIG. 7A, an array of surface mount capacitors 310 and inductors 320, an array of surface mount integrated passive devices 330 shown in FIG. 7B, FIG. 17F to FIG. 18Q, other embodiments, such as the array of built-in inductors 418 or 430 and surface mount capacitors 418 shown in FIG. 19A and FIG. 20A, and the array of surface mount capacitors 446 and inductors 448 shown in FIG. 21J. It can be cited as an explanation. The output pad 2110 corresponds to the pad 440 in FIG. 21H, the inductor 2310 corresponding to the inductor 446 in FIG. 21J, and metal traces above the passivation layer 160 (the metal layers 401, 402, shown in FIGS. 21H and 21J, And the left segment of 406). The output pad 2110 can also be connected to the capacitor 2310 through a metal trace made of copper or sputtered aluminum electroplated under the passivation layer 160. The placement of the on-chip input capacitor 32u for input power is as shown in FIGS. 3, 4, 4N, 4U, 4AJ, 4AK, 4AL, 4AM, 5, 5D, 6, 6I, and 7A to 17L, FIG. 18M, FIG. 18Q, FIG. 19A, an arrangement of the surface mount integrated passive device 330 shown in FIG. 7B, in which the surface mount capacitor 310, inductor 2320 and capacitors 2310 and 32u shown in FIG. 20A, and the placement of the on-chip capacitor 1310, such as the placement of the surface mount capacitor 446 shown in FIG. 21J. The N-type DOMS devices 3114b, 3114e, 3115e, 3116b, and 3116e shown in FIGS. 34 to 36 are the same as the DMOS devices of FIGS.

  FIG. 37 shows a cross-sectional view of a portion of the step-down switching voltage regulator or converter shown in FIG. FIG. 38 shows a cross-sectional view of a portion of the step-up switching voltage regulator or converter shown in FIG. The elements shown in FIGS. 37 and 38 are shown to have the same reference numbers as shown in FIGS. 24, 25, 34, and 37. Additional elements described in FIGS. 37 and 38 are as follows. 3180: Opening in the passivation layer. The opening has a thickness between 0.1 and 20 micrometers, between 0.5 and 30 micrometers, or between 0.1 and 200 micrometers.

  The operational amplifiers 32g, 32j, 32k, and 32o can be implemented or realized by the operational amplifier circuit shown in FIG. This circuit will be discussed below with respect to FIG.

The elements shown in FIG. 39 are described as follows.
33a, 33b, 33c, 33f, and 33g: PMOS devices.
33h, 33i, and 33j: NMOS devices.

33d: Resistor.
33e: Gate to silicon capacitor.
FIG. 40 shows a functional block diagram of a converter that realizes the circuit diagram of FIG. FIG. 41 shows a functional block diagram of a converter that realizes the circuit diagram of FIG. Elements shown in FIGS. 40 and 41 are shown having the same reference numerals as those shown in FIGS. 24, 25, 34, 35, and 37.

The elements shown in FIGS. 40 and 41 are described as follows.
114a: MOSFET driver, anti-shoot-through converter control logic.
1310: Output power disconnect capacitor. The capacitance of this capacitor may be between 1 μF and 100 μF, between 0.1 pF and 50 mH, or between 1 pF and 1 mF.
1311: Power stage voltage pad 1313: Output voltage node pad.

  1320: Switch inductor. The inductance of this inductor can be between 0.1 nH and 10 mH, between 100 nH and 10 mH, or between 1 nH and 100 mH.

3114b: N-type DMOS device.
3114e: N-type DMOS device.
3115b: P-type DMOS device.

3115e: N-type DMOS device.
31c: Power supply pad for control circuit.
FB: Feedback voltage from the output.

31e: Chip enable pad.
31f: Power normality indicating pad.
31g: Output voltage tracking input pad. The signal applied to this pin is used as a reference voltage and will be ignored if the internal reference voltage is below the internal 0.6V reference.

31h: Circuit grounding pad.
31i: Fixed frequency PWM (pulse-width-modulation) operation pad or pad for synchronizing the device to an external clock signal. When this pin is high, the device is forced into 1.5 MHz fixed frequency PWM operation.

31j: Pad for grounding the transducer.
31q: On-chip capacitor. The arrangement of the on-chip input capacitor 31q is shown in FIGS. 3, 4, 4N, 4U, 4AJ, 4AK, 4AL, 4AM, 5, 5D, 6, 6I, and 7A. FIG. 17B to FIG. 17L, FIG. 18M, FIG. 18Q, FIG. 19A, FIG. 19B, FIG. 17F to FIG. 17L, FIG. 18M, FIG. Reference may be made to an arrangement of on-chip capacitors 1310, such as the arrangement of surface mount capacitors 418 shown in 20A and the arrangement of surface mount capacitors 446 shown in FIG. 21J.

31r: Feedback voltage resistor.
31s: Feedback voltage resistor.
32a: NMOS
32b: Phase lock loop circuit 32c: sawtooth circuit.

32d: Vout generator.
32e: High-side current detection.
32f: Addition comparator.

32g: Error amplifier.
32h: Loop compensation.
32i: Analog softstart.

32j: a pulse modulator provided with a pulse width modulation comparator and a pulse frequency modulation circuit.
32k: Pulse frequency / pulse width modulation transition circuit.
32 m: Low side current detection.

32n: Bandgap undervoltage protection and thermal shutdown.
32o: Output voltage tracking.
32p: NMOS device.

32s: These elements surrounded by a dotted line 32s are formed in the chip.
32t: These elements surrounded by dotted line 32t are formed under the chip passivation layer 160 (already shown). An element outside the dotted line 32t is formed on the chip passivation layer 160 (shown above) and has an on-chip output filter with an on-chip inductor 1320 and an on-chip capacitor 1310. • Includes part of the regulator or converter.

32u: On-chip input capacitor for input power. The capacitance may be between 1 nF and 100 μF.
32v: switching circuit.

32w: Output filter.
The inductor 1320 can be connected to the capacitors 1310 and 31q and the resistor 31a through Cu wiring formed on or above the passivation layer 160. The Cu wiring layer may contain electroplated copper having a thickness between 3 and 30 micrometers or between 2 and 50 micrometers.

Example Embodiment: Application Circuit and Chip The circuits described above, for example, FIGS. 14, 15, 22, 23, 34 to 36, and 39 to 41, and FIGS. 3 and 4 4N, 4U, 4AK, 4AL, 4AM, 5, 6, 6I, 7A, 7B, 17L, 18M, 18Q, 19A, 19B, 20A, FIG. The foregoing structure shown in 20B, FIG. 21J, and FIG. 21K shows a system-in-package or module (including a power management IC chip 3210a or 3210b with an on-chip passive device). 27A, 27B, 28A, 28B, 29A, 29B, 30A, 30B, 31A, 31B, 32A, 32B, 33A, and FIG. As shown in FIG. 33B, the power management IC chip 3210a for the wire bonding process or the power management IC chip 3210b for the flip chip bonding process can be mounted on or realized by this.

  For example, the entire structure shown in FIG. 3 includes an on-chip capacitor 310 and an on-chip inductor 320 above the passivation layer 160, and FIGS. 26A, 27A, 28A, 29A, 30A, and 31A. 32A and / or the chip 3210a shown in FIG. 32A and shown in FIGS. 26A, 27A, 28A, 29A, 30A, 31A, 32A, and / or 33A, The wire bonded wire 3230 can be bonded to the metal pad exposed by the opening 165 in the passivation layer 160 shown in FIG.

  For another example, the entire structure shown in FIG. 4 or FIG. 4N includes an on-chip capacitor 310 and an on-chip inductor 320 above the passivation layer 160, and FIG. 26A, FIG. 27A, FIG. 29A, FIG. 30A, FIG. 31A, FIG. 32A, and / or the chip 3210a shown in FIG. 33A, and FIG. 26A, FIG. 27A, FIG. 28A, FIG. 29A, FIG. Alternatively, the wire-bonded wire 3230 shown in FIG. 33A can be bonded to the bonding metal layer 400c above the pad 166b exposed by the opening in the passivation layer 160 shown in FIG. 4 or FIG. 4N. The bonded wire 3230 is a wire bonder as shown in FIG. May be cited as the wire 37 was.

  In another example, the entire structure shown in FIG. 4U or FIG. 4AM includes an on-chip capacitor 310 and an on-chip inductor 320 above the passivation layer 160, and FIGS. 26A, 27A, 28A, and 29A. 30A, FIG. 31A, FIG. 32A, and / or the chip 3210a shown in FIG. 33A, and FIG. 26A, FIG. 27A, FIG. 28A, FIG. 29A, FIG. The wire-bonded wire 3230 shown in FIG. 33A can be bonded to the metal layer 46 above the pad 166b exposed by the opening in the passivation layer 160 shown in FIG. 4U or 4AM. The wire 3230 is the wire shown in FIG. 4U or 4AM It may be cited as the wire 47 is bonded.

  In addition, the entire structure shown in FIG. 6, FIG. 6I, or FIG. 7A includes an on-chip capacitor 310 and an on-chip inductor 320 above the passivation layer 160, FIG. 26A, FIG. 27A, FIG. 29A, 30A, 31A, 32A, and / or the chip 3210a shown in FIG. 33A, FIG. 26A, FIG. 27A, FIG. 28A, FIG. 29A, FIG. 33A can be bonded to the metal layer 220 exposed by the openings 240 in the polymer layer 230 shown in FIG. 6, FIG. 6I, or FIG. The wire bonded wire 3230 is the wire bonded wire 56 shown in FIG. 6I. Can be quoted.

  Further, the entire structure shown in FIG. 7B includes an integrated passive device 330 of capacitors and inductors above the passivation layer 160, and FIG. 26A, FIG. 27A, FIG. 28A, FIG. 29A, FIG. 32A and / or the chip 3210a shown in FIG. 33A, which can be used with the wire 32A shown in FIG. 26A, FIG. 27A, FIG. 28A, FIG. 29A, FIG. The bonded wire 3230 can be bonded to the metal layer 220 exposed by the opening in the polymer layer 230, and the wire bonded wire 3230 is referred to as the wire bonded wire 56 shown in FIG. 7B. be able to.

  In addition, the entire structure shown in FIG. 17L includes an on-chip inductor 408 and an on-chip inductor 320 above the passivation layer 160, and FIG. 26A, FIG. 27A, FIG. 28A, FIG. 29A, FIG. It can be used for the chip 3210a shown in FIG. 31A, FIG. 32A, and / or FIG. 33A and shown in FIG. 26A, FIG. 27A, FIG. 28A, FIG. 29A, FIG. The wire bonded wire 3230 can be bonded to the metal pad 410 exposed by the opening in the polymer layer 414 shown in FIG. 17L, and the wire bonded wire 3230 is referred to as the wire bonded wire 416. be able to.

  As another example, the entire structure shown in FIG. 18M includes an on-chip inductor 430 and an on-chip capacitor 418 above the passivation layer 160, and FIGS. 26A, 27A, 28A, 29A, and 30A. 31A, 32A, and / or 33A shown in FIG. 33A and can be used in FIGS. 26A, 27A, 28A, 29A, 30A, 31A, 32A, and / or 33A. The wire bonded wire 3230 shown can be bonded to the bonding metal layer 428 exposed by the openings in the polymer layer 436 shown in FIG. 18M, and the wire bonded wire 3230 is shown in FIG. Can be cited as wire-bonded wire 416 That.

  In addition, the entire structure shown in FIG. 18Q includes an on-chip inductor 430 and an on-chip capacitor 418 above the passivation layer 160, and FIG. 26A, FIG. 27A, FIG. 28A, FIG. 29A, FIG. It can be used for the chip 3210a shown in FIG. 31A, FIG. 32A, and / or FIG. 33A and shown in FIG. 26A, FIG. 27A, FIG. 28A, FIG. 29A, FIG. The wire-bonded wire 3230 can be bonded to the bonding metal layer 428 exposed by the openings in the polymer layer 436 shown in FIG. 18Q, and the wire-bonded wire 3230 can be bonded to the wire wires shown in FIG. It can be cited as bonded wire 416.

  In another example, the entire structure shown in FIG. 19A includes an on-chip inductor 430 and an on-chip capacitor 418 above the passivation layer 160, and FIGS. 26A, 27A, 28A, 29A, and 30A. 31A, 32A, and / or 33A shown in FIG. 33A and can be used in FIGS. 26A, 27A, 28A, 29A, 30A, 31A, 32A, and / or 33A. The wire bonded wire 3230 shown can be bonded to the wire bonding pad 432 exposed by the opening in the polymer layer 436 shown in FIG. 19A, and the wire bonded wire 3230 is shown in FIG. 19A. Can be cited as wire-bonded wire 416 That.

  Further, the entire structure shown in FIG. 20A includes an on-chip inductor 430 and an on-chip capacitor 418 above the passivation layer 160, and FIGS. 26A, 27A, 28A, 29A, 30A, and 31A. 32A and / or 33A can be used in the chip 3210a shown in FIGS. 26A, 27A, 28A, 29A, 30A, 31A, 32A, and / or 33A. The wire bonded wire 3230 can be bonded to the bonding metal layer 428 exposed by the openings in the polymer layer 436 shown in FIG. 20A, and the wire bonded wire 3230 can be bonded to the wire bonding shown in FIG. 20A. Can be referred to as wire 416.

  In addition, the entire structure shown in FIG. 21J includes an on-chip inductor 448 and an on-chip capacitor 446 above the passivation layer 160, and FIGS. 26A, 27A, 28A, 29A, 30A, and 30A. It can be used for the chip 3210a shown in FIG. 31A, FIG. 32A, and / or FIG. 33A and shown in FIG. 26A, FIG. 27A, FIG. 28A, FIG. 29A, FIG. The wire-bonded wire 3230 can be bonded to the bonding pad 440 exposed by the openings in the polymer layer 444 shown in FIG. 21J, and the wire-bonded wire 3230 is shown in FIG. It can be cited as bonded wire 416.

  As another example, the entire structure shown in FIG. 3 includes an on-chip capacitor 310 and an on-chip inductor 320 above the passivation layer 160, and FIGS. 26B, 27B, 28B, 29B, and 30B. 31B, FIG. 32B, and / or the chip 3210b shown in FIG. 33B, and can be used in FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, FIG. 30B, FIG. 31B, FIG. The illustrated metal bumps 3360 can be formed on the metal pads exposed by the openings 165 in the passivation layer 160 shown in FIG. 3 to bond the chip 3210b to the substrate 3310 or 3000.

  4 or 4N includes an on-chip capacitor 310 and an on-chip inductor 320 above the passivation layer 160, and FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, and FIG. 31B, FIG. 32B, and / or the chip 3210b shown in FIG. 33B, and can be used in FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, FIG. 30B, FIG. The metal bump 3360 shown is formed on the bonding metal layer 400c above the pad 166b exposed by the opening in the passivation layer 160 shown in FIG. 4 or 4N to bond the chip 3210b to the substrate 3310 or 3000. can do.

  In another example, the entire structure shown in FIG. 4U or FIG. 4AM includes an on-chip capacitor 310 and an on-chip inductor 320 above the passivation layer 160, and FIGS. 26B, 27B, 28B, and 29B. 30B, FIG. 31B, FIG. 32B, and / or the chip 3210b shown in FIG. 33B, and FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, FIG. 30B, FIG. The metal bump 3360 shown in FIG. 33B is formed on the metal layer 46 above the pad 166b exposed by the opening in the passivation layer 160 shown in FIG. 4U in order to bond the chip 3210b to the substrate 3310 or 3000. be able to.

  In addition, the entire structure shown in FIG. 5 or FIG. 5D includes an on-chip capacitor 310 and an on-chip inductor 320 above the passivation layer 160, and FIG. 26B, FIG. 27B, FIG. 28B, FIG. 30B, FIG. 31B, FIG. 32B, and / or the chip 3210b shown in FIG. 33B, and FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, FIG. 30B, FIG. 31B, FIG. The metal bump 3360 shown in FIG. 5 can be formed on the pad 166b exposed by the opening in the passivation layer 160, and the metal bump 3360 includes the elements 400 and 260 shown in FIG. Can be quoted.

  In other examples, the entire structure shown in FIG. 6, FIG. 6I, or FIG. 7A includes an on-chip capacitor 310 and an on-chip inductor 320 above the passivation layer 160, and FIG. 26B, FIG. 28B, FIG. 29B, FIG. 30B, FIG. 31B, FIG. 32B, and / or the chip 3210b shown in FIG. 32B. FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, FIG. And / or metal bumps 3360 shown in FIG. 33B are exposed by openings 240 in polymer layer 230 shown in FIG. 6, FIG. 6I, or FIG. 7A to bond chip 3210b to substrate 3310 or 3000. It can be formed on layer 220.

  Further, the entire structure shown in FIG. 7B includes an integrated passive device 330 of capacitors and inductors above the passivation layer 160, and is shown in FIGS. 26B, 27B, 28B, 29B, 30B, 31B, and 31B. The metal bump 3360 shown in FIGS. 26B, 27B, 28B, 29B, 30B, 31B, 32B, and / or 33B can be used for the chip 3210b shown in FIG. Can be formed on the metal layer 220 exposed by the openings in the polymer layer 230 to bond the chip 3210b to the substrate 3310 or 3000.

  In addition, the entire structure shown in FIG. 17L includes an on-chip inductor 408 and an on-chip capacitor 418 above the passivation layer 160, and FIGS. 26B, 27B, 28B, 29B, 30B, and 30B. It can be used for the chip 3210b shown in FIG. 31B, FIG. 32B, and / or FIG. 33B and shown in FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, FIG. Metal bumps 3360 may be formed on the metal pads 410 exposed by the openings in the polymer layer 414 shown in FIG. 17L to bond the chip 3210b to the substrate 3310 or 3000.

  In yet another example, the entire structure shown in FIG. 18M includes an on-chip inductor 430 and an on-chip capacitor 418 above the passivation layer 160, and FIG. 26B, FIG. 27B, FIG. 28B, FIG. 30B, FIG. 31B, FIG. 32B, and / or the chip 3210b shown in FIG. 33B, and FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, FIG. 30B, FIG. 31B, FIG. The metal bumps 3360 shown in FIG. 6 can be formed on the metal layer 428 exposed by the openings in the polymer layer 436 shown in FIG. 18M in order to bond the chip 3210b to the substrate 3310 or 3000.

  As another example, the entire structure shown in FIG. 18Q includes an on-chip inductor 430 and an on-chip capacitor 418 above the passivation layer 160, and FIGS. 26B, 27B, 28B, 29B, and 30B. 31B, FIG. 32B, and / or the chip 3210b shown in FIG. 33B, and can be used in FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, FIG. 30B, FIG. The illustrated metal bump 3360 indicates that the chip 3210b can be formed on the metal layer 428 exposed by the openings in the polymer layer 436 shown in FIG. 18Q to bond the chip 3210b to the substrate 3310 or 3000.

  Further, the entire structure shown in FIG. 19A includes an on-chip inductor 430 and an on-chip capacitor 418 above the passivation layer 160, and FIGS. 26B, 27B, 28B, 29B, 30B, and 31B. 32B and / or the chip 3210b shown in FIG. 33B and the metal shown in FIGS. 26B, 27B, 28B, 29B, 30B, 31B, 32B, and / or 33B. Bumps 3360 can be formed on pads 432 exposed by openings in polymer layer 436 shown in FIG. 19A to bond chip 3210b to substrate 3310 or 3000.

  In yet another example, the entire structure shown in FIG. 20A includes an on-chip inductor 430 and an on-chip capacitor 418 above the passivation layer 160, and FIG. 26B, FIG. 27B, FIG. 28B, FIG. 30B, FIG. 31B, FIG. 32B, and / or the chip 3210b shown in FIG. 33B, and FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, FIG. 30B, FIG. 31B, FIG. The metal bumps 3360 shown in FIG. 6 can be formed on the metal layer 432 exposed by the openings in the polymer layer 436 shown in FIG. 20A in order to bond the chip 3210b to the substrate 3310 or 3000.

  Finally, the entire structure shown in FIG. 21J includes an on-chip inductor 448 and an on-chip capacitor 446 above the passivation layer 160, and FIGS. 26B, 27B, 28B, 29B, 30B, and 30B. It can be used for the chip 3210b shown in FIG. 31B, FIG. 32B, and / or FIG. 33B and shown in FIG. 26B, FIG. 27B, FIG. 28B, FIG. 29B, FIG. Metal bumps 3360 may be formed on bonding pads 444 exposed by openings in polymer layer 436 shown in FIG. 21J to bond chip 3210b to substrate 3310 or 3000.

  Thus, from the above description, embodiments and aspects of the present disclosure can provide semiconductor chips and application circuits, and since passive and active devices are integrated with a semiconductor chip, signal paths between two types of devices Has a minimum distance, thus enabling fast and effective voltage regulation and reducing circuit routing area on the PCB. The response / response time of each device is shortened, and the performance of the electronic device is improved without increasing the cost.

  The components, steps, features, purposes, benefits, and advantages discussed above are merely exemplary. None of these or any discussion about them is intended to limit the scope of protection at all. Many other embodiments are also possible. These include embodiments with fewer components, steps, features, benefits, and advantages, embodiments with more, and / or different embodiments. They also include embodiments in which the components and / or steps are arranged differently and / or in a different order.

  Upon reading this disclosure, those skilled in the art will recognize that embodiments of the present disclosure can be implemented in hardware, software, firmware, or any combination of these, and on one or more networks. . Further, embodiments of the present disclosure can be included in or carried by various signals, eg, transmitted over a wireless RF or IR communication link and downloaded from the Internet.

  Unless otherwise stated, all measurements, values, ratings, positions, sizes, sizes, and other specifications specified herein, including the claims that follow, are approximations. ,it's not correct. They are intended to represent the legitimate scope consistent with the functions to which they relate and their customary in the technical field to which they relate.

  Where the phrase “means for” is used in the claims, it is intended and intended to encompass the corresponding structures and materials described, and equivalents thereof. Should be appropriate. Similarly, when the phrase “step for” is used in the claims, it includes the corresponding act described and equivalents thereof. The absence of these phrases is not intended and should not be construed as limiting the claim to any corresponding structure, material, or act, or equivalents thereof. Means that.

Although the present disclosure has been described with reference to the particular embodiment (s) above, the present disclosure can be practiced with modification within the spirit and scope of the appended claims, Those skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the disclosure. For example, while preferred radiation sources have been described as using certain lines produced by mercury lamps, other light sources suitable for the desired radiation wavelength can, of course, be used within the scope of the present disclosure. Accordingly, all such modifications fall within the scope of this disclosure, and this disclosure is intended to encompass the subject matter of the claims that follow.
Hereinafter, the invention described in the scope of claims of the present application will be appended.
[C1]
A chip package,
A substrate,
A first chip above the substrate;
A second chip above the substrate;
A voltage regulator device overlying the substrate, the voltage regulator device configured and arranged to address different voltage needs of the first chip and the second chip;
A chip package.
[C2]
The chip package according to C1, wherein the voltage regulator device comprises a semiconductor chip,
A silicon substrate;
A number of active devices in or above the silicon substrate, comprising a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices Type device,
A first dielectric layer overlying the silicon substrate;
A metallization structure above the first dielectric layer, the metallization structure connected to the active device, and a first metal layer and a second metal above the first metal layer A metallization structure comprising layers,
A second dielectric layer between the first and second metal layers;
A passivation layer above the metallization structure and the first and second dielectric layers, wherein an opening in the passivation layer exposes a pad and a contact pad of the metallization structure; and
An inductor component and a capacitor component connected to the pad through a first solder layer, wherein the inductor component, the capacitor component, a switch controller, and a voltage feedback device form the voltage regulator Components and capacitor components;
A chip package.
[C3]
The chip package of C2, wherein the passivation layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers.
[C4]
The chip package according to C2, further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is formed of the under bump metal structure. The chip package at the top.
[C5]
The chip package of C4, wherein the under bump metal structure comprises a nickel layer.
[C6]
The chip package of C4, wherein the under bump metal structure comprises a copper layer.
[C7]
The chip package of C1, wherein the second chip is above the first chip.
[C8]
The chip package of C1, wherein the substrate comprises a ball grid array (BGA) substrate.
[C9]
A chip package,
A substrate,
A first chip above the substrate;
A second chip above the substrate;
A voltage conversion device overlying the substrate, wherein the voltage conversion device is configured and arranged to address different voltage needs of the first chip and the second chip;
A chip package.
[C10]
The chip package according to C9, wherein the voltage conversion device includes a semiconductor chip, and the semiconductor chip includes:
A silicon substrate;
A number of active devices in or above the silicon substrate, comprising a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices Type device,
A first dielectric layer overlying the silicon substrate;
A metallization structure above the first dielectric layer, the metallization structure connected to the active device, and a first metal layer and a second metal above the first metal layer A metallization structure comprising layers,
A second dielectric layer between the first and second metal layers;
A passivation layer above the metallization structure and the first and second dielectric layers, wherein an opening in the passivation layer exposes a pad and a contact pad of the metallization structure; and
An inductor component and a capacitor component connected to the pad through a first solder layer, the inductor component, capacitor component, switch controller, and voltage feedback device forming an on-chip voltage converter An inductor component and a capacitor component;
A chip package.
[C11]
The chip package of C10, wherein the passivation layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers.
[C12]
The chip package of C10, further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is formed of the under bump metal structure. The chip package at the top.
[C13]
The chip package of C12, wherein the under bump metal structure comprises a nickel layer.
[C14]
The chip package of C12, wherein the under bump metal structure comprises a copper layer.
[C15]
The chip package of C9, wherein the second chip is above the first chip.
[C16]
The chip package of C9, wherein the substrate comprises a ball grid array (BGA) substrate.
[C17]
A chip package,
A substrate,
A first chip above the substrate;
A second chip above the substrate;
A power management device overlying the substrate, the power management device configured and arranged to address different voltage needs of the first chip and the second chip;
A chip package.
[C18]
The chip package according to C17, wherein the power management device includes a semiconductor chip, and the semiconductor chip includes:
A silicon substrate;
A number of active devices in or above the silicon substrate, comprising a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices Type device,
A first dielectric layer overlying the silicon substrate;
A metallization structure above the first dielectric layer, the metallization structure connected to the active device, and a first metal layer and a second metal above the first metal layer A metallization structure comprising layers,
A second dielectric layer between the first and second metal layers;
A passivation layer above the metallization structure and the first and second dielectric layers, wherein an opening in the passivation layer exposes a pad and a contact pad of the metallization structure; and
An inductor component and a capacitor component connected to the pad through a first solder layer;
A chip package.
[C19]
The chip package of C18, wherein the passivation layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers.
[C20]
The chip package of C18, further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is formed of the under bump metal structure. The chip package at the top.
[C21]
The chip package of C20, wherein the under bump metal structure comprises a nickel layer.
[C22]
The chip package of C20, wherein the under bump metal structure comprises a copper layer.
[C23]
The chip package of C17, wherein the second chip is above the first chip.
[C24]
The chip package of C17, wherein the substrate comprises a ball grid array (BGA) substrate.

Claims (22)

A semiconductor chip,
A semiconductor substrate;
A first 1D MO S devices located on said semiconductor substrate,
A second DMOS device on the semiconductor substrate;
A first capacitor above the semiconductor substrate;
Is above the semiconductor substrate, a inductor having a first terminal and a second terminal, said first terminal of said inductor, coupled to the first terminal of the first terminal and the second 2DMOS device of claim 1DMOS device And the second terminal of the inductor is coupled to the first capacitor; and
An on-chip capacitor coupled to a second terminal of the first DMOS device;
A semiconductor chip comprising:   2. The semiconductor chip according to claim 1, further comprising a passivation layer above the semiconductor substrate, wherein the passivation layer includes a nitride layer, and the first capacitor is above the passivation layer. There is a semiconductor chip.   The semiconductor chip of claim 2, wherein the nitride layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers.   The semiconductor chip according to claim 1, further comprising a passivation layer above the semiconductor substrate, the passivation layer comprising a nitride layer, and the inductor being above the passivation layer. Semiconductor chip.   5. The semiconductor chip of claim 4, wherein the nitride layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers.   The semiconductor chip according to claim 1, further comprising a polymer layer above the inductor.   7. The semiconductor chip according to claim 6, further comprising a tin-containing joint at the bottom of the first capacitor.   The semiconductor chip of claim 1, wherein the inductor comprises a copper layer having a thickness between 1.5 and 15 micrometers. A semiconductor chip,
A semiconductor substrate;
A first 1D MO S devices located on said semiconductor substrate,
A second DMOS device on the semiconductor substrate;
A first capacitor above the semiconductor substrate;
An inductor having a first terminal and a second terminal above the semiconductor substrate, wherein the first terminal of the inductor is coupled to a first terminal of the first DMOS device and a first terminal of the second DMOS device. An inductor coupled to the first capacitor, the second terminal of the inductor;
A switch controller coupled to the gate of the first DMOS device and the gate of the second DMOS device;
A voltage feedback device having a first terminal coupled to the second terminal of the inductor and the first capacitor; and a second terminal coupled to the switch controller;
An on-chip capacitor coupled to a second terminal of the first DMOS device;
A semiconductor chip comprising:   10. The semiconductor chip according to claim 9, further comprising a passivation layer above the semiconductor substrate, wherein the passivation layer includes a nitride layer, and the first capacitor is above the passivation layer. There is a semiconductor chip.   11. The semiconductor chip of claim 10, wherein the nitride layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers.   The semiconductor chip according to claim 9, further comprising a passivation layer above the semiconductor substrate, the passivation layer comprising a nitride layer, and the inductor being above the passivation layer. Semiconductor chip.   13. The semiconductor chip of claim 12, wherein the nitride layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers.   14. The semiconductor chip according to claim 13, further comprising a passivation layer above the semiconductor substrate, the passivation layer comprising a nitride layer, and the on-chip capacitor above the passivation layer. A semiconductor chip.   15. The semiconductor chip of claim 14, wherein the nitride layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers. A semiconductor chip,
A semiconductor substrate;
An inductor above the semiconductor substrate;
A first capacitor above the semiconductor substrate;
Wherein a first 1D MO S devices in the semiconductor substrate, a first terminal of the first 1DMOS device is coupled to a first terminal of the inductor, and the 1DMOS device,
A second DMOS device on the semiconductor substrate, the first terminal of the inductor and a gate coupled to the first DMOS device, the first terminal of the inductor, the first DMOS device, and the second DMOS device A second DMOS device having a first terminal of the second DMOS device coupled to the gate of the second DMOS device and a second terminal of the second DMOS device coupled to the first capacitor;
A switch controller coupled to the gate of the first DMOS device;
A voltage feedback device having a first terminal coupled to the second terminal of the second DMOS device and the first capacitor, and a second terminal coupled to the switch controller;
An on-chip capacitor coupled to a second terminal of the first DMOS device;
A semiconductor chip comprising:   17. The semiconductor chip according to claim 16, further comprising a passivation layer above the semiconductor substrate, wherein the passivation layer includes a nitride layer, and the first capacitor is above the passivation layer. There is a semiconductor chip.   18. The semiconductor chip of claim 17, wherein the nitride layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers.   The semiconductor chip according to claim 16, further comprising a passivation layer above the semiconductor substrate, the passivation layer comprising a nitride layer, and the inductor being above the passivation layer. Semiconductor chip.   20. The semiconductor chip of claim 19, wherein the nitride layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers.   17. The semiconductor chip according to claim 16, further comprising a passivation layer above the semiconductor substrate, wherein the passivation layer comprises a nitride layer, and the on-chip capacitor is above the passivation layer. A semiconductor chip.   The semiconductor chip of claim 21, wherein the nitride layer comprises a silicon nitride layer having a thickness greater than 0.3 micrometers.

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