TW396584B - The producing method of the electrostatic discharge protective circuit in IC - Google Patents

The producing method of the electrostatic discharge protective circuit in IC Download PDF

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Publication number
TW396584B
TW396584B TW86111713A TW86111713A TW396584B TW 396584 B TW396584 B TW 396584B TW 86111713 A TW86111713 A TW 86111713A TW 86111713 A TW86111713 A TW 86111713A TW 396584 B TW396584 B TW 396584B
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Taiwan
Prior art keywords
electrostatic discharge
protection circuit
integrated circuit
manufacturing
discharge protection
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TW86111713A
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Chinese (zh)
Inventor
Ruei-Yun Shiue
Jin-Shan Hou
Yi-Shiun Wu
Lin-Jiun Wu
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Taiwan Semiconductor Mfg
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Publication of TW396584B publication Critical patent/TW396584B/en

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

This is a production method of the electrostatic discharge protective circuit in IC. The field effect transistor's gate oxide layer, gate plate, source plate, and butted drain are formed on the P semiconductor's substrate board. A layer of dielectric layer covers the whole semiconductor substrate board's surface. Than, a contact is opened on the top of N+ drain plate to implant the P+ dopant into the contacts opening drain plate of semiconductor substrate board contacts. It completes a N+/P+/N+ serious connection diode butted drain. It finally becomes a metal connecting line. This invention only implants the P+ dopant onto the smaller dimension contacts opening, mean. It not only decreases the protection circuit's collapse voltage to 2 volt, but also reduces this electrostatic discharge protection circuit's electric currency leakage while it is in static status and the capacitance contacts.

Description

A7 B7 經濟部中央棣隼局貝工消費合作社印製 五、發明説明（/) (一) 技術領域 本發明係關於積體電路的製造方法，特別係關於積體 電路兀件的靜電放電(electrostatic discharge ; ESD)保護電路 的製造方法。 (二) 發明背景 保護積體電路元件不受到靜電放電電壓影響，對設計 兀件而言是一項熟悉的課題。請參閱圖一，當一個巨大的 靜電放電電壓(如人體所帶靜電可大於2000伏特)出現在積體 電路晶片的輸出/入焊塾(bonding pad)l時，會損壞連接至 此焊墊的積體電路元件5。爲了便於說明，我們將積體電路 元件與焊墊連接的節點稱爲保護節點A。 當焊墊上沒有電壓，或者焊墊電壓在正常信號電壓的 範圍內’靜電放電保護電路3不會啓動，不致影響晶片的操 作電路。當焊墊電壓與正常信號電壓同極性，但高於正常 範圍時’保護電路會開啓，鉗位焊墊的電壓，以保護積體 電路元件不受到靜電放電電壓的傷害。 當焊墊上出現極性相反的高電壓時，可以有許多不同 的方式來保護元件，例如可參閱台灣積體電路製造股份有 限公司的台灣專利第083，143號以及第079,945號的說明書。 請繼續參閱圖一，最簡單的靜電放電保護電路3(可參考 Weste等人所著”Principle of CMOS VLSI design，，,第227-229 頁，1985) ’是一對由PMOS 31和NMOS 33所構成的鈕位二 極體(clamp diode)。在保護節點A的電壓維持在正常信號電 壓的範圍內，保護電路之PM0S 31和NM0S 33所構 2 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） B7 五、發明説明（2) 經濟部中央標隼局員工消费合作社印繁 成的鉗位二極體都是逆向偏壓，兩者皆會保持關閉，不致 影響電路的操作。但若是銲墊1出現堆積的靜電荷所導致了 很高的電壓時，就會經傳送至節點A，隨著此電壓的上升， 會造成PMOS 31和NMOS 33的崩潰，使大部份的靜電放電 電流都經由此NMOS 33而接地，不會對積體電路造成傷 害。 傳統形成靜電放電保護電路的作法，是在NMOS 33的 汲極中植入磷離子，如此製作的保護電路其NMOS二極體之 崩潰電壓約在8伏特左右，然而在邁入深次微米(deep submicron) 積體電路領域之後 ，積體電路的尺寸越來越小 ，在 閘氧化層的厚度小於100埃以下的積體電路，因爲： Q = CV ⑴ 在堆積相同數目靜電荷Q的狀況下，其電容值C增大，造成 了積體電路的崩潰電壓V變小，僅約爲7伏特左右，比起保 護電路的崩潰電壓(8伏特左右)還小，如此一來靜電放電保 護電路就失去保護積體電路的功用了。因此另一種改在 NMOS 33的汲極中植入硼離子以形成N+P嘴面的設計就被 提出，雖然可以降低靜電放電保護電路的崩潰電壓，但是 卻有靜止狀態(standby mode)漏電流過大的缺點，影響了積 體電路的表現(performance)。 (三)發明的簡要說明 本發明之主要目的爲提供一種積體電路之靜電放電保 護電路的製造方法，將保護電路的崩潰電壓減少爲僅約2伏 3 1^^------訂 (請先閲讀背面之注意事項再填寫本頁) 本紙浪又度適用中國國豕樣车（CNS ) A4規格（210X 297公董） 經濟部中央標隼局員工消費合作社印製 A7 _B7_ 五、發明説明（)） 特左右，可以有效地保護深次微米積體電路不會受到靜電 放電的傷害。 本發明之次要目的爲提供一種積體電路之靜電放電保 護電路的製造方法，將離子佈植的區域僅限於接觸窗內， 可以縮小漏電流的區域，而達到降低漏電流以及接面電容 值的功效。 本發明係利用以下的製程方式，而達成上述之各種目 的：首先，在P型半導體基板表面形成一層閘氧化層，然 後，繼續定義形成複晶矽閘極於所述閘氧化層之上，接 著，形成側壁子於所述複晶矽閘極的兩側，繼續形成N+濃 摻雜的汲極區域後，再形成一層間介電層於整個半導體基 板表面，然後，以微影及蝕刻技術，在所述層間介電層打 開一個接觸窗，接著，將P+型雜質自所述接觸窗的開口處 植入所述半導體基板內，形成一個pt摻雜的區域於所述N+ 汲極區域與所述P型半導體基板接面，此步驟爲本發明之 重點所在，不像習知技藝般在形成一層間介電層前進行全 面性的P+離子佈植，本發明僅在較小面積的接觸窗開口處 植入P+型雜質，不但可以降低N+P+接面基納二極體的崩潰 電壓，同時更改善了此靜電放電保護電路於靜止狀態的漏 電流現象，進而也提升了積體電路產品的表現，另一方 面，也形成一個N+/P+/N+串聯二極體對汲極（butted drain)，進一步降低串聯電阻，最後，在形成電晶體各極 與外界接觸的金屬連線，本發明所述之深次微米積體電路 之靜電放電保護電路的製造方法於焉完成。 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) --------11----丁 、τ 『 一 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 A7 ___B7_ 五、發明説明（f) (四) 圖示的簡要說明 圖一爲習知技藝保護電路的電路示意圖。 圖二爲本發明實施例保護電路的製程剖面圖。 圖三爲習知技藝與本發明實施钶之保護電路的汲極電 壓電流關係比較。 (五) 發明的詳細說明 本發明實施例之保護電路係以製作在P型基板的N型 摻雜區，但熟知此技藝人士皆能輕易明瞭，本發明實施例 之保護電路也可以製作在N型基板的P型摻雜區中，而達 到相同的效果，彼此的結構都互相對應，毋需具體說明也 應很清楚β 請參閱圖二，是本發明保護電路的剖面圖，爲了說明 簡便起見，圖示中僅顯示了Ν+二極體33的部分。首先，在 晶格方向爲(100)或(111)的Ρ型半導體基板101表面形成一層 閘氧化層(gate oxide)103，然後，繼續定義形成複晶矽閘極 105於所述閘氧化層103之上，接著，形成側壁子107於所述 複晶矽閘極105‘的兩側，如圖二所示。 所述半導體基板101，通常是成分爲矽或是砷化鎵 (GaAs)的半導體晶圓，所述閘氧化層103係利用熱氧化法將 所述半導體基板101之表面的矽原子而形成，以〇.35μπι的製 程爲例，其厚度係介於65到75埃之間。所述複晶矽閘極105 通常是利用同步攙雜磷(in-situ phosphorus doped)之低壓化學 氣相沈積法(LPCVD)所形成，其反應氣體是15%PH3 + 85% 5_ 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） --^-------ί'裝------訂------4 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消费合作社印製 A7 ____B7 五、發明説明（j：)A7 B7 Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, V. Description of the Invention (/) (1) Technical Field The present invention relates to a method for manufacturing integrated circuits, and particularly to electrostatic discharge of integrated circuit components. discharge; ESD) manufacturing method of protection circuit. (II) Background of the Invention Protecting integrated circuit components from electrostatic discharge voltage is a familiar issue for designing components. Please refer to Figure 1. When a large electrostatic discharge voltage (such as the static electricity carried by the human body can be greater than 2000 volts) appears on the output / input bonding pads of the integrated circuit chip, the product connected to this pad will be damaged.体 电路 Element5. The body circuit element 5. For the convenience of explanation, the node where the integrated circuit component is connected to the bonding pad is called a protection node A. When there is no voltage on the pads, or the pad voltage is within the range of the normal signal voltage, the ESD protection circuit 3 will not start and will not affect the operation circuit of the wafer. When the pad voltage is the same polarity as the normal signal voltage, but above the normal range, the 'protection circuit will open and clamp the pad voltage to protect the integrated circuit components from being damaged by electrostatic discharge voltage. When high voltages of opposite polarity appear on the pads, there are many different ways to protect the components. For example, see Taiwan Patent Nos. 083,143 and 079,945 of Taiwan Semiconductor Manufacturing Co., Ltd. Please continue to refer to Figure 1. The simplest electrostatic discharge protection circuit 3 (refer to "Principle of CMOS VLSI design by Weste et al.," Pages 227-229, 1985) 'is a pair of PMOS 31 and NMOS 33 A clamp diode. The voltage of the protection node A is maintained within the range of the normal signal voltage. The protection circuit is composed of PM0S 31 and NM0S 33. 2 (Please read the precautions on the back before filling this page ) This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) B7 V. Description of the invention (2) The clamp diodes printed and produced by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs are reverse biased. Both will remain closed and will not affect the operation of the circuit. However, if a high voltage is caused by the accumulated static charge on pad 1, it will be transmitted to node A, and as this voltage rises, it will cause PMOS The collapse of 31 and NMOS 33 caused most of the electrostatic discharge current to be grounded through this NMOS 33, which will not cause damage to the integrated circuit. The traditional method of forming an electrostatic discharge protection circuit is to plant the drain of NMOS 33 Into the phosphorus The breakdown voltage of the NMOS diode of the protection circuit thus produced is about 8 volts. However, after entering the field of deep submicron integrated circuits, the size of integrated circuits is getting smaller and smaller, and the gate is oxidized. The thickness of the integrated circuit is less than 100 angstroms because: Q = CV ⑴ When the same number of electrostatic charges Q are accumulated, the capacitance value C increases, causing the integrated circuit's collapse voltage V to become smaller, only about It is about 7 volts, which is smaller than the breakdown voltage of the protection circuit (about 8 volts). In this way, the electrostatic discharge protection circuit loses the function of protecting the integrated circuit. Therefore, another type is implanted in the drain of NMOS 33. The design of boron ions to form the N + P mouth surface has been proposed. Although it can reduce the breakdown voltage of the electrostatic discharge protection circuit, it has the disadvantage of excessive leakage current in the standby mode, which affects the performance of the integrated circuit. (3) Brief description of the invention The main object of the present invention is to provide a method for manufacturing an integrated circuit electrostatic discharge protection circuit, which reduces the breakdown voltage of the protection circuit to only about 2 volts. 3 1 ^^ ------ Order (Please read the precautions on the back before filling this page) This paper is again applicable to China National Sample Car (CNS) A4 specification (210X 297 public directors) Central Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau A7 _B7_ Fifth, the invention description ()) can effectively protect deep sub-micron integrated circuits from being harmed by electrostatic discharge. The secondary purpose of the present invention is to provide static electricity for integrated circuits The manufacturing method of the discharge protection circuit limits the area where the ions are implanted to the contact window, which can reduce the area of the leakage current, thereby achieving the effects of reducing the leakage current and the capacitance of the interface. The present invention uses the following process methods to achieve the above-mentioned various objectives: first, a gate oxide layer is formed on the surface of the P-type semiconductor substrate, and then, a polycrystalline silicon gate electrode is further defined to form the gate oxide layer, and then Forming sidewalls on both sides of the polycrystalline silicon gate, and continuing to form an N + heavily doped drain region, and then forming an interlayer dielectric layer on the entire surface of the semiconductor substrate, and then using lithography and etching techniques, A contact window is opened in the interlayer dielectric layer, and then a P + type impurity is implanted into the semiconductor substrate from the opening of the contact window to form a pt-doped region between the N + drain region and the N + drain region. This step is the focus of the present invention. Unlike conventional techniques, which do not perform a comprehensive P + ion implantation before forming an interlayer dielectric layer, the present invention only applies to contact windows with a small area. Implanting a P + -type impurity in the opening can not only reduce the breakdown voltage of the G + diode at the N + P + interface, but also improve the leakage current phenomenon of the electrostatic discharge protection circuit in the static state. The performance of integrated circuit products, on the other hand, also formed an N + / P + / N + series diode pair drain (butted drain), which further reduced the series resistance. Finally, in the formation of the metal contact between the electrodes of the transistor and the outside Line, the manufacturing method of the electrostatic discharge protection circuit of the deep sub-micron integrated circuit according to the present invention is completed. 4 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -------- 11 ---- Ding, τ 『I (Please read the precautions on the back before filling this page) Economy Printed by A7 _B7_ of the Consumer Standards Cooperative of the Ministry of Standards of the People's Republic of China 5. Description of the Invention (f) (4) Brief Description of the Figures Figure 1 is a schematic circuit diagram of the protection circuit of the conventional technology. FIG. 2 is a process cross-sectional view of a protection circuit according to an embodiment of the present invention. Figure 3 is a comparison of the relationship between the drain voltage and the current of the conventional art and the protection circuit of the present invention. (5) Detailed description of the invention The protection circuit of the embodiment of the present invention is made in the N-type doped region of the P-type substrate, but those skilled in the art can easily understand that the protection circuit of the embodiment of the present invention can also be made in N In the P-type doped region of the P-type substrate, the same effect is achieved, and the structures of each other correspond to each other. It should be clear without specific description. Please refer to FIG. 2, which is a cross-sectional view of the protection circuit of the present invention. See, only the portion of the N + diode 33 is shown in the illustration. First, a gate oxide layer 103 is formed on the surface of the P-type semiconductor substrate 101 with a lattice direction of (100) or (111), and then, a polycrystalline silicon gate electrode 105 is further defined to form the gate oxide layer 103. Above, then, side walls 107 are formed on both sides of the complex silicon gate 105 ′, as shown in FIG. 2. The semiconductor substrate 101 is generally a semiconductor wafer composed of silicon or gallium arsenide (GaAs). The gate oxide layer 103 is formed by thermally oxidizing silicon atoms on the surface of the semiconductor substrate 101 to For example, the thickness of 0.35 μm is between 65 and 75 angstroms. The polycrystalline silicon gate 105 is generally formed by a low pressure chemical vapor deposition (LPCVD) method using synchronous in-situ phosphorus doped. The reaction gas is 15% PH3 + 85% 5_ This paper is applicable to China National Standard (CNS) A4 specification (210X297 mm)-^ ------- ί 'installed ------ order ------ 4 (Please read the notes on the back before filling (This page) Printed A7 ____B7 by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (j :)

SiH4與5%PH3 + 95%N2的混合氣體，反應溫度約爲550°C， 其厚度介於1000到3000埃之間。 請繼續參閱圖二，形成N+濃摻雜的汲極區域109後，再 形成一層間介電層111於整個半導體基板101表面，然後， 以微影及蝕刻技術，在所述層間介電層111打開一個接觸窗 113，接著，將P+型雜質115自所述接觸窗113的開口處植入 所述半導體基板101內，形成一個P+摻雜的區域117於所述 Νϋ極區域109與所述P型半導體基板101接面，如圖二所 示。此步驟爲本發明之重點所在，不像習知技藝般在形成 一層間介電層前進行全面性的Ρ +離子佈植，本發明僅在較 小面積的接觸窗113開口處植入Ρ+型雜質，不但可以降低 Ν+Ρ+接面基納二極體的崩潰電壓，同時更改善了此靜電放 電保護電路於靜止狀態的漏電流現象，另一方面，也形成 一個Ν+/Ρ+/Ν+串聯二極體對汲極(butted drain)，進一步 降低串聯電阻，進而也提升了積體電路產品的表現，。最 後，在形成電晶體各極與外界接觸的金屬連線(未於圖中標 出），本發明所述之深次微米積體電路之靜電放電保護電路 的製造方法於焉完成。 所述N+濃摻雜的源極區域109，通常是利用離子植入法 植入砷(As75)離子，其離子植入能量爲20到80 keV之間， 而離子植入劑量介於1E15到5E15離子/平方公分之間。所 述層間介電層111通常是利用電漿增強式化學氣相沈積法 (PECVD)所形成的四乙氧基砍院(tetrathoxysilane ; TEOS)， 其厚度介於1000到3000埃之間。但所述層間介電層111也可 _ 6 _ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） H - ί - I - -I - I. .... —^- - ---- ill —- s - - (請先閲讀背面之注意事項再填寫本頁) 經满部中央標準局員工消费合作社印製 A7 _____B7 五、發明説明（/) 以是硼磷攙雜玻璃膜(BPSG)等材料。而所述p+型雜質通常 也是利用離子植入法植入硼(B11)或二氟化硼(BF2)離子，其 離子植入能量係介於50到80 keV之間，而離子植入劑量介 於1E13到2E14離子/平方公分之間。 請參閱圖三，爲臺灣積體電路製造股份有限公司之研 發成果，顯示了習知技藝與本發明實施例之保護電路的汲 極電壓(VD-VB)電流(ID)關係比較，可由圖中看出，利用本發 明實施例所製作的靜電放電保護電路，適當地選取植入離 子的劑量(dose)，即可以降低其N+P+接面(即圖一中的N+ 二極體33)的崩潰電壓僅約2伏特左右，較以往設計的靜電放 電保護電路之崩潰電壓(約8伏特左右)降低許多，因此可以 有效地作爲深次微米積體電路之靜電放電保護電路之用， 以70埃的閜氧化層之積體電路爲例，其崩潰電壓約爲7伏特 左右。 在保護節點A的電壓維持在正常信號電壓的範圍內，保 護電路之N+二極體33就會保持關閉，不致影響電路的操 作。但若是銲墊1出現堆積的靜電荷所導致了很高的電壓 時，就會經傳送至節點A，隨著此電壓的上升，會造成N+P +接面(即圖一中的N+二極體33)的崩潰，使大部份的靜電放 電電流都經由此一N+P+接面而接地，不會對積體電路造成 傷害。 上述說明係以較佳實施例來闡述本發明，而非限制本 發明’並且，熟知半導體技藝之人士皆能明瞭，適當而作 _______7______ 本纸張纽適用中SS家鮮（CNS M4規格（210X297公釐1 ' -I I I is -I —I —I— —II ....... - I - . -- (請先閲讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（y )些微的改變及調整，仍將不失本發明之要義所在，亦不脫 離本發明之精神和範圍。 ’ (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標隼局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）SiH4 and 5% PH3 + 95% N2 mixed gas, the reaction temperature is about 550 ° C, and its thickness is between 1000 and 3000 Angstroms. Please continue to refer to FIG. 2. After the N + heavily doped drain region 109 is formed, an interlayer dielectric layer 111 is formed on the entire surface of the semiconductor substrate 101. Then, the interlayer dielectric layer 111 is formed by lithography and etching techniques. A contact window 113 is opened, and then a P + -type impurity 115 is implanted into the semiconductor substrate 101 from the opening of the contact window 113 to form a P + doped region 117 between the Nϋ electrode region 109 and the P The interface of the semiconductor substrate 101 is shown in FIG. This step is the focus of the present invention. Unlike the conventional technique, which does not perform a comprehensive P + ion implantation before forming an interlayer dielectric layer, the present invention only implants P + at the opening of the contact window 113 with a small area. Type impurities, which can not only reduce the breakdown voltage of the N + P + junction kena diode, but also improve the static current leakage phenomenon of this electrostatic discharge protection circuit. / N + series diode to drain (butted drain), further reducing the series resistance, which also improves the performance of integrated circuit products. Finally, the manufacturing method of the electrostatic discharge protection circuit of the deep sub-micron integrated circuit according to the present invention is completed after forming the metal connection between the electrodes of the transistor and the outside (not shown in the figure). The N + heavily doped source region 109 is usually implanted with arsenic (As75) ions by ion implantation, the ion implantation energy is between 20 and 80 keV, and the ion implantation dose is between 1E15 and 5E15. Ions / cm2. The interlayer dielectric layer 111 is usually a tetrathoxysilane (TEOS) formed by a plasma enhanced chemical vapor deposition (PECVD) method, and has a thickness between 1000 and 3000 angstroms. However, the interlayer dielectric layer 111 may also be _ 6 _ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) H-ί-I--I-I. .... — ^--- --- ill —- s--(Please read the notes on the back before filling this page) Printed by the Consumer Standards Cooperative of the Central Bureau of Standards A7 _____B7 V. Description of Invention (/) It is a borophosphorus doped glass film ( BPSG) and other materials. The p + -type impurities are usually implanted with boron (B11) or boron difluoride (BF2) ions by ion implantation. The ion implantation energy is between 50 and 80 keV. Between 1E13 and 2E14 ions / cm². Please refer to Figure 3, which shows the research and development results of Taiwan Semiconductor Manufacturing Co., Ltd., which shows the comparison between the drain voltage (VD-VB) current (ID) of the conventional technique and the protection circuit of the embodiment of the present invention. It can be seen that by using the electrostatic discharge protection circuit manufactured in the embodiment of the present invention, the dose of implanted ions can be appropriately selected, that is, the N + P + junction (ie, the N + diode 33 in FIG. 1) can be reduced. The breakdown voltage is only about 2 volts, which is much lower than the collapse voltage (about 8 volts) of conventionally designed electrostatic discharge protection circuits. Therefore, it can be effectively used as an electrostatic discharge protection circuit for deep sub-micron integrated circuits. As an example, the integrated circuit of a plutonium oxide layer has a breakdown voltage of about 7 volts. When the voltage of the protection node A is maintained within the range of the normal signal voltage, the N + diode 33 of the protection circuit will remain closed, which will not affect the operation of the circuit. However, if a high voltage is caused by the accumulated static charge on pad 1, it will be transmitted to node A. As this voltage rises, it will cause the N + P + junction (that is, N + 2 in Figure 1). The collapse of the pole body 33) causes most of the electrostatic discharge current to be grounded through this N + P + interface, which will not cause damage to the integrated circuit. The above description is to illustrate the present invention with a preferred embodiment, but not to limit the present invention. Moreover, those skilled in the art of semiconductors will be able to understand and make it appropriate. 1 '-III is -I —I —I— —II .......-I-.-(Please read the notes on the back before filling this page) A7 B7 V. Description of the invention (y ) Minor changes and adjustments will still not lose the essence of the invention, nor deviate from the spirit and scope of the invention. '(Please read the precautions on the back before filling this page) Order the staff consumption of the Central Bureau of Standards of the Ministry of Economic Affairs The paper size printed by the cooperative is applicable to the Chinese National Standard (CNS) A4 (210X297 mm)

Claims (1)

經濟部中央標準局貝工消费合作社印裂 A8 B8 C8 D8 六、申請專利範圍 1. 一種積體電路之靜電放電保護電路的製造方法，該保護雩 路是一互補式場效電晶體，其第一導電型態場效重晶體 之汲極與‘電壓源相連，而第二導璽型麓場效電晶體之源 極則接地，係包含下列歩驟二 ⑻形成一互補式場效電晶體於第一導電型態半導體基 板的表面，所述場效電晶體係包含：閘氧化層、閘極、 源極和汲極； (b) 形成一層間介電層於整個半導體基板的表面，韮在 所述第二型態場效電晶體韵源極:開接觸窗； (c) 將第一導電型態雜質植入所述接觸窗開口的所述第 二導電型態場效電晶體汲極與所述半導體基板接面處， 以形成一個二極體；以及 (d) 形成金屬連線。 2. 如申請專利範圍第1項之積體電路之靜電放電保護電路的 製造方法，其中所述半導體基板是選自矽和砷化鎵(GaAs) 竽導體晶圓之一。 3. 如申請專利_圍第1項之積體電路之靜電放電保護電路的 製造方法，其中所述第一導電型態與第二導電型態是相 反的導電型態。 4. 如申請專利範圍第3項之積體電路之靜電放電保護電路放 製造方法，其中所述第一導電型態悬P型(重洞）。 5. 如申請專利範圍第1項之積體電路之靜電放電保護電路的 製造方法，其中所述第·-導電型態雜質是選自硼(B11)、 二m化珊(BF2)等離子之一。 9 本紙張尺度適用中國國家棵準（CNS ) A4规格（210X297公釐） ,---------1¾------1T------4. (請先閲讀背面之注意事項再填寫本頁) 經濟部中夬棣準局員工消费合作社印製 396584 含 8: ____D8 六、申請專利範圍 6. 如申請專利範圍第5項之積體電路之靜電放電保護電路的 製造方法，其中所述離子係利用能量介於50到8〇 keV之 間，植入劑量介於1E13到2E14離子/平方公分之間的離 子。 7. —種的積體電路靜電放電保護電路之場效電晶體的製造方 法，係包含下列步驟： (a) 形成閘氧化層、閘極、源極和汲極於半導體基板 上； (b) 形成一層間介電層於整個半導體基扳的表面，魏在 所述汲極的上方打開接觸窗； (c) 將與所述汲極導電型態相反的雜質植入所述接觸窗 開口的所述汲極與所述半導體基板接面處，以形成一個 二極體；以及 ⑷形成金屬連線。 8·如座請專利範圍第7項之積體電路之靜電放電保護電路的 製造方法，其中斯述单導體基板是選直砂和砷化鎵(GaAs)半導體晶圓乏一。 ---- ------- 9. 如申請專利範圍第7項之積體電路之靜電放電保護電路的 製造方法，其中所述汲極的導電型態是N型(電子）。 10. 如申請專利範圍第7項之積體電路之靜重放重保護重路 的製造方法上其中所述與汲極導重型態担反的雜質是選 自硼(B11)、二氟等離子之一。 11. 如申請專利範圍第10項之積體電路之靜電放電保護電路 的製造方法，其中所述離子係利用能量介於50到?0 10 —；------i------IT------^ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS > A4规格（210X297公釐） 經濟部中央標隼局員工消費合作社印装 396584 S D8 六、申請專利範圍 keV之間，植入劑量介於1E13到2E14離子/平方公分之. 間的離子。 (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 本纸張尤变適用中國國家標準（CNS ) A4規格（210X297公釐）The Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed A8, B8, C8, and D8. 6. Application for Patent Scope 1. A method for manufacturing an integrated circuit's electrostatic discharge protection circuit. The protection circuit is a complementary field-effect transistor. The drain of the conductive type field effect heavy crystal is connected to the 'voltage source, and the source of the second conduction type field effect transistor is grounded, which includes the following steps 2 to form a complementary field effect transistor on the first The surface of the conductive type semiconductor substrate, the field effect transistor system includes: a gate oxide layer, a gate electrode, a source electrode, and a drain electrode; (b) forming an interlayer dielectric layer on the surface of the entire semiconductor substrate, A second-type field-effect transistor rhyme source electrode: opening a contact window; (c) implanting a first-conductivity-type impurity into the second-conduction-type field-effect transistor drain electrode and the opening of the contact window; Forming a diode at the junction of the semiconductor substrate; and (d) forming a metal connection. 2. The manufacturing method of the electrostatic discharge protection circuit of the integrated circuit according to item 1 of the patent application scope, wherein the semiconductor substrate is one selected from silicon and gallium arsenide (GaAs) plutonium conductor wafer. 3. For example, the manufacturing method of the electrostatic discharge protection circuit of the integrated circuit of item 1 in the patent application, wherein the first conductive type and the second conductive type are opposite conductive types. 4. The manufacturing method of the electrostatic discharge protection circuit of the integrated circuit according to item 3 of the application for a patent, wherein the first conductive type is a P-type (heavy hole). 5. The manufacturing method of the electrostatic discharge protection circuit of the integrated circuit according to item 1 of the scope of the patent application, wherein the first conductive type impurity is one selected from the group consisting of boron (B11) and dm2 (BF2) plasma. . 9 This paper size is applicable to China National Standard (CNS) A4 (210X297mm), --------- 1¾ ------ 1T ------ 4. (Please read the back first Please pay attention to this page, please fill in this page) Printed by the Consumers' Cooperatives of the Ministry of Economic Affairs of the Ministry of Economic Affairs 396584 Including 8: __D8 VI. Application for patent 6. Manufacture of electrostatic discharge protection circuit for integrated circuits such as item 5 of the patent application The method, wherein the ion system uses ions having an energy between 50 and 80 keV and implanting a dose between 1E13 and 2E14 ions / cm 2. 7. A method for manufacturing a field effect transistor of an integrated circuit electrostatic discharge protection circuit, comprising the following steps: (a) forming a gate oxide layer, a gate electrode, a source electrode and a drain electrode on a semiconductor substrate; (b) An inter-dielectric layer is formed on the entire surface of the semiconductor substrate, and Wei opens a contact window above the drain electrode; (c) implants an impurity of the opposite conductivity type from the drain electrode into the contact window opening. A junction between the drain and the semiconductor substrate to form a diode; and ⑷ forming a metal connection. 8. The manufacturing method of the electrostatic discharge protection circuit of the integrated circuit as described in item 7 of the patent, wherein the single-conductor substrate is selected from the group consisting of straight sand and gallium arsenide (GaAs) semiconductor wafers. ---- ------- 9. The manufacturing method of the electrostatic discharge protection circuit of the integrated circuit according to item 7 of the patent application scope, wherein the conductive type of the drain electrode is N-type (electron). 10. According to the manufacturing method of the static replay protection heavy circuit of the integrated circuit of item 7 in the scope of the patent application, the impurity opposite to the heavy state of the drain electrode is selected from the group consisting of boron (B11) and difluoride plasma. one. 11. The manufacturing method of the electrostatic discharge protection circuit of the integrated circuit according to item 10 of the patent application scope, wherein the ion system uses energy between 50 and? 0 10 —; ------ i ----- -IT ------ ^ (Please read the notes on the back before filling out this page) This paper size applies to the Chinese National Standard (CNS > A4 size (210X297 mm)) Packing 396584 S D8 6. Between patent application range keV, implant dose between 1E13 to 2E14 ions / cm². (Please read the precautions on the back before filling this page)-Binding and binding Zhang Youbian applies the Chinese National Standard (CNS) A4 specification (210X297 mm)
TW86111713A 1997-08-14 1997-08-14 The producing method of the electrostatic discharge protective circuit in IC TW396584B (en)

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US7915161B2 (en) 2000-10-18 2011-03-29 Megica Corporation Post passivation interconnection schemes on top of IC chip
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