4370 4 9 '發明說明（ 洋細說明： 技術領域： 件的積體電路中形成高壓靜電保護元 爯特別是關於一種具有低彈回電壓之靜 每保叙件的製作方法及其結構。 發明背景： 對於以金氧半場效電晶體所形 成的積體電路而言，外 二所輸入的afl雜連接至所述金氧半場效電晶體的問極。 經濟部智慧財產局員工消費合作社印製 A7 B7 五 右外界所輪入訊號的電壓過大，則閘極介電層會崩潰 (^Breakdown)而使元件損害。所述閘極介電層通常是一熱 氧化層’其抗電壓之強度約為1E7至2E7伏特/公分。以深 一欠微米製程而言’閘極介電層的厚度僅約為40A，亦即僅 能抵抗4至8伏特的電壓，若外界所輸入訊號大於8伏特， 則閘極介電層會崩潰。雖然目前積體電路通用的工作電壓 一般為3.3或2.5伏特，低於所述的8伏特，但是積體電路在 製作和使用的過程中，其輸入端經常會有來自人體或機械 具極高電壓的靜電（可能高於4000伏特），因而造成積體 電路内部元件的損壞。因此針對積體電路每一接腳的銲墊 (Bonding Pad)，在銲墊和内部元件之間都必須有靜電保護 電路，以便在外來的高壓靜電進入内部元件之前便將其接 地。如何保護積體電路元件以避免受到高壓靜電放電電壓 的影響，對設計元件而言是一項非常重要的課題。另外特 別重要的是，所述高壓靜電保護元件承受高壓靜電的彈回 電壓(5napback Voltage)不能過高，否則在承受兩壓靜電 本纸張尺度適用中國囤家標準（CNS)A4規格（21〇 X 29^公釐） 437 Ο 4 9 Α7 Β7 濟 部 智 慧 財 產 局 員 消 費 合 作 社 印 製 五、發明說明（>) 放電時會產生高熱而使該元件損壞，如此便失去高壓靜電 保護元件的功能。 請參考圖一 ’係習知南壓靜電保護元件的結構剖面 圖。圖一所示係位於一半導體基板10上的N型金氡半場效 電晶體1Ί (以後皆簡稱NMOS)，其包含一閘極介電層 (Gate Die丨ectric)12、閘極導電層13、淡摻雜源/汲極區 (Lightly Doped Drain/Source; LDD)15、介電質間隙壁 (Insulator Spacer)16、和源極/汲極區（s〇Urce/Drain)14。 另外，為了形成高壓靜電保護元件’在形成淡摻雜源/汲極 區15之前或之後並以一道具高能量且深摻雜的離子佈植形 成一 N型深摻雜區（N-type Deep Drain;以後皆簡稱 NDD) 17以加深PN接面的深度’改善元件的手指效應 (Finger Effect)及電流承载能力。然而此方法不但會增加接 面電各而致使保護電路的反應速率（ReSp〇nse SpeeCJ)變 忮，更嚴重的是，因為此一結構電晶體的彈回電壓極高， 因此所述高壓靜電保護元件無法承受高電壓的靜電，大約 ，承受2000伏特的電壓下即因產生高熱而燒毁，因而失去 向麗靜電保護元件的功能。 因此，形成一種具低彈回電壓的高壓靜電保護元件， 能持續地將外界的高壓靜電接地以保護内部元件，同時高 壓靜電保護元件自身不會被燒毁’是各積體電路公司一項 非常重要的課題。 發明概述： 本發明的主要目的為提供一種在積體電路中形成高壓 本紙張尺度晒家鮮（CN^4驗（膨 4 3 7 u 4 94370 4 9 'Explanation of the invention (foreign explanation: technical field: formation of high-voltage electrostatic protection elements in integrated circuits of components, in particular, a manufacturing method and structure of a static protection component with a low rebound voltage]. BACKGROUND OF THE INVENTION : For integrated circuits formed of metal-oxide-semiconductor half-field-effect transistors, the afl input from the second input is connected to the questionnaire of the metal-oxide-semiconductor half-field-effect transistors. A7 printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs B7 If the voltage of the external signal is too high, the gate dielectric layer will collapse (^ Breakdown) and damage the device. The gate dielectric layer is usually a thermal oxide layer. Its anti-voltage strength is about 1E7 to 2E7 volts / cm. In the case of a deep-to-micron process, the thickness of the gate dielectric layer is only about 40A, that is, it can only withstand a voltage of 4 to 8 volts. If the external input signal is greater than 8 volts, the gate The dielectric layer will collapse. Although the current operating voltage of integrated circuits is generally 3.3 or 2.5 volts, which is lower than the 8 volts mentioned, the input terminals of integrated circuits are often produced by human body Or the static electricity of the machine with extremely high voltage (may be higher than 4000 volts), which causes damage to the internal components of the integrated circuit. Therefore, for the bonding pads of each pin of the integrated circuit, There must be electrostatic protection circuits in order to ground external high-voltage static electricity before it enters internal components. How to protect integrated circuit components from being affected by high-voltage electrostatic discharge voltage is very important for designing components. In addition, it is particularly important that the high-voltage electrostatic protection element withstand high-voltage static rebound voltage (5napback Voltage) should not be too high, otherwise the Chinese paper standard (CNS) A4 specification is applicable to the paper withstand two-voltage static. 21〇X 29 ^ mm) 437 〇 4 9 Α7 Β7 Printed by the Consumers' Cooperative of the Ministry of Intellectual Property of the Ministry of Finance 5. Description of the invention (>) High heat will be generated during discharge and the element will be damaged, so the high voltage electrostatic protection element will be lost. Function. Please refer to Fig. 1 for a structural cross-sectional view of a conventional south-voltage electrostatic protection element. Fig. 1 shows a semiconductor substrate. N-type gold 氡 half field effect transistor 1Ί (hereinafter referred to as NMOS) on 10, which includes a gate dielectric layer (Gate Die 丨 ectric) 12, a gate conductive layer 13, a lightly doped source / drain region ( (Lightly Doped Drain / Source; LDD) 15, dielectric spacer (Insulator Spacer) 16, and source / drain region (s0Urce / Drain) 14. In addition, in order to form a high-voltage electrostatic protection element, Before or after the hetero / drain region 15 is implanted with a high-energy and deeply doped ion implanted to form an N-type deep doped region (hereinafter referred to as NDD) 17 to deepen the PN junction 'Depth' improves the finger effect and current carrying capacity of the device. However, this method will not only increase the contact voltage and cause the response rate of the protection circuit (ReSponse SpeeCJ) to become rampant. It is even more serious because the rebound voltage of this structure transistor is extremely high, so the high-voltage electrostatic protection The component cannot withstand high-voltage static electricity. Approximately, under the voltage of 2000 volts, it is burned due to high heat generation, so it loses the function of protecting Xiangli electrostatic components. Therefore, the formation of a high-voltage electrostatic protection element with a low rebound voltage can continuously ground the external high-voltage static electricity to protect internal components, while the high-voltage electrostatic protection element itself will not be burned. Important subject. Summary of the invention: The main purpose of the present invention is to provide a high voltage in integrated circuit. This paper is sized for domestic use (CN ^ 4 inspection (expanded 4 3 7 u 4 9
五、發明說明（)） 靜電保護元件的方法。 伴1本t明的次要目的為提供一種低彈回電®之高壓靜電 保濩7L件的製作方法。 (請先閱讀背面之注意事項再填寫本頁) 本發明的再一目的為提供一種積體 護元件的結構。 本發明係揭露-種在積體電路中形成高轉電 件的方法，·本發明所形成的高壓靜電保護元件係一 N型金 氧毕場效電晶體（_〇s)，可適用於動態隨機存取記憶 體、靜態_|存取記«、以雜何_之轉電路之積 體電路的高壓靜電保護元件。 、 經濟部智慧財產局員工消費合作社印製 本發明所述方法的製程步驟包括有：利用微影及離子 佈植製程在一半導體基板上形成P型井區和N型井區，再 开>成絕緣隔離；形成所述N型井區係改變光罩的設計，在 預備形成N型金氧半場效電晶體的汲極區，亦進行N型井 區的離子佈植而形成一 N型井區。接下來形成N型金氧半 場效電晶體結構，所述金氧半場效電晶體結構包含有閘極 介電層、閘極導電層、N型摻雜汲極、淡摻雜源/汲極區、 介電質間隙壁、一源極、以及二個分離的没極。最後在所 述兩個汲極之間形成一p型濃摻雜區。 本發明所形成的高壓靜電保護元件中，由P型濃摻雜 區、N型井區、和P型井區形成一個PNp的雙極接面電 晶體；另外由N型井區、ρ型井區、和源極形成一個fsiPfs 的雙極接面電晶體。而此一 PNP和NPN即形成所謂的移 控制整流器（Silicon Controled Rectifier; SCR)。當所述 本紙張尺妓^剩家辟（CNS)A4娜咖公釐） 437〇 4 9 A7 ------- ' _____ 五、發明說明（+ ) NIVIOS的汲極承受一外來的高壓靜電時’ pnp雙極接面電 晶體的基極被NPN雙極搂面電晶體的集極所驅動’或者 NPN雙極接面電晶體的基極被pNp雙極接面電晶體的集 極所驅動’因而就驅動矽控制整流器(SCR)導通而產生彈 回效應(Snapback) ’而把靜電放電突波(esD Pulse)鎖在很 低的電壓’這樣可以將外來的靜電電荷藉由所述矽控制整 流器(SCR)排掉，如此便可保護積體電路之内部元件不會 被高壓靜電所破壞。 特別重要的是’利用本發明所述方法形成的高壓靜電 保護元件，其矽控制整流器(SCR)的工作電壓相當低’可 以降低至2伏特以下。因此當所述nm〇S的汲極承受外來 的高歷靜電時’所產生的熱量會比習用的靜電保護元件低 很多。利用本發明所述方法形成的高壓靜電保護元件可以 承受高達8000伏特以上的高壓靜電，而不會因高熱而燒 毀’可以達到保護内部元件的功效。 圖式的簡要說明： 圖一是習知技術中形成靜電保護元件的剖面示意圖。 圖二是本發明在一半導體基板上形成P型井區和N型井 區’再形成絕線隔離的剖面示意圖。 圖三是本發明中形成金氧半場效電晶體結構的剖面示意 圖。 圖四是本發明中形成P型濃摻雜區的剖面示意圖。 圖五是本發明中所形成之高壓靜電保護元件的等效電路 圖。 43 7 ϋ 4 9 五 、發明說明（/ 圖號說明： 10-半導體基板 12-閘極介電層 14-源極及極區 16-介電質間隙壁 20— Ρ型井區 30-絕緣隔離 41-閘極介電層 43- Ν型摻雜深汲極 45-介電質間隙壁 47-沒極 11- Ν型金氧半場效電晶體 13-閘極導電層 15-淡摻雜源/沒極區 17- Ν型摻雜區 21- Ν型井區 40-金氧半場效電晶體結構 42-閘極導電層 44-淡摻雜源/:及極區 46-源極 50- Ρ型濃摻雜區 本發明係揭露-個在積體電路中形成高麗靜電保護元 件的方法及其結構。本發明所形成的高歷靜電保護元件係 -问型金氧半場效電晶體⑽QS)，可翻於動態隨機 存取A憶體、靜態隨機存取記憶體、以及任 電路之積魏關魏航件。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 請參考圖二，首先利用習知標準的微影及離子佈植製 程在一半導體基板1〇上形成ρ型井區2〇和Ν型井區 21，再藉由習知的技術形成絕緣隔離3〇，並因而定義出主 動元件區。所述絕緣隔離3〇可以是傳統的區域氧化矽層 (LOCOS )，也可以是淺渠溝隔離（Shan〇w Trench Isolation) ’其作用是做為主動元件區的隔離。 所述N型井區21係位於預備形成nm〇S之汲極的區 胃本紙張尺度適用中i"國豕槔準（CNS)A4 g^f^$7 i^ I y 4 3 7 u 4 9 A7 ----- B7 ---; ----- --— 五、發明說明（A) 威’是本發明重點之一。在傳統的製程中，N型井區用來 形成PMOS而P型井區用來形成NMOS。然而本發明改 變光罩的設計，在靜電保護元件之NIVJOS汲極區的部分區 城’亦進行N型井區的離子佈植而形成一 N型井區21。 所述N型井區21，係以能量介於70至140 KeV的砷或磷 離子進行離子佈植所形成，其摻雜濃度係介於1E12到 5E13原子/平方公分之間。 接著請參考圖三，利用習知的製程技術形成金氧半場 效電晶體結構40 ’所述金氧半場效電晶體結構40包含有 閘極介電層(Gate Die丨ectr丨c)41、閘極導電層42、N型摻 雜深汲極(N-type Deep Drain;以後皆簡稱為NDD)43、淡 換雜源/:?及極區(Lightly Doped Drain/Source;以後皆簡稱為 LDD)44、介電質間隙壁（|nsL1iat〇r Spacer)45、以及源極/ 没極(Source/Drain)46。 經濟部智慧財產局員工消費合作社印製 所述閘極介電層41係以熱氧化法所形成，其厚度在 30至8〇A之間。在形成所述閘極介電層41之前或之後， 可加入一道啟始電壓調整的離子佈植製程。所述閘極導電 層42係以低壓化學氣相沉積法Pressure Chemical Vapor Deposition;以後皆簡稱為LPCVD)形成一層複晶矽 層，其厚度介於800至4000A之間。所述複晶矽層的摻 雜有兩種方法，其中之一係以砷或磷摻入反應氣體矽烷 (Silane)中，使砷或磷與矽同步沉積；另一方法係先沉積一 本質複晶矽層，再以離子佈植的技術將砷或磷摻雜入該複 晶矽層内。利用傳統的微影和非等向反應性離子蝕刻技 本紙張尺度―中國國家標準（CNS)A4 $格⑽x 2如公6V. Description of the invention ()) Method of electrostatic protection element. The secondary purpose of this book is to provide a method for manufacturing a 7L piece of high-voltage electrostatic protection with low resilience. (Please read the precautions on the back before filling out this page.) Another object of the present invention is to provide a structure of an integrated protection element. The present invention discloses a method for forming a high-voltage electric component in an integrated circuit. The high-voltage electrostatic protection element formed by the present invention is an N-type metal-oxide field-effect transistor (_〇s), which can be applied to dynamic Random access memory, static _ | access record «, high-voltage electrostatic protection components of integrated circuit of the circuit of the turn of miscellaneous _. 2. The process of printing the method of the present invention by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics includes the steps of: forming a P-type well area and an N-type well area on a semiconductor substrate using a lithography and ion implantation process, and then opening > Insulation isolation is formed; the design of the photomask is changed in the formation of the N-type well region, and an N-type well is also formed in the drain region of the N-type metal-oxide-semiconductor field-effect transistor to form an N-type well. Area. Next, an N-type metal-oxide-semiconductor field-effect transistor structure is formed, which includes a gate dielectric layer, a gate conductive layer, an N-type doped drain electrode, and a lightly doped source / drain region. , A dielectric bulkhead, a source, and two separate poles. Finally, a p-type heavily doped region is formed between the two drain electrodes. In the high-voltage electrostatic protection element formed by the present invention, a PNp bipolar junction transistor is formed by a P-type heavily doped region, an N-type well region, and a P-type well region; in addition, the N-type well region and the p-type well Area, and source to form a bipolar junction transistor with fsiPfs. This PNP and NPN form a so-called Silicon Controlled Rectifier (SCR). When the paper ruler ^ left home (CNS) A4 Naka mm) 437〇4 9 A7 ------- '_____ V. Description of the invention (+) NIVIOS's drain endures an external high voltage When static, the base of the pnp bipolar junction transistor is driven by the collector of the NPN bipolar junction transistor, or the base of the NPN bipolar junction transistor is driven by the collector of the pNp bipolar junction transistor. The drive thus drives the silicon controlled rectifier (SCR) to conduct and cause a snapback effect, and locks the electrostatic discharge surge (esD Pulse) at a very low voltage. This allows external electrostatic charges to pass through the silicon The control rectifier (SCR) is discharged, so that the internal components of the integrated circuit can be protected from being damaged by high voltage static electricity. It is particularly important that the operating voltage of the silicon controlled rectifier (SCR) of the high-voltage electrostatic protection element formed by the method of the present invention can be reduced to below 2 volts. Therefore, when the drain of the nmOS is subjected to external high static electricity, the heat generated is much lower than that of the conventional electrostatic protection element. The high-voltage electrostatic protection element formed by the method of the present invention can withstand high-voltage static electricity of up to 8000 volts or more without being burnt by high heat, and can achieve the effect of protecting internal elements. Brief description of the drawings: FIG. 1 is a schematic cross-sectional view of forming an electrostatic protection element in the conventional technology. FIG. 2 is a schematic cross-sectional view of the present invention in which a P-type well region and an N-type well region are formed on a semiconductor substrate, and then insulation isolation is formed. Fig. 3 is a schematic cross-sectional view showing the formation of a metal-oxide half field-effect transistor structure in the present invention. FIG. 4 is a schematic cross-sectional view of forming a P-type heavily doped region in the present invention. Fig. 5 is an equivalent circuit diagram of the high-voltage electrostatic protection element formed in the present invention. 43 7 ϋ 4 9 V. Description of the invention (/ Drawing number description: 10-Semiconductor substrate 12-Gate dielectric layer 14-Source and electrode area 16-Dielectric barrier wall 20-P-well area 30-Insulation isolation 41-Gate dielectric layer 43-N-type doped deep drain 45-Dielectric barrier 47-Way 11-N-type gold-oxygen half field effect transistor 13-Gate conductive layer 15-Lightly doped source / Non-polar region 17-N-type doped region 21-N-type well region 40-Gold-oxygen half field effect transistor structure 42-Gate conductive layer 44-Lightly doped source /: and region 46-Source 50-P type Densely doped region The present invention discloses a method and structure for forming a Korean electrostatic protection element in an integrated circuit. The high calendar electrostatic protection element formed by the present invention is an intermetallic field-effect transistor (QS), which can Turn to the dynamic random access memory, static random access memory, and any circuit products. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 2. First, the conventional standard lithography and ion implantation process is used to form a p-type well area 20 and an N-type well area 21 on a semiconductor substrate 10, and then Insulation isolation 30 is formed by a conventional technique, and an active device region is thus defined. The insulation isolation 30 may be a conventional regional silicon oxide layer (LOCOS) or a shallow trench isolation (SOS). Its function is to isolate the active device area. The N-type well region 21 is located in the region where the drain electrode of nmOS is to be formed. The paper size is suitable for the application of the national standard (CNS) A4 g ^ f ^ $ 7 i ^ I y 4 3 7 u 4 9 A7 ----- B7 ---; ----- --- V. Description of the invention (A) Wei 'is one of the key points of the present invention. In a conventional process, an N-type well area is used to form a PMOS and a P-type well area is used to form an NMOS. However, the present invention changes the design of the photomask, and ion implantation of the N-type well region is also performed in a part of the NIVJOS drain region of the electrostatic protection element to form an N-type well region 21. The N-type well region 21 is formed by ion implantation with arsenic or phosphorus ions having an energy between 70 and 140 KeV, and its doping concentration is between 1E12 and 5E13 atoms / cm 2. Next, referring to FIG. 3, a conventional metal-oxide-semiconductor field-effect transistor structure 40 is formed by using a conventional process technology. The metal-oxygen half-effect transistor structure 40 includes a gate dielectric layer (Gate Die 丨 ectr 丨 c) 41, a gate Electrode conductive layer 42, N-type Deep Drain (hereinafter referred to as NDD) 43, lightly doped drain / source; and Lightly Doped Drain / Source (hereinafter referred to as LDD) 44. A dielectric spacer (| nsL1iator Spacer) 45 and a source / drain 46. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the gate dielectric layer 41 is formed by a thermal oxidation method and has a thickness of 30 to 80 A. Before or after the gate dielectric layer 41 is formed, an ion implantation process with an initial voltage adjustment may be added. The gate conductive layer 42 is formed by a low pressure chemical vapor deposition (Pressure Chemical Vapor Deposition; hereinafter referred to as LPCVD) to form a polycrystalline silicon layer with a thickness between 800 and 4000A. There are two methods for doping the polycrystalline silicon layer, one of which is doping arsenic or phosphorus into the reaction gas Silane to deposit arsenic or phosphorus and silicon simultaneously; the other method is to deposit an essentially complex The crystalline silicon layer is doped with arsenic or phosphorus by the ion implantation technique. Utilizing traditional lithography and anisotropic reactive ion etching techniques Paper size-China National Standard (CNS) A4 $ 格 ⑽x 2 如 公 6
* 4 3 7 ϋ 4 9 五、發明說明（/ 術，以Cb為反應氣體來蝕刻所述複晶砍層，以形成閘極 $構。接著以氧氣f漿灰化法和濕式去緣法剝除掉用以 定義閘極結構的光阻。❹卜，若欲得到電阻較低的閉極導 電層42 ’亦可在所述複晶石夕層上沉積一層石夕化金屬層。接 下來在預備形成汲極的區域形成一 N型摻雜深汲極 (NDD)43 〇形成所述N型摻雜深汲極(NDD)43，係以能量 介於50至150 KeV的砷或磷離子進行離子佈植所形成， 其摻雜濃度係介於1E12到5E14原子/平方公分之間。接 下來在主動元件區形成淡摻雜源極/汲極區44。所述淡摻 雜源極/没極區44，係以能量介於20至80 KeV的砷或碟 離子進行離子佈植所形成’其摻雜濃度介於1E12到5E13 原子/平方公分之間。接著在所述閘極結構的側壁形成介電 質間隙壁45。所述介電質間隙壁45的製程，是先用 LPCVD或是PECVD技術形成一層厚度介於1〇〇〇至 3000人的氧化矽層或氮化矽層’再以cf4做為反應氣體藉 由非等向反應性離子蝕刻法進行回蝕刻而成。接下來在主 動元件區形成源極/汲極。所述形成源極/汲極，係先利用 傳統的微影技術定義出預備形成源極和汲極的區域，再以 能量介於30至100 KeV的砷或磷離子進行離子佈植所形 成’其摻雜濃度介於1E14到5E16原子/平方公分之間。 本發明的重點在於，所形成的源極46和習知技術相同， 但所形成的没極47則和習知技術有很大的差異。請參考 圖一，習知技術中的汲極係以單一的N型濃摻雜所構成。 然而本發明在設計及佈局時便已將汲極區域放大，藉著特 $"纸張尺度用中國國家標準（CNS)A4規格（210 X 2备公釐） f請先閱讀背面之注意事項再填寫本頁；> 裝-----^ —丄訂---------今 經濟部智慧財產局員工消費合作社印製 A7 437U 4 9 五、發明說明（f 殊之光罩的佈局’利用微影及離子佈植技術形成兩個分離 的汲極47，如圖三所示。 接下來凊參考圖四，為本發明之另一重點所在，以p 型半導體物質進行靜電保護離子佈植，在所述兩個没極47 之間形成P型濃摻雜區50, 51。形成所述p型濃摻雜區 50, 51，係以能量介於50至12〇 KeV的硼或三氟化硼離 子進行離子佈植所形成，其摻雜濃度介於1E14到5E16 原子/平方公分之間。本發明所述在積體電路中形成高壓靜 電保護元件的方法及其結構於焉完成。 由圖四和圖一的比較可以得知，本發明所形成之高壓 靜電保護元件和習知技術所形成之元件最大的不同點在 於，本發明較習知技術多了所述(\|型井區21和P型濃摻 雜區50，因此在由汲極至源極的通路上形成p型/ n型/ p 型/ N型的結構，因而形成—個矽控制整流器（Sj|ic〇n* 4 3 7 ϋ 4 9 V. Description of the invention (/ technique, Cb is used as a reactive gas to etch the polycrystalline cutting layer to form a gate structure. Then, an oxygen f slurry ashing method and a wet demargination method are used. The photoresist used to define the gate structure is stripped off. That is, if a closed-electrode conductive layer 42 'with lower resistance is to be obtained, a petrified metal layer may be deposited on the polycrystalline stone layer. Next An N-type doped deep drain (NDD) 43 is formed in the region where the drain is to be formed. The N-type doped deep drain (NDD) 43 is formed with arsenic or phosphorus ions having an energy between 50 and 150 KeV. Formed by ion implantation, the doping concentration is between 1E12 and 5E14 atoms / cm 2. Next, a lightly doped source / drain region 44 is formed in the active device region. The lightly doped source / The non-polar region 44 is formed by ion implantation with arsenic or disk ions having an energy between 20 and 80 KeV, and its doping concentration is between 1E12 and 5E13 atoms / cm 2. Then in the gate structure, A dielectric gap wall 45 is formed on the sidewall. The dielectric gap wall 45 is manufactured by using a LPCVD or PECVD technique to form a layer having a thickness between 1 and 1 Å. The silicon oxide layer or silicon nitride layer of 〇00 to 3,000 people is then etched back using cf4 as a reactive gas by anisotropic reactive ion etching. Next, a source / drain is formed in the active device region. The formation of the source / drain is formed by using conventional lithography techniques to define the area where the source and drain are to be formed, and then implanting the ions with arsenic or phosphorus ions with an energy between 30 and 100 KeV. 'The doping concentration is between 1E14 and 5E16 atoms / cm 2. The main point of the present invention is that the formed source 46 is the same as the conventional technique, but the formed non-electrode 47 is very different from the conventional technique. Please refer to Figure 1. The drain in the conventional technology is composed of a single N-type doping. However, in the design and layout of the present invention, the drain region has been enlarged. With special paper The Zhang scale uses the Chinese National Standard (CNS) A4 specification (210 X 2 mm). F Please read the precautions on the back before filling in this page; > Loading ----- ^ — 丄 定 ------ --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 437U 4 9 V. Invention Description (f special The layout of the cover 'uses lithography and ion implantation technology to form two separate drain electrodes 47, as shown in Figure 3. Next, referring to Figure 4, this is another important point of the present invention, which uses p-type semiconductor materials to perform static electricity. Protective ion implantation forms P-type heavily doped regions 50, 51 between the two immortal electrodes 47. The p-type heavily doped regions 50, 51 are formed with an energy between 50 and 120 KeV. Boron or boron trifluoride ion formed by ion implantation, and its doping concentration is between 1E14 and 5E16 atoms / cm 2. The method for forming a high-voltage electrostatic protection element in an integrated circuit and the structure thereof are described in the present invention.焉 Done. It can be seen from the comparison between FIG. 4 and FIG. 1 that the biggest difference between the high-voltage electrostatic protection element formed by the present invention and the element formed by the conventional technique is that the present invention has more described (\ | type wells) than the conventional technique. Region 21 and P-type heavily doped region 50, so a p-type / n-type / p-type / N-type structure is formed on the path from the drain to the source, thus forming a silicon controlled rectifier (Sj | ic〇n
Controled Rectifier; SCR)。 接下來請參考圖五，為本發明所形成之高壓靜電保護 元件的等效電路圖。由圖五中可得知，由P型濃掺雜區 50、N型井區21、和P型井區20形成一個PNP的雙極 接面電晶體；另外由N型井區21、P型井區20、和源極 46形成一個NPN的雙極接面電晶體^當所述NM〇s的汲 極承受一外來的高壓靜電時’ PNP雙極接面電晶體的基極 被NPN雙極接面電晶體的集極所驅動，或者npn雙極接 面電晶體的基極被PNP雙極接面電晶體的集極所驅動， 因而就驅動矽控制整流器（SCR)導通而產生彈回效應 知紙張尺度適用中國國家標準（CNS)A4規格（210 χ 2的公釐 (請先閱讀背面之注意事項再填寫本頁) ctj 裝 ii—.I.---^訂---------竣 經濟部智慧財產局員工消費合作社印製 < ' 43 7U 4 9 A7 * —-------- B7 五、發明説明（7 ) ' :-- (Snapback)而把靜電放電突波(ESD pu|se)鎖在很低的電 壓’延樣可以將外來的靜電電荷藉由所述雜制整流器 (SCR)排掉’如此便可保護親之㈣元件不會被高 壓靜電所破壞。 知'別重要的是，利用本發明所述方法形成的高壓靜電 保護元件，頻制整流器(SCR)的工作電壓相當低，可以 ?低5巧特以下。因此當所述_QS驗極承受外來的 兩壓靜電時’所產生的熱量會比習用的靜電保護元件低很 多:利用本發明所述方法形成的高壓靜魏護々件可以承 受高達_伏特以上的高壓靜電，而不會因高熱而燒 毁，可以達到保護内部元件的功效。 另外，在本發明中之N型摻雜深汲極43的離子佈植 和淡摻雜源/汲極區44的離子佈植之順序可對調，可以達 到二相同的效果。在另—方面，在本發明中之源極，没極 46的離子佈植和p型濃摻雜區5〇的離子佈植之順序亦可 對調’可以達到完全相同的效果。 以上所述係利用較佳實施例詳細說明本發明，而非限 制本發明的範圍，而，且熟知此技藝的人士亦能明瞭，適當 而作些微的改變與調整，仍將不失本發明之要義所在，亦 不脫離本發明之精神和範圍。 (請先間讀背面之注意事項再填寫本頁) τ，1Τ 經濟部智慧財產局員工消費合作社印製 本紙崎適用中ΐΐϋ5τ^)·Α4— (210X297公釐）Controled Rectifier; SCR). Please refer to FIG. 5 for an equivalent circuit diagram of the high-voltage electrostatic protection element formed by the present invention. It can be known from FIG. 5 that a PNP bipolar junction transistor is formed by the P-type heavily doped region 50, the N-type well region 21, and the P-type well region 20; in addition, the N-type well region 21 and the P-type The well area 20 and the source electrode 46 form an NPN bipolar junction transistor. ^ When the drain of the NMOs is subjected to an external high-voltage static electricity, the base of the PNP bipolar junction transistor is NPN bipolar. Driven by the collector of the junction transistor, or the base of the npn bipolar junction transistor is driven by the collector of the PNP bipolar junction transistor, thus driving the silicon controlled rectifier (SCR) to conduct and cause a springback effect The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 χ 2 mm (please read the precautions on the back before filling this page) ctj equipment ii—.I .--- ^ order ------ --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs < '43 7U 4 9 A7 * ---------- B7 V. Description of Invention (7)':-(Snapback) The discharge surge (ESD pu | se) is locked at a very low voltage. The “extended sample can discharge the external electrostatic charge through the hybrid rectifier (SCR).” This protects the pro-components from high-voltage static electricity. It is important to know that the high-voltage electrostatic protection element formed by the method of the present invention has a relatively low operating voltage of the frequency-controlled rectifier (SCR), which can be as low as 5 or less. Therefore, when the _QS test pole When subjected to external two-voltage static electricity, the heat generated will be much lower than that of conventional electrostatic protection components: the high-voltage static Weiwei protection piece formed by the method of the present invention can withstand high-voltage static electricity of more than _ volts, without Burning under high heat can achieve the effect of protecting internal components. In addition, the order of ion implantation of N-type doped deep drain 43 and ion implantation of lightly doped source / drain region 44 in the present invention can be reversed. The same effect can be achieved. In another aspect, in the present invention, the order of the ion implantation of the source electrode 46 and the ion implantation of the p-type heavily doped region 50 can also be reversed. The above is a detailed description of the present invention using the preferred embodiments, rather than limiting the scope of the present invention, and those skilled in the art will also understand that slight changes and adjustments will be made appropriately and will not change. Lose money The essence of the invention does not depart from the spirit and scope of the invention. (Please read the notes on the back before filling out this page.) Τ, 1Τ Printed on this paper by the Intellectual Property Bureau of the Intellectual Property Bureau of the Ministry of Economic Affairs. Applicable paper 纸 5τ ^) · Α4— (210X297 mm)