JPH0230180B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field) The present invention relates to semiconductor devices, and in particular to semiconductor devices having a multilayer wiring structure, particularly semiconductor integrated circuit devices, in which wiring patterns are devised to prevent short circuits in upper layer wiring. Concerning shape.

(Prior Art) In semiconductor integrated circuits, as the degree of integration increases, it has become inevitable to adopt a multilayer wiring structure.
Although the multilayer wiring structure has the major advantages of simplification of design due to the increased topological freedom of wiring and reduction of chip area due to the reduction of the wiring area, the upper layer wiring is arranged across large steps of the lower layer wiring. In particular, when an upper layer wiring runs in parallel with a step of a lower wiring with a narrow wiring interval, there is a problem of short circuit between the upper layer wiring in the step. That is, in recent wiring forming processes, anisotropic dry etching has become mainstream for etching metal for wiring because it is necessary to form fine wiring with high accuracy. this,
In anisotropic dry etching, etching progresses anisotropically, so etching follows the resist pattern. However, if there is a steep step, the effective metal film thickness at the step becomes thicker. Etching residue is likely to occur on stepped portions. As the spacing between the upper layer wirings becomes narrower, the possibility of short-circuiting of the upper layer wirings due to this phenomenon becomes higher.

(Object of the Invention) An object of the present invention is to provide an effective semiconductor device that eliminates the drawbacks of the prior art.

(Structure of the Invention) In order to reduce the possibility of a short circuit between the upper layer wirings at the stepped portion of the lower layer wiring, the present invention provides two opposing sides of the upper layer wiring passing in parallel to the stepped portion of the lower layer wiring at the stepped portion. The purpose is to prevent short circuits between upper layer wirings by moving them relatively backward to widen the interval.

(Description of Examples) In FIG. 1, a first wiring layer 3 is formed on a silicon oxide film 2 formed on the surface of a silicon substrate 1.
This is a cross-sectional structure in which an insulator 4 is provided on the insulator 4 and covered with an insulator 4. The step difference in the first wiring layer 3 is directly reflected on the insulator 4, and a step 5 is also formed in the insulator. After the wiring metal is deposited on the insulator in this state, ordinary resist coating and alignment exposure are performed to form a resist pattern for the second layer of wiring on the wiring metal. When anisotropic dry etching is performed under such conditions, the etching regresses with anisotropy in the direction perpendicular to the silicon wafer, which tends to leave etching residue on the stepped portions, causing short circuits in the second layer wiring. It becomes easier to wake up.

FIG. 2 is a plan view showing the prior art, and is a plan view at the time when etching of the second wiring layer is completed. Two second wiring layers 7 run in parallel across the first wiring layer 3. 8-11
is the remainder of the second layer wiring metal at the step portion of the first layer wiring, that is, at the step portion of the insulator 4 above it. 8, 10, and 11 may cause a short circuit between the second wiring layers, and the remaining metal at 9 completely causes a short circuit between the second wiring layers. Short circuits between wires due to metal residue at the stepped portions rapidly increase as the wire spacing becomes narrower, causing a decrease in the yield of good chips.

In order to reduce the possibility of short-circuiting between upper layer wirings at a stepped portion of lower layer wiring, the present invention aims to connect two opposing sides of a plurality of upper layer interconnects that are perpendicular to the lower layer wiring and run parallel to the stepped portion of the lower layer wiring. The purpose is to rectify the gap at the stepped portion to widen the interval, thereby reducing the possibility of short circuit between the upper layer wirings.

FIG. 3 shows an embodiment of the present invention, and is a plan view at the time when etching of the second wiring layer with the second layer pattern is completed. The second layer straddles the first wiring layer 3 and passes through the insulator (Fig. 1).
A plurality of wiring layers 13 run in parallel. 1
Reference numerals 4 to 17 indicate pattern portions in which two opposing sides of the second wiring layer are set back at step portions of the first wiring layer. As a result, the interval between the second wiring layers at the stepped portion is increased, and the possibility of a short circuit between the second wiring layers due to metal residue at the stepped portion is reduced.
The recessed portion of the second wiring pattern at the stepped portion may be provided on two opposing sides, or may be provided on only one side.

If the wiring pattern structure of the present invention is adopted,
In semiconductor integrated circuits, where the degree of integration is increasing,
The stability of wiring formation is increased, and the yield of non-defective products can be improved.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a state in which the first layer of wiring is formed, FIG. 2 is a plan view showing a conventional technique, and FIG. 3 is a plan view showing an embodiment of the present invention. In addition, in the figure, 1... silicon semiconductor substrate,
2... Insulating film such as silicon dioxide film, 3... First wiring layer which is lower layer wiring, 4... Interlayer insulating layer such as CVD silicon dioxide, 5... Step, 7,
13...Second wiring layer which is upper layer wiring, 1
4, 15, 16, 17... Planar patterns of recesses according to the present invention.

Claims (1)

[Claims] 1. In a plurality of upper layer wirings arranged perpendicularly to the lower layer wirings on one or more lower layer wirings arranged in a semiconductor device having a multilayer wiring structure, the upper layer wirings passing through the stepped portions of the lower layer wirings face each other. A semiconductor device characterized in that two sides of the upper layer wiring are relatively set back at the step portion, and the spacing between the upper layer wirings at the step portion is expanded compared to the spacing at other portions including above the center portion of the lower layer wiring. .