JPS60176251A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a short circuit between upper layer wirings by relatively retreating the opposite two sides of the upper layer wirings at a stepped section and expanding a clearance in a semiconductor device having multilayer wiring structure. CONSTITUTION:A plurality of second layer wiring layers 13 run parallel through an inter-layer insulator 4 while crossing first layer wiring layers 3. Spaces among the second layer wiring layers at the stepped sections of the first layer wiring layers 3 are expanded by pattern sections 14-17 where two opposite sides of the second layer wiring layers are retreated at the stepped sections, and the possibility of short circuits among the second layer wiring layers due to the remaining of a metal at the stepped sections is reduced.

Description

Detailed Description of the Invention (Technical Field) The present invention provides protection for semiconductor devices, particularly semiconductor devices having a multilayer wiring structure, particularly semiconductor integrated circuit devices, by devising the wiring pattern to prevent short circuits in upper layer wiring. Regarding the wiring shape.

(Prior Art) In semiconductor integrated circuits, as the degree of integration increases, it is inevitable to adopt a multilayer wiring structure.

Although the multilayer wiring structure has the major advantages of facilitating design by increasing the topological freedom of wiring and reducing the chip area by reducing the wiring area, it is because the upper layer wiring is arranged across large steps of the lower layer wiring. In particular, when upper layer wirings walk parallel to each other with narrow wiring intervals in step i of the lower wiring, there is a problem of short-circuiting between the upper layer wirings at the step portion. That is, in recent wiring forming processes, anisotropic dry etching has become mainstream for etching metal for wiring because it is necessary to form fine wiring with high precision. In this anisotropic dry etching, etching progresses anisotropically, so
Although etching is performed through the resist pattern, if there is a steep step, the effective metal film thickness at the step increases, and etching residue is likely to occur at the step. As the spacing between the upper layer wirings becomes narrower, the possibility of a short circuit between the upper layer wirings due to this phenomenon becomes higher.

(Object of the Invention) An object of the present invention is to provide an effective semiconductor device that eliminates the drawbacks of the prior art.

(Structure of the Invention) In order to reduce the possibility of a short circuit between the upper layer wirings at the stepped portion of the lower layer wiring, the present invention provides two opposing sides of the upper layer wiring passing in parallel to the stepped portion of the lower layer wiring at the stepped portion. The purpose is to prevent short circuits between upper layer wirings by moving them relatively backward to widen the interval.

(Explanation of Embodiment) In FIG. 1, a first wiring layer 3 is disposed on a silicon oxide film 2 formed on the surface of a silicon substrate 1, and an insulating material 4 is covered thereon. It has a cross-sectional structure. The step difference in the first wiring layer 3 is directly reflected on the insulator 4, and a step 5 is also formed in the insulator. After the wiring metal is deposited on the insulator in such a state, ordinary resist coating and eyelid exposure are performed to form the rinse strips of the second layer of wiring on the wiring metal. If anisotropic dry etching is performed in such a state, the etching regresses with anisotropy in the direction perpendicular to the silicon wafer, which tends to leave etching residue on the stepped portions and short circuits in the second layer wiring. Become.

FIG. 2 is a plan view showing the prior art, and is a plan view at the time when etching of the second wiring layer is completed. 1st
Two second wiring layers 7 run in parallel across the second wiring layer 3. Reference numerals 8 to 11 indicate the residue of the second layer wiring metal at the step portion of the first layer wiring, that is, at the step portion of the insulator 4 thereon. Nos. 8, 10, and 11 may cause a short circuit between the second wiring layers, and the metal crosspiece 9 completely causes a short circuit between the second wiring layers. Such short circuits between wires due to the metal crosspiece at the stepped portion increase rapidly as the wire spacing becomes narrower, causing a decrease in the yield of non-defective chips.

In order to reduce the possibility of short-circuiting between upper layer wirings at a stepped portion of lower layer wiring, the present invention aims to connect two opposing sides of a plurality of upper layer interconnects that are perpendicular to the lower layer wiring and run parallel to the stepped portion of the lower layer wiring. The purpose is to rectify the gap at the stepped portion to widen the interval, thereby reducing the possibility of short circuit between the upper layer wirings.

FIG. 3 shows an embodiment of the present invention, and is a plan view at the time when etching of the second wiring layer with the second layer pattern is completed. A plurality of second wiring layers 13 run in parallel across the first wiring layer 3 via an interlayer insulator (FIG. 1).

Reference numerals 14 to 17 indicate pattern portions in which two opposing sides of the second wiring layer are set back at step portions of the first wiring layer. As a result, the interval between the 2Nth wiring layers at the stepped portion is increased, and the possibility of a short circuit between the second wiring layers due to the metal crosspiece at the stepped portion is reduced.

The four portions of the second layer wiring pattern at the stepped portion may be provided on two opposing sides, or may be provided only on the - side.

By employing the wiring pattern structure of the present invention,4 the stability of forming one wiring can be increased and the yield of good products can be improved in semiconductor integrated circuits whose degree of integration is increasing.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing the state in which the first layer of wiring has been formed! Figure 2 is a plan view showing the prior art.
The figure is a plan view showing an embodiment of the present invention. In addition, in the figure, 1... silicon semiconductor substrate,
2... Insulating film such as silicon dioxide film, 3...
...The 211th wiring layer, which is the lower layer wiring, 4...
・・C0■ Interlayer insulating layer such as silicon dioxide, 5...
...Level difference, 7°13...Second wiring layer, which is upper layer wiring, 14.15, 16.17...
It is a plane pattern of a recessed part according to the present invention.

Claims (1)

[Claims] In a plurality of upper layer wirings which are perpendicular to one or more lower layer wirings disposed in a semiconductor device having a multilayer wiring structure and are perpendicular to the lower layer wirings, the upper layer wirings passing through the stepped portions of the lower layer wirings face each other. 2'lL is relatively set back at the stepped portion, and the upper layer wiring spacing at the stepped portion is expanded compared to the spacing at other portions.