JPS6325951A - Semiconductor device - Google Patents

Abstract

PURPOSE:To weaken the stress of a sealing resin and to obtaine a semiconductor device characterized by less short circuits between interconnections and wire breakdown and high reliability, by providing pseudo interconnections having a double-layer structure at least at the corner part of a semiconductor chip. CONSTITUTION:Pseudo interconnections 3A and 5A having a double-layer sturcutre are provided at least at a corner part 9 of a semiconductor chip. For example, a first aluminum interconnection 3 is provided on an insulating film 2 comprising SiO2 and the like, which is formed on a semiconductor substrate 1. A second aluminum interconnection 5 is formed through an interlayer insulating film 4. The first pseudoaluminum interconnection 3A and the second pseudo aluminum interconnection 5A are formed in a network pattern in approximately parallel with a scribing line 8 at the corner part 9 of the semiconductor chip. When resin sealing of the device formed in this way is performed after the assembling processes, the irregular parts formed by the pseudo aluminum interconnections 3A and 5A weaken the stress in the sealing resin at the corner part 9. Therefore, the stress applied to the first and second aluminum interconnections 3 and 5 becomes less. Thus the short circuits between the aluminum interconnections and wire breakdown in the aluminum interconnections become less.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a resin-sealed multilayer wiring structure.

[Conventional technology]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In recent years, in order to reduce the size and cost of semiconductor chips, many semiconductor devices having multilayer wiring structures sealed with resin have been manufactured.The structure of a conventional zero-order semiconductor device will be described with reference to the drawings.

FIGS. 4(a) to 4(c) are a plan view of a portion of a semiconductor device having a conventional two-layer wiring structure, a sectional view taken along the line DD, and a sectional view taken along the line EE'.

4(a) to (C), an insulating film 2 is provided on a semiconductor substrate 1, a first aluminum wiring 3 as a lower layer wiring is provided on this insulating film 2, and then an interlayer insulating film 4 is provided, A second aluminum wiring 5 is provided thereon as an upper layer wiring, and a silicon oxide film 6 grown in a vapor phase and a silicon nitride film 7 formed by a plasma CVD method are laminated as a cover film. 8 is a scribe line of the semiconductor chip.

The semiconductor device having the two-layer wiring structure constructed in this manner is completed by being sealed with resin through an assembly process.

[Problem that the invention seeks to solve]

As shown in FIGS. 4(a) to 4(c), the semiconductor device having the above-mentioned conventional resin-sealed multilayer wiring structure has a region where the first aluminum wiring 3 and the second aluminum wiring 5 intersect. This occurs, and especially the second aluminum wiring 5 in that area is formed into a convex shape. Therefore, when a semiconductor device is sealed with resin and subjected to a temperature cycle test, stress is applied to the second aluminum wiring 5 due to the sealing resin having a large coefficient of thermal expansion.

Particularly near the corners of the semiconductor device, the stress generated between the semiconductor device and the sealing resin is stronger than the stress in the central region of the semiconductor device.
There is a problem that cracks and cracks are likely to occur, and a short circuit failure between the first aluminum wiring 3 and the second aluminum wiring 5 or a disconnection failure of the second aluminum wiring 5 occurs, resulting in a decrease in reliability.

An object of the present invention is to provide a highly reliable semiconductor device.

[Means for solving problems]

The semiconductor device of the present invention has a two-layer structure of pseudo interconnects provided at least at the corner portions of a semiconductor chip.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A-A' of a first embodiment of the present invention.

In FIGS. 1(a) and 1(b), on an insulating film 2 formed on a semiconductor substrate 1 and made of S, O2, etc., a first aluminum wiring 3 and a second aluminum wiring 3 are connected via an interlayer insulating film 4. A first pseudo-aluminum interconnect 3A and a second pseudo-aluminum interconnect 5A are formed substantially parallel to the scribe line 8 in the corner portion 9 of the semiconductor chip.
are formed in a mesh shape. Note that 6 is a silicon oxide film and 7 is a silicon nitride film.

When the first embodiment configured in this way is resin-sealed through an assembly process, the uneven portions formed by the first and second pseudo-aluminum wirings 3A and 5A will cause the sealing resin to form at the corner portions 9. Since the stress is weakened, the stress applied to the first and second aluminum interconnections 3.5 is reduced. Therefore, short circuits between aluminum wirings and disconnections of aluminum wirings are extremely rare.

FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along the line BB' of a second embodiment of the present invention.

In this second embodiment, since the first pseudo aluminum wiring 3A provided in the corner portion 9 is formed to have a wide width, displacement of the pseudo wiring itself due to stress caused by the sealing resin is reduced.

FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along line cc' of a third embodiment of the present invention.

In this third embodiment, the first pseudo aluminum wiring 3A reaches the semiconductor substrate 1 through the opening 10A provided in the insulating film 2, and the second pseudo aluminum wiring 5A also extends through the interlayer insulating film 4. It is connected to the first pseudo aluminum wiring 3A through an opening 10B provided in the. The first and second pseudo-aluminum wirings 3A, 5A configured in this manner become stronger and can suppress stress in the sealing resin.

In the above embodiment, a case of a two-layer structure having first and second aluminum wirings has been described, but it is of course possible to have a structure of three or more layers.

〔Effect of the invention〕

As explained above, the present invention can weaken the stress of the sealing resin by providing two-layered pseudo wires at least in the corners of the semiconductor chip, thereby increasing reliability with fewer short circuits and disconnections between wires. A high quality semiconductor device can be obtained.

[Brief explanation of drawings]

1(a), (b) to 3(a), (b) are plan views and sectional views of the first to third embodiments of the present invention, and FIG.
), (b), and (c) are a plan view and a cross-sectional view of a semiconductor device having a conventional two-layer wiring structure. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... First aluminum wiring, 3A... First pseudo aluminum wiring, 4... Interlayer insulating film, 5... Second aluminum wiring , 5A... second pseudo aluminum wiring, 6...
Silicon oxide film, 7... Silicon nitride film, 8... Scribe line, 9... Corner part, IOA, IOB...
・Open hole. Agent Patent Attorney Susumu Uchihara 7':", 1.,":
:-Kureigyu l Figure 2 Figure 4

Claims (1)

[Claims] A semiconductor device characterized in that a two-layer pseudo wiring is provided in at least a corner portion of a semiconductor chip.