JP2004119415A

JP2004119415A - Resin sealed semiconductor device and process for producing resin sealed semiconductor

Info

Publication number: JP2004119415A
Application number: JP2002276798A
Authority: JP
Inventors: Makoto Okawa; 大川　誠
Original assignee: Denso Corp
Current assignee: Denso Corp
Priority date: 2002-09-24
Filing date: 2002-09-24
Publication date: 2004-04-15
Anticipated expiration: 2022-09-24
Also published as: JP3941645B2

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a resin sealed semiconductor device having a multilayer wiring structure in which a passivation film is protected against cracking due to a thermal stress being applied from resin to the surface of a semiconductor chip by temperature cycle. <P>SOLUTION: Lead-out wiring is provided using lower layer wiring 103 and 106 excepting uppermost layer wiring 107 in the electrode wiring having a multilayer wiring structure of a resin sealed semiconductor becoming a major cause of cracking a passivation film 108 in order to minimize level difference incident to the uppermost layer wiring. Furthermore, cracking of the passivation film 108 is minimized at the corner of the electrode wiring by directing the lead-out wiring in the electrode wiring reversely to the direction of a closest corner or/and edge on the periphery of a semiconductor chip in order to minimize the effect of a shear stress acting from the periphery toward the center of the semiconductor chip. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に関し、特に樹脂封止型半導体装置及び樹脂封止型半導体製造方法に関する。
【０００２】
【従来の技術】
樹脂封止型半導体装置のパッシベーション膜は、半導体素子の表面での機械的な保護及び吸湿などによる素子劣化の防止並びに各半導体素子間での絶縁の確保などの機能を持ち、半導体素子の機能信頼性を確保する上で、極めて重要な役割を果たしている。このパッシベーション膜にクラックが発生すると、吸湿による特性劣化やクラックの進行による電極断線に至ることもあり、半導体装置の機能が喪失することになる。
【０００３】
そのため、従来はある特許公報（特許文献１）に記載のように、幅広の配線にスリットやホールを設けて実質的に配線の幅を狭くすることにより、配線による発熱を減少する方法でパッシベーション膜にクラックが発生するのを回避する方法が取られていた。
【０００４】
また、このような対策が取れない電極配線部については、２つの特許文献（特許文献２、特許文献３）に記載のように、配線パターンとパッシベーション膜との接触部である配線パターンのコーナの形状を鈍角又は円弧状にすることで内部応力のコーナへの集中を緩和する方法などが取られていた。
【０００５】
近年、電極配線の多層化が進み、かつパワーＩＣなどの電極配線の厚膜化が進んだ結果、電極に幅広配線を適用した半導体チップでは、モールド材で封止した後の温度負荷サイクル試験などで、電極配線上や電極配線のコーナなどのパッシベーション膜にクラックが発生するという問題が起きた。パッシベーション膜のクラックがチップの外周部付近に集中して発生していることから、これらのパッシベーション膜におけるクラックの発生の主原因としては、半導体チップへの外部からの温度変化に起因して発生する封止樹脂からの熱応力が考えられる。
【０００６】
他の特許公報（特許文献４）では、半導体チップへの外部からの温度変化に起因して発生する熱応力の問題に対応する方法としてパッシベーション膜の膜厚を電極配線の膜厚及び電極配線幅から算出した所定の膜厚とする方法について記載しているが、応力に対する強さは各層膜を形成する素材により異なるため、各層膜の形成に所定の素材を用いた場合についてのみ有効な方法である。
【０００７】
【特許文献１】
特開昭５７−４５２５９号公報
【特許文献２】
特開昭６１−２５５０３９号公報
【特許文献３】
特開平５−２１８０２１号公報
【特許文献４】
特許第２９９０３２２号公報
【０００８】
上記したように、半導体チップへの外部からの温度変化に起因して発生する熱応力によるパッシベーション膜でのクラック発生防止方法にはパッシベーション膜の膜厚と配線の幅を調整する方法や、コーナー部の形状による応力集中を緩和する方法が知られているが、電極配線部では防止効果が十分ではなかった。
【０００９】
【発明が解決しようとする課題】
本発明は、上記問題点に鑑み行われたもので、パッシベーション膜でのクラックの発生原因である段差部に発生する応力の発生原因に焦点を絞り込んで調査研究した結果、多層配線構造の場合には、半導体チップへの外部からの温度変化に起因して発生する封止樹脂の熱応力によって最上層の配線上部に発生する剪断応力が、最上層配線に起因する段差部への応力集中を引き起こすことが主たる原因であることがわかった。
【００１０】
これは、従来技術では電極パッドからの電極配線内の引出配線は主として最上層の電極配線を使用して行っていたり（図２参照）、電極パッドからの電極配線内の引出配線の引出方向も任意の方向で行われていた（図６参照）場合に、最上層配線に起因する段差部にクラックが集中しやすいことからも言えることである。
【００１１】
したがって、本発明の課題は上記主要原因に対応した汎用的、かつ効果的な解決方法を備えた樹脂封止型半導体装置及び樹脂封止型半導体製造方法を提供することである。
【００１２】
【課題を解決するための手段】
前記課題を解決した本発明は、パッシベーション膜のクラック発生の主要な原因となる樹脂封止型半導体での多層配線構造の電極配線内の最上層電極配線を使用した電極配線を最小限にすること及び半導体チップ周辺のコーナ方向から中央に向かって働く剪断応力の影響を最小限にするために電極配線の引出配線の方向を半導体チップ周辺の最も近接するコーナ方向又は及びエッジ方向と反対方向に電極配線内の引出配線を設置する樹脂封止型半導体装置及び樹脂封止型半導体製造方法を提供するものである。
【００１３】
請求項に記載の発明によれば、以下の効果がある。
半導体チップが多層配線構造の場合には、最上層より下層の配線で引出部を形成することにより、封止樹脂の熱応力によって剪断応力が最上層の配線上部に発生することを効果的に防止することができ、その結果、パッシベーション膜でのクラック発生を防止する効果がある。
【００１４】
また、半導体チップ周辺のコーナへの内部剪断応力の集中による影響を最小限にするために電極配線内の引出配線の方向を半導体チップ周辺の最も近接するコーナの方向と反対方向とすることで、電極配線のコーナなどにおけるパッシベーション膜のクラック発生を防止する効果がある。
【００１５】
さらに、半導体チップ周辺のコーナへの内部剪断応力の集中による影響を最小限にするために半導体チップ周辺のコーナ及び半導体チップ周辺のエッジから所定範囲に位置する全ての引出配線の引出方向を最も近接する半導体チップ周辺のコーナ方向又は／及びエッジ方向と反対方向とすることで、パッシベーション膜のクラック発生を防止する効果がある。
【００１６】
【発明の実施の形態】
本発明の好ましい実施の形態について、図を用いて詳細に説明する。
以下に図１及び図３並びに図４及び図５を参照して、本発明の樹脂封止型半導体製造方法の実施の形態における各ステップについて説明する。
図１に示す本発明の樹脂封止型半導体装置の製造方法は、半導体基板形成ステップ、絶縁膜形成ステップ、電極配線形成ステップ、パッシベーション膜形成ステップ、下層電極配線形成ステップ、引出配線形成ステップ、電極配線変更ステップ及び効果領域引出配線形成ステップから構成する。
【００１７】
半導体基板形成ステップは、Ｓｉ（シリコン）で半導体装置の半導体素子群を含む半導体基板１０１を形成するステップである。
絶縁膜形成ステップは、半導体素子群を含む半導体基板１０１上にプラズマＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　　Ｄｅｐｏｓｉｔｉｏｎ）で形成されたシリコン酸化などの絶縁膜１０２、塗布形成されたシリコン酸化膜（いわゆるＳＯＧ膜）の層間絶縁膜ａ１０４及びプラズマＣＶＤ酸化シリコン膜などでの層間絶縁膜ｂ１０５を形成するステップである。なお、符号ａ、ｂは２つの層間絶縁膜の下層側と上層側をそれぞれ示すものである。
【００１８】
電極配線形成ステップは、通常のフォトエッチングで層間絶縁膜ａ１０４及び層間絶縁膜ｂ１０５を除去して、多層配線構造の電極配線が繋がっている電極パッド１０９から多層配線構造の電極配線を形成するステップである。例えば３層配線構造の電極配線では、電極パッド１０９からの電極配線内に３層構造の配線、すなわち第１層配線（１ｓｔＡＬ）１０３、第２層配線（２ｎｄＡＬ）１０６、第３層配線（３ｒｄＡＬ）１０７を形成する。
【００１９】
パッシベーション膜形成ステップは、半導体装置の半導体素子を保護するために電極パッド１０９、層間絶縁膜ａ１０４及び層間絶縁膜ｂ１０５の上部にパッシベーション膜１０８を形成するステップである。パッシベーション膜１０８は膜厚が１．０μｍ〜２．０μｍであり、プラズマＣＶＤで形成したシリコン窒化膜で構成される。
【００２０】
下層電極配線形成ステップは、例えば３層配線構造では電極配線内の配線（１ｓｔＡＬ１０３、２ｎｄＡＬ１０６、３ｒｄＡＬ１０７）の最上層配線２０２（３ｒｄＡＬ１０７）を除いた下層配線２０１（２ｎｄＡＬ１０６及び／又は１ｓｔＡＬ１０３）を用いて半導体基板１０１上の半導体素子と電極パッド１０９又は／及び半導体素子間を配線するように半導体基板１０１上に電極配線をレイアウトして配線するステップである。
【００２１】
引出配線形成ステップは、電極配線内の引出配線Ａ２１０の引出方向を最も近接する半導体チップ周辺上のコーナ５０１の方向又は／及び最も近接する半導体チップ周辺のエッジ５０２の方向と反対の方向に配線し、その引出配線Ａ２１０で半導体基板１０１上の半導体素子と電極パッド１０９間又は／及び半導体素子間を配線するように半導体基板１０１上に引出配線Ａ２１０を配線レイアウトして配線を行うステップである（図５参照）。
【００２２】
電極配線変更ステップは、電極配線内の最上層配線２０２で電極パッド１０９と半導体基板１０１上の半導体素子間を結ぶ場合（図４参照）、いったん、電極配線内の下層配線２０１で配線を行いビアホール４０１で最上層配線２０２に接続するためにビアホール４０１を含んだ形で半導体素子と電極パッド１０９間又は／及び半導体素子間を配線するように半導体チップ上にビアホール４０１を含む形で電極配線をレイアウト変更して配線を行うステップである。
【００２３】
効果領域引出配線形成ステップは、半導体チップ周辺のコーナ５０１から少なくとも４００μｍ以内又は／及び半導体チップ周辺のエッジ５０２から少なくとも２００μｍ以内に位置する全ての電極配線内の引出配線Ａ２１０に対して、その引出方向を最も近接する半導体チップ周辺のコーナ５０１の方向又は／及び最も近接する半導体チップ周辺のエッジ５０２の方向と反対方向とすることを含んだ形で半導体素子と電極パッド１０９間又は／及び半導体素子間を配線するように半導体基板１０１上に引出配線Ａ２１０をレイアウトして配線を行うステップである。
【００２４】
上記製造方法により製造された本発明にかかる樹脂封止型半導体装置の実施の形態の構造についてさらに詳細に説明する。図１に示す本発明の樹脂封止型半導体装置の半導体チップ例は、半導体基板１０１、絶縁膜１０２、層間絶縁膜ａ１０４、層間絶縁膜ｂ１０５、電極パッド１０９、３層配線構造の電極配線内の配線（１ｓｔＡＬ１０３、２ｎｄＡＬ１０６、３ｒｄＡＬ１０７）及びパッシベーション膜１０８から構成されている。電極パッド１０９にはワイヤボンディング部１１０が設けられている。なお、図１（ｂ）では、ワイヤボンディング部１１０の接続ワイヤは図示省略している。
【００２５】
半導体素子群を含む半導体基板１０１上にプラズマＣＶＤで形成されたシリコン酸化などの絶縁膜１０２が設けられ、この上に塗布形成されたシリコン酸化膜（いわゆるＳＯＧ膜）の層間絶縁膜ａ１０４及びプラズマＣＶＤ酸化シリコン膜などの層間絶縁膜ｂ１０５で３層配線構造の電極配線内の配線（１ｓｔＡＬ１０３、２ｎｄＡＬ１０６、３ｒｄＡＬ１０７）の各々の引出配線層間の層間絶縁膜ａ１０４（膜厚０．８μｍ）及び層間絶縁膜ｂ１０５（膜厚０．８μｍ）が形成されている。
【００２６】
３層配線構造の電極配線内の配線（１ｓｔＡＬ１０３、２ｎｄＡＬ１０６、３ｒｄＡＬ１０７）には、Ａｌ（アルミニウム）に１％のＳｉ（シリコン）、０．５％のＣｕ（銅）を含有する材料の合金を用いる。また、各層の配線層厚は、１ｓｔＡＬ１０３／２ｎｄＡＬ１０６／３ｒｄＡＬ１０７＝０．６μｍ／０．９μｍ／１．３３μｍである。
【００２７】
電極パッド１０９は、通常のフォトエッチングで層間絶縁膜ａ１０４及び層間絶縁膜ｂ１０５を除去して、各層の電極配線が繋がっている。パッシベーション膜１０８は、電極配線、層間絶縁膜ａ１０４及び層間絶縁膜ｂ１０５の上部に半導体装置の半導体チップを保護するために形成されている。また、パッシベーション膜１０８は、プラズマＣＶＤで形成されたシリコン窒化膜で構成されており、その膜厚は１．０μｍ〜２．０μｍである。
【００２８】
次に、半導体チップサイズ６×３ｍｍの外周部付近（半導体チップのエッジから２００μｍ以内）に、１３０μｍ×１３０μｍの電極パッド１０９を２５個形成したテストサンプルを作成しエポキシ樹脂系のモールド樹脂を用いてモールド形成したサンプルを用いて、本発明の効果の確認を行った。
【００２９】
その方法は、発明の効果を比較するために電極パッド１０９からの電極配線内の引出配線Ｄ２４０を最上層配線２０２である３ｒｄＡＬ１０７を用いて配線したものと３ｒｄＡＬ１０７を除いた下層配線２０１（１ｓｔＡＬ１０３又は２ｎｄＡＬ１０６）から選定した下層配線２０１で配線したものを−６５゜Ｃと１５０゜Ｃの温度の液相に各々５分ずつ浸漬する温度サイクル試験を５００サイクル行った後で、パッシベーション膜１０８のクラック発生状況を調べて比較する方法で行った。
【００３０】
その結果、引出配線Ｄ２４０を最上層配線２０２である３ｒｄＡＬ１０７を用いて配線したものは、２台評価して合計８カ所（１６％＝８カ所÷２台÷２５カ所）にパッシベーション層上クラックの発生が検出された。その内、半導体チップ周辺のコーナ５０１から４００μｍ以内に位置する５カ所の電極パッド１０９から７カ所のパッシベーションのクラックを検出した。これらの５カ所の電極パッド１０９でのクラック発生率は、７０％（＝７カ所÷２台÷５カ所）の高発生率を示した。
【００３１】
一方、電極配線内の引出配線Ａ２１０を最上層配線である３ｒｄＡＬ１０７を除いた下層配線２０１（１ｓｔＡＬ１０３、２ｎｄＡＬ１０６）から選定した下層配線２０１で配線したものは、６台評価してパッシベーション膜１０８のクラック発生はゼロであった。この結果、電極パッド１０９からの電極配線内の引出配線Ａ２１０を最上層配線２０２である３ｒｄＡＬ１０７を除いた下層配線２０１（１ｓｔＡＬ１０３及び２ｎｄＡＬ１０６）から選定した下層配線２０１で配線することが、「段差」によるパッシベーション膜１０８のクラック発生防止に有効であることが確認された。
【００３２】
次に半導体チップ周辺のコーナ５０１及びエッジ５０２からの距離と剪断応力との関係の解析シミュレーションの結果を示した図７について説明する。この結果は、温度差Δｔ＝２１５℃の条件で、三次元モデルによる有限要素法によって求めたものである。図７中、プロットしてあるのは、対角線上の剪断応力である。
【００３３】
その結果は、図７に示すように剪断応力は半導体チップ内の位置により大きく変化し、半導体チップの周辺コーナ５０１からの距離が４００μｍ以内及び半導体チップエッジ５０２からの距離が２００μｍ以内の範囲では、半導体チップの中央部から半導体チップ周辺のコーナ５０１に向かって発生する剪断応力の影響が強いことがわかった。
【００３４】
図８に示すように、チップ外周方向に引出配線を設けると、引出配線とパッドに加わる剪断応力によって、引出配線とパッドの接続部の凹部コーナにモーメントが働き凹部コーナに応力が集中し、クラックが発生しやすくなるが、反対方向に引き出すことで、これが防止できるものと考えられる。
【００３５】
また、その結果パッシベーション膜のクラックが発生しなくなることから、電極配線内の引出配線Ａ２１０を半導体チップ周辺の最も近接したコーナ５０１又は／及びエッジ５０２の方向と反対の方向に配備することがパッシベーション膜１０８でのクラックの発生防止に有効であると考えられる。
【００３６】
図５は、上記結果の実施例を示したものである。また、図６は従来行われていた電極配線内の引出配線Ｄ２４０の例であり、引出配線Ｄ２４０は任意の方向でレイアウトしていた。このため、引出配線Ｄ２４０は半導体チップ周辺のコーナ５０１の方向への配備も普通に行われていた。
【００３７】
以上によれば、本実施の形態において、次のような効果を得ることができる。
最上層より下層の配線で引出部を形成することにより、封止樹脂の熱応力によって剪断応力が最上層の配線上部に発生することを効果的に防止することができ、その結果、パッシベーション膜でのクラック発生を防止する効果がある。
【００３８】
また、半導体チップ周辺のコーナへの内部剪断応力の集中による影響を最小限にするために電極配線内の引出配線の方向を半導体チップ周辺の最も近接するコーナ又は／及びエッジの方向と反対方向とすることで、電極配線のコーナなどにおけるパッシベーション膜のクラック発生を防止する効果がある。
【００３９】
さらに、半導体チップ周辺のコーナへの内部剪断応力の集中による影響を最小限にするために半導体チップ周辺のコーナ及び半導体チップ周辺のエッジから所定範囲に位置する全ての引出配線の引出方向を最も近接する半導体チップ周辺のコーナ又は／及びエッジへの方向と反対方向とすることで、パッシベーション膜のクラック発生を防止する効果がある。
【図面の簡単な説明】
【図１】（ａ）は、本発明の樹脂封止型半導体装置の好ましい実施の形態の断面図、（ｂ）は、その平面図であり、（ａ）は、（ｂ）中の矢視断面を示している。
【図２】（ａ）は、従来の半導体装置の断面図、（ｂ）は、その平面図であり、（ａ）は、（ｂ）中の矢視断面を示している。
【図３】（ａ）は、本発明の樹脂封止型半導体装置の２層配線の実施の形態の断面図、（ｂ）は、その平面図であり、（ａ）は、（ｂ）中の矢視断面を示している。
【図４】（ａ）は、本発明の樹脂封止型半導体装置の製造方法の好ましい実施の形態の電極配線変更ステップにおける最上層の電極配線を用いて半導体チップ上の電極配線と半導体素子間を結ぶ様子を示す断面図、（ｂ）は、その平面図である。
【図５】引出配線形成ステップにおける電極配線内の引出配線の引出方向の例を示した半導体装置の平面図である。
【図６】従来行われていた電極配線内の引出配線の例を示した半導体装置の平面図である。
【図７】半導体チップ周辺のコーナ及びエッジからの距離と剪断応力との関係を解析シミュレーションした結果を示したグラフ図である。
【図８】チップ外周方向に引出配線を設けた場合の、凹部コーナへの応力集中の様子を示す模式図である。
【符号の説明】
１０１　半導体基板
１０２　絶縁膜
１０３　第１層配線（１ｓｔＡＬ）
１０４　層間絶縁膜ａ
１０５　層間絶縁膜ｂ
１０６　第２層配線（２ｎｄＡＬ）
１０７　第３層配線（３ｒｄＡＬ）
１０８　パッシベーション膜
１０９　電極パッド
１１０　ワイヤボンディング
２０１　下層配線
２０２　最上層配線
２１０　引出配線Ａ（下層電極配線使用）
２２０　引出配線Ｂ（２ｎｄＡＬ使用）
２３０　引出配線Ｃ（３ｒｄＡＬ使用）
２４０　引出配線Ｄ（最上層電極配線使用）
４０１　ビアホール
５０１　半導体チップ周辺のコーナ
５０２　半導体チップ周辺のエッジ
６０１　クラック[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a resin-sealed semiconductor device and a resin-sealed semiconductor manufacturing method.
[0002]
[Prior art]
The passivation film of the resin-encapsulated semiconductor device has functions such as mechanical protection on the surface of the semiconductor element, prevention of element deterioration due to moisture absorption, and insulation between the semiconductor elements, and the reliability of the semiconductor element. It plays a very important role in ensuring the quality. If a crack occurs in the passivation film, the characteristics may be degraded due to moisture absorption or the electrode may be disconnected due to the progress of the crack, and the function of the semiconductor device may be lost.
[0003]
Therefore, as described in a conventional patent publication (Patent Document 1), a passivation film is formed by reducing the heat generated by wiring by providing slits and holes in wide wiring to substantially reduce the width of the wiring. In order to avoid the occurrence of cracks, a method has been adopted.
[0004]
Further, as for the electrode wiring portion where such measures cannot be taken, as described in the two patent documents (Patent Documents 2 and 3), the corner of the wiring pattern which is the contact portion between the wiring pattern and the passivation film is used. A method of reducing the concentration of the internal stress at the corners by adopting an obtuse angle or an arc shape has been adopted.
[0005]
In recent years, as the number of electrode wiring layers has increased and the thickness of electrode wiring such as power ICs has increased, semiconductor chips using wide wiring for electrodes have been subjected to temperature load cycle tests after sealing with a mold material. As a result, there has been a problem that cracks occur in the passivation film on the electrode wiring and the corners of the electrode wiring. Since the cracks in the passivation film are concentrated near the outer periphery of the chip, the main cause of the cracks in these passivation films is caused by an external temperature change to the semiconductor chip. Thermal stress from the sealing resin is considered.
[0006]
In another patent publication (Patent Document 4), as a method for coping with the problem of thermal stress generated due to an external temperature change on a semiconductor chip, the thickness of a passivation film is set to the thickness of an electrode wiring and the width of an electrode wiring. It describes the method of making the predetermined film thickness calculated from, but since the strength against stress differs depending on the material forming each layer film, it is an effective method only when the predetermined material is used for forming each layer film. is there.
[0007]
[Patent Document 1]
JP-A-57-45259 [Patent Document 2]
Japanese Patent Application Laid-Open No. 61-255039 [Patent Document 3]
JP-A-5-218021 [Patent Document 4]
Japanese Patent No. 2990322
As described above, a method for preventing cracks in the passivation film due to thermal stress generated due to an external temperature change to the semiconductor chip includes a method of adjusting the thickness of the passivation film and the width of the wiring, and a method of controlling a corner portion. There is known a method of alleviating the stress concentration due to the above shape, but the effect of preventing the electrode wiring portion is not sufficient.
[0009]
[Problems to be solved by the invention]
The present invention has been made in view of the above-described problems, and as a result of conducting research by focusing on the cause of the stress generated in the step portion which is the cause of the crack in the passivation film, as a result, in the case of a multilayer wiring structure, In the above, the shear stress generated at the upper part of the uppermost wiring due to the thermal stress of the sealing resin generated due to an external temperature change to the semiconductor chip causes the concentration of stress on the step portion caused by the uppermost wiring Turned out to be the main cause.
[0010]
This is because, in the prior art, the lead wiring in the electrode wiring from the electrode pad is mainly performed by using the uppermost layer electrode wiring (see FIG. 2), and the leading direction of the lead wiring in the electrode wiring from the electrode pad is also changed. This can also be said from the fact that cracks are likely to concentrate on the step due to the uppermost layer wiring when the operation is performed in an arbitrary direction (see FIG. 6).
[0011]
Therefore, an object of the present invention is to provide a resin-sealed semiconductor device and a resin-sealed semiconductor manufacturing method provided with a versatile and effective solution to the above main causes.
[0012]
[Means for Solving the Problems]
The present invention that solves the above-mentioned problem minimizes electrode wiring using an uppermost layer electrode wiring in an electrode wiring of a multilayer wiring structure in a resin-encapsulated semiconductor, which is a main cause of generation of cracks in a passivation film. In order to minimize the influence of shear stress acting from the corner direction around the semiconductor chip toward the center, the direction of the lead wiring of the electrode wiring is set in the direction opposite to the nearest corner direction and / or the edge direction around the semiconductor chip. An object of the present invention is to provide a resin-encapsulated semiconductor device and a method for manufacturing a resin-encapsulated semiconductor in which a lead-out wiring in a wiring is provided.
[0013]
According to the invention described in the claims, the following effects are obtained.
When the semiconductor chip has a multi-layer wiring structure, by forming the extraction part with the wiring below the uppermost layer, it is possible to effectively prevent the shear stress from being generated above the uppermost wiring due to the thermal stress of the sealing resin As a result, there is an effect of preventing generation of cracks in the passivation film.
[0014]
Further, in order to minimize the influence of the concentration of internal shear stress on the corners around the semiconductor chip, the direction of the lead wiring in the electrode wiring is set to be opposite to the direction of the closest corner around the semiconductor chip, This has the effect of preventing the occurrence of cracks in the passivation film at the corners of the electrode wiring.
[0015]
Further, in order to minimize the influence of the concentration of internal shear stress on the corners around the semiconductor chip, the leading directions of all the lead wires located within a predetermined range from the corners around the semiconductor chip and the edges around the semiconductor chip are closest to each other. By making the direction opposite to the corner direction and / or the edge direction around the semiconductor chip to be formed, there is an effect of preventing generation of cracks in the passivation film.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Preferred embodiments of the present invention will be described in detail with reference to the drawings.
Each step in the embodiment of the resin-sealed semiconductor manufacturing method of the present invention will be described below with reference to FIGS. 1 and 3 and FIGS. 4 and 5.
The method for manufacturing a resin-encapsulated semiconductor device of the present invention shown in FIG. 1 includes a semiconductor substrate forming step, an insulating film forming step, an electrode wiring forming step, a passivation film forming step, a lower electrode wiring forming step, a lead wiring forming step, and an electrode. It comprises a wiring change step and an effect area extraction wiring formation step.
[0017]
The semiconductor substrate forming step is a step of forming a semiconductor substrate 101 including a semiconductor element group of a semiconductor device using Si (silicon).
In the insulating film forming step, the insulating film 102 such as silicon oxide formed by plasma CVD (Chemical Vapor Deposition) on the semiconductor substrate 101 including the semiconductor element group, and the interlayer insulating of the coated silicon oxide film (so-called SOG film) This is a step of forming a film a104 and an interlayer insulating film b105 of a plasma CVD silicon oxide film or the like. Symbols a and b indicate the lower layer side and the upper layer side of the two interlayer insulating films, respectively.
[0018]
The electrode wiring forming step is a step of removing the interlayer insulating film a104 and the interlayer insulating film b105 by ordinary photoetching and forming an electrode wiring of the multilayer wiring structure from the electrode pad 109 to which the electrode wiring of the multilayer wiring structure is connected. is there. For example, in the case of an electrode wiring having a three-layer wiring structure, wiring having a three-layer structure, that is, a first layer wiring (1stAL) 103, a second layer wiring (2ndAL) 106, and a third layer wiring (3rdAL) are provided in the electrode wiring from the electrode pad 109. ) 107 is formed.
[0019]
The passivation film forming step is a step of forming a passivation film 108 on the electrode pad 109, the interlayer insulating film a104, and the interlayer insulating film b105 in order to protect a semiconductor element of the semiconductor device. The passivation film 108 has a thickness of 1.0 μm to 2.0 μm and is made of a silicon nitride film formed by plasma CVD.
[0020]
In the lower-layer electrode wiring forming step, for example, in a three-layer wiring structure, a semiconductor is formed using the lower-layer wiring 201 (2ndAL106 and / or 1stAL103) except for the uppermost wiring 202 (3rdAL107) of the wiring (1stAL103, 2ndAL106, 3rdAL107) in the electrode wiring. This is a step of laying out and laying out electrode wiring on the semiconductor substrate 101 so as to connect between the semiconductor element on the substrate 101 and the electrode pad 109 or / and the semiconductor element.
[0021]
In the lead wiring forming step, the lead wiring A210 in the electrode wiring is drawn in the direction opposite to the direction of the corner 501 on the periphery of the nearest semiconductor chip or / and the direction of the edge 502 around the nearest semiconductor chip. This is a step of laying out and laying out the lead wiring A210 on the semiconductor substrate 101 such that the lead wiring A210 is connected between the semiconductor element on the semiconductor substrate 101 and the electrode pad 109 and / or between the semiconductor elements (FIG. 5).
[0022]
In the electrode wiring changing step, when the electrode pad 109 and the semiconductor element on the semiconductor substrate 101 are connected by the uppermost wiring 202 in the electrode wiring (see FIG. 4), the wiring is once performed by the lower wiring 201 in the electrode wiring and the via hole is formed. At 401, the electrode wiring is laid out on the semiconductor chip so as to include the via hole 401 so as to connect between the semiconductor element and the electrode pad 109 or / and between the semiconductor elements so as to connect to the uppermost layer wiring 202. This is the step of changing the wiring.
[0023]
The effect area lead-out wiring forming step is performed for the lead-out direction of the lead-out wiring A210 in all the electrode wirings located within at least 400 μm from the corner 501 around the semiconductor chip or / and at least 200 μm from the edge 502 around the semiconductor chip. Between the semiconductor element and the electrode pad 109 and / or between the semiconductor element and the direction including the direction of the corner 501 around the nearest semiconductor chip and / or the direction of the edge 502 around the nearest semiconductor chip. This is a step of laying out the lead-out wiring A210 on the semiconductor substrate 101 so that wiring is performed.
[0024]
The structure of the embodiment of the resin-sealed semiconductor device according to the present invention manufactured by the above manufacturing method will be described in more detail. The semiconductor chip example of the resin-encapsulated semiconductor device of the present invention shown in FIG. 1 includes a semiconductor substrate 101, an insulating film 102, an interlayer insulating film a104, an interlayer insulating film b105, an electrode pad 109, and a three-layer wiring structure in an electrode wiring. It is composed of wirings (1stAL103, 2ndAL106, 3rdAL107) and a passivation film 108. A wire bonding section 110 is provided on the electrode pad 109. In FIG. 1B, connection wires of the wire bonding unit 110 are not shown.
[0025]
An insulating film 102 of silicon oxide or the like formed by plasma CVD is provided on a semiconductor substrate 101 including a semiconductor element group, and an interlayer insulating film a104 of a silicon oxide film (so-called SOG film) applied thereon and plasma CVD. An interlayer insulating film b104 (with a thickness of 0.8 μm) and an interlayer insulating film b105 between the respective lead wiring layers (1stAL103, 2ndAL106, 3rdAL107) in the electrode wiring of the three-layer wiring structure with an interlayer insulating film b105 such as a silicon oxide film. (A film thickness of 0.8 μm).
[0026]
For the wiring (1stAL103, 2ndAL106, 3rdAL107) in the electrode wiring of the three-layer wiring structure, an alloy of a material containing Al (aluminum) containing 1% Si (silicon) and 0.5% Cu (copper) is used. . The wiring layer thickness of each layer is 1stAL103 / 2ndAL106 / 3rdAL107 = 0.6 μm / 0.9 μm / 1.33 μm.
[0027]
The electrode pad 109 is formed by removing the interlayer insulating film a104 and the interlayer insulating film b105 by ordinary photoetching, and the electrode wiring of each layer is connected. The passivation film 108 is formed on the electrode wiring, the interlayer insulating film a104 and the interlayer insulating film b105 to protect the semiconductor chip of the semiconductor device. The passivation film 108 is formed of a silicon nitride film formed by plasma CVD, and has a thickness of 1.0 μm to 2.0 μm.
[0028]
Next, a test sample in which 25 130 μm × 130 μm electrode pads 109 were formed near the outer periphery of the semiconductor chip having a size of 6 × 3 mm (within 200 μm from the edge of the semiconductor chip), and an epoxy resin-based mold resin was used. The effect of the present invention was confirmed using a sample formed with a mold.
[0029]
In order to compare the effects of the present invention, the method uses a method in which the lead wiring D240 in the electrode wiring from the electrode pad 109 is wired using the 3rdAL107, which is the uppermost layer wiring 202, and a lower layer wiring 201 (1stAL103 or 2ndAL106 excluding the 3rdAL107). ), 500 cycles of a temperature cycle test in which each of the lower wirings 201 selected from the above was immersed in a liquid phase at a temperature of -65 ° C. and 150 ° C. for 5 minutes each, and then the state of occurrence of cracks in the passivation film 108 Was performed by a method of checking and comparing.
[0030]
As a result, cracks on the passivation layer were generated in a total of eight places (16% = 8 places ÷ 2 places ÷ 25 places) when two outgoing wiring lines D240 were wired using the 3rdAL107, which is the uppermost layer wiring 202, were evaluated. Was detected. Of these, seven passivation cracks were detected from five electrode pads 109 located within 400 μm from the corner 501 around the semiconductor chip. The crack occurrence rate at these five electrode pads 109 was as high as 70% (= 7 places ÷ 2 units ÷ 5 places).
[0031]
On the other hand, when the lead wiring A210 in the electrode wiring is wired with the lower wiring 201 selected from the lower wiring 201 (1stAL103, 2ndAL106) excluding the 3rdAL107 which is the uppermost wiring, six passivation films 108 are cracked after evaluation. Was zero. As a result, wiring of the lead wiring A210 in the electrode wiring from the electrode pad 109 with the lower wiring 201 selected from the lower wiring 201 (1stAL103 and 2ndAL106) excluding the 3rdAL107 which is the uppermost wiring 202 is caused by the “step”. It was confirmed that the passivation film 108 was effective in preventing cracks.
[0032]
Next, FIG. 7 showing the result of an analysis simulation of the relationship between the distance from the corner 501 and the edge 502 around the semiconductor chip and the shear stress will be described. This result was obtained by a finite element method using a three-dimensional model under the condition of a temperature difference Δt = 215 ° C. In FIG. 7, what is plotted is the diagonal shear stress.
[0033]
As a result, as shown in FIG. 7, the shear stress greatly changes depending on the position in the semiconductor chip. When the distance from the peripheral corner 501 of the semiconductor chip is within 400 μm and the distance from the semiconductor chip edge 502 is within 200 μm, It was found that the influence of the shear stress generated from the center of the semiconductor chip toward the corner 501 around the semiconductor chip was strong.
[0034]
As shown in FIG. 8, when the lead wiring is provided in the chip outer peripheral direction, a moment acts on the concave corner of the connecting portion between the lead wiring and the pad due to the shear stress applied to the lead wiring and the pad, and the stress is concentrated on the concave corner and the crack is formed. It is thought that this can be prevented by pulling out in the opposite direction.
[0035]
Further, as a result, cracks in the passivation film do not occur, and therefore, it is necessary to dispose the lead wiring A210 in the electrode wiring in the direction opposite to the direction of the corner 501 and / or the edge 502 closest to the periphery of the semiconductor chip. This is considered to be effective in preventing the occurrence of cracks at 108.
[0036]
FIG. 5 shows an example of the above result. FIG. 6 shows an example of a lead wire D240 in a conventional electrode wire, and the lead wire D240 is laid out in an arbitrary direction. For this reason, the lead-out wiring D240 is normally provided in the direction of the corner 501 around the semiconductor chip.
[0037]
According to the above, the following effects can be obtained in the present embodiment.
By forming the lead portion with the wiring below the uppermost layer, it is possible to effectively prevent shear stress from being generated above the uppermost wiring due to the thermal stress of the sealing resin, and as a result, the passivation film Has the effect of preventing the occurrence of cracks.
[0038]
In addition, in order to minimize the influence of the concentration of internal shear stress on the corners around the semiconductor chip, the direction of the lead wiring in the electrode wiring is set to the direction opposite to the direction of the nearest corner or / and edge around the semiconductor chip. This has the effect of preventing cracks in the passivation film at corners of the electrode wiring.
[0039]
Further, in order to minimize the influence of the concentration of internal shear stress on the corners around the semiconductor chip, the leading directions of all the lead wires located within a predetermined range from the corners around the semiconductor chip and the edges around the semiconductor chip are closest to each other. The direction opposite to the corner and / or the edge around the semiconductor chip to be formed has an effect of preventing the generation of cracks in the passivation film.
[Brief description of the drawings]
1A is a cross-sectional view of a preferred embodiment of a resin-sealed semiconductor device of the present invention, FIG. 1B is a plan view thereof, and FIG. 1A is an arrow view in FIG. It shows a cross section.
2A is a cross-sectional view of a conventional semiconductor device, FIG. 2B is a plan view thereof, and FIG. 2A is a cross-sectional view of FIG.
FIG. 3A is a cross-sectional view of an embodiment of a two-layer wiring of a resin-sealed semiconductor device of the present invention, FIG. 3B is a plan view thereof, and FIG. Of FIG.
FIG. 4 (a) is a diagram showing a method for manufacturing a resin-sealed semiconductor device according to a preferred embodiment of the present invention; And (b) is a plan view thereof.
FIG. 5 is a plan view of the semiconductor device showing an example of a drawing direction of a drawing wiring in an electrode wiring in a drawing wiring forming step.
FIG. 6 is a plan view of a semiconductor device showing an example of a lead wiring in an electrode wiring, which has been conventionally performed.
FIG. 7 is a graph showing a result of analysis and simulation of a relationship between a distance from a corner and an edge around a semiconductor chip and a shear stress.
FIG. 8 is a schematic diagram showing a state of stress concentration on a concave corner when a lead wiring is provided in a chip outer peripheral direction.
[Explanation of symbols]
Reference Signs List 101 semiconductor substrate 102 insulating film 103 first layer wiring (1st AL)
104 interlayer insulating film a
105 interlayer insulating film b
106 Second layer wiring (2ndAL)
107 Third layer wiring (3rdAL)
108 Passivation film 109 Electrode pad 110 Wire bonding 201 Lower layer wiring 202 Top layer wiring 210 Leader wiring A (using lower layer electrode wiring)
220 Leader wiring B (using 2ndAL)
230 Leader wiring C (using 3rdAL)
240 Lead wire D (using top layer electrode wire)
401 Via hole 501 Corner around semiconductor chip 502 Edge 601 around semiconductor chip Crack

Claims

A semiconductor substrate including a semiconductor element group of a semiconductor chip;
An insulating film formed on the semiconductor substrate,
An electrode wiring formed in a multilayer wiring structure from an electrode pad provided on the insulating film,
A passivation film formed on the insulating film and the electrode wiring,
Lead wiring formed by creating a layout from wiring of a predetermined layer selected from the lower electrode wiring except the uppermost electrode wiring in the electrode wiring,
Resin-sealed semiconductor device having the same.

A semiconductor substrate including a semiconductor element group of a semiconductor chip;
An insulating film formed on the semiconductor substrate,
An electrode wiring formed in a multilayer wiring structure from an electrode pad provided on the insulating film,
A passivation film formed on the insulating film and the electrode wiring,
Creating and forming a layout of the extraction wiring in which the extraction direction of the extraction wiring in the electrode wiring is opposite to the direction of the corner around the closest semiconductor chip or / and the direction of the edge near the closest semiconductor chip. The drawn out wiring and
Resin-sealed semiconductor device having the same.

A semiconductor substrate including a semiconductor element group of a semiconductor chip;
An insulating film formed on the semiconductor substrate,
An electrode wiring formed in a multilayer wiring structure from an electrode pad provided on the insulating film,
A passivation film formed on the insulating film and the electrode wiring,
A lower wiring layer formed by selecting a predetermined wiring from a lower wiring layer excluding the uppermost wiring layer of the electrode wiring and creating a layout of the wiring wiring;
The lead wiring in the electrode wiring is arranged such that the lead direction is opposite to the direction of the corner around the closest semiconductor chip or / and the direction of the edge around the closest semiconductor chip. With the formed extraction wiring,
Resin-sealed semiconductor device having the same.

When connecting the electrode pad and the semiconductor element on the semiconductor substrate with the uppermost layer electrode wiring, once the predetermined extraction wiring is selected and wired from the lower layer electrode wiring excluding the uppermost layer electrode wiring, and then the via hole is used. An electrode wiring formed by changing the layout of the electrode wiring so as to be connected to the uppermost layer electrode wiring,
The resin-encapsulated semiconductor device according to claim 1, further comprising:

At least 400 μm from the corners around the semiconductor chip and / or at least 200 μm from the edges around the semiconductor chip. The resin sealing according to any one of claims 1 to 4, further comprising: a lead wiring formed by creating a layout of the lead wiring in a direction opposite to a direction of an edge around the adjacent semiconductor chip. Stop type semiconductor device.

A semiconductor substrate forming step for forming a semiconductor substrate including a semiconductor element group of a semiconductor chip;
An insulating film forming step for forming an insulating film on the semiconductor substrate,
An electrode wiring forming step for forming an electrode wiring of a multilayer wiring structure from electrode pads provided on the insulating film;
A passivation film forming step for forming a passivation film on the insulating film and the electrode wiring;
A lead wiring in the electrode wiring, a lower electrode wiring forming step for selecting a predetermined lead wiring from the lower electrode wiring except the uppermost electrode wiring in the electrode wiring and creating a layout of the lead wiring; ,
And a method for manufacturing a resin-sealed semiconductor.

A semiconductor substrate forming step for forming a semiconductor substrate including a semiconductor element group of a semiconductor chip;
An insulating film forming step for forming an insulating film on the semiconductor substrate,
An electrode wiring forming step for forming an electrode wiring of a multilayer wiring structure from electrode pads provided on the insulating film;
A passivation film forming step for forming a passivation film on the insulating film and the electrode wiring;
The layout of the lead-out wiring is created so that the lead-out direction of the lead-out wiring in the electrode wiring is opposite to the direction of the corner around the closest semiconductor chip or / and the direction of the edge near the closest semiconductor chip. A lead wiring forming step,
And a method for manufacturing a resin-sealed semiconductor.

A semiconductor substrate forming step for forming a semiconductor substrate including a semiconductor element group of a semiconductor chip;
An insulating film forming step for forming an insulating film on the semiconductor substrate,
An electrode wiring forming step for forming an electrode wiring of a multilayer wiring structure from electrode pads provided on the insulating film;
A passivation film forming step for forming a passivation film on the insulating film and the electrode wiring;
A lead wiring in the electrode wiring, a lower electrode wiring forming step for selecting a predetermined lead wiring from a lower electrode wiring except for the uppermost electrode wiring of the electrode wiring and creating a layout of the lead wiring,
In order to create a layout of the lead-out wiring, the lead-out wiring in the electrode wiring has a lead-out direction opposite to a direction of a corner around the nearest semiconductor chip or / and a direction of an edge around the nearest semiconductor chip. And a lead wiring forming step of
And a method for manufacturing a resin-sealed semiconductor.

When connecting the electrode pad and the semiconductor element on the semiconductor substrate with the uppermost layer electrode wiring, once the predetermined extraction wiring is selected and wired from within the lower layer electrode wiring excluding the uppermost layer electrode wiring, and then the via hole is used. 9. The method for manufacturing a resin-encapsulated semiconductor according to claim 6, further comprising: an electrode wiring changing step of changing a layout of the electrode wiring so as to connect to the uppermost layer electrode wiring. .

At least 400 μm from the corners around the semiconductor chip and / or at least 200 μm from the edges around the semiconductor chip. 10. The method according to claim 6, further comprising: forming an effect area lead-out wiring for creating a layout of the lead-out wiring in a direction opposite to a direction of an edge around the adjacent semiconductor chip. 11. A resin-encapsulated semiconductor manufacturing method.