KR100709443B1 - Method for forming bonding pad of semiconductor device - Google Patents

Method for forming bonding pad of semiconductor device Download PDF

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KR100709443B1
KR100709443B1 KR1020060008273A KR20060008273A KR100709443B1 KR 100709443 B1 KR100709443 B1 KR 100709443B1 KR 1020060008273 A KR1020060008273 A KR 1020060008273A KR 20060008273 A KR20060008273 A KR 20060008273A KR 100709443 B1 KR100709443 B1 KR 100709443B1
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metal wiring
forming
bonding pad
upper metal
semiconductor device
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KR1020060008273A
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Korean (ko)
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윤훈상
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 소자의 본딩 패드 형성방법에 관한 것으로, 본딩 압력을 분산시키기 위해, 하부 금속배선을 상부 금속배선과 중첩되지 않도록 상부 금속배선의 최외곽 라인에서 일정간격 이격시켜 형성하고, 본딩 패드가 형성되는 영역에 슬릿 형태의 다수개의 더미 하부 금속배선을 형성하고, 칩을 보호하기 위한 PIQ층을 상부 금속 배선과 중첩되도록 형성하여 본딩 압력에 의한 스트레스를 완화시킬 수 있는 기술이다.The present invention relates to a method for forming a bonding pad of a semiconductor device. In order to disperse the bonding pressure, the lower metal wiring is formed to be spaced apart from the outermost line of the upper metal wiring so as not to overlap with the upper metal wiring, and the bonding pad is formed. A plurality of dummy lower metal wires having a slit shape are formed in a region to be formed, and a PIQ layer for protecting a chip is formed to overlap with the upper metal wires to reduce stress caused by bonding pressure.

본딩 패드, PIQ Bonding pads, PIQ

Description

반도체 소자의 본딩 패드 형성방법{METHOD FOR FORMING BONDING PAD OF SEMICONDUCTOR DEVICE}Bonding pad formation method of semiconductor device {METHOD FOR FORMING BONDING PAD OF SEMICONDUCTOR DEVICE}

도 1은 종래기술에 따른 반도체 소자의 본딩 패드 형성방법을 도시한 단면도.1 is a cross-sectional view showing a bonding pad forming method of a semiconductor device according to the prior art.

도 2는 종래기술에 따른 반도체 소자의 본딩 패드 형성방법에 따른 문제점을 설명하기 위한 사진도.Figure 2 is a photograph for explaining a problem according to the bonding pad forming method of a semiconductor device according to the prior art.

도 3은 본 발명에 따른 반도체 소자의 본딩 패드 형성방법을 도시한 단면도.3 is a cross-sectional view showing a bonding pad forming method of a semiconductor device according to the present invention;

본 발명은 반도체 소자의 본딩 패드 형성방법에 관한 것으로, 특히 본딩 압력을 분산시킬 수 있는 반도체 소자의 본딩 패드 형성방법에 관한 기술이다.The present invention relates to a method for forming a bonding pad of a semiconductor device, and more particularly, to a method for forming a bonding pad of a semiconductor device capable of dispersing a bonding pressure.

일반적으로, 반도체 소자의 도전층은 금속층과 절연층의 적층으로 형성되고, 서로 상하위 도전층을 접속시키는 공정으로 제조된다. 반도체 소자의 미세화, 고집적화에 따라 서로 적층되는 도전층의 수가 증가하게 되며, 요구되는 도전층의 수만큼 절연층과 도전층을 적층하고 패터닝하는 공정들을 진행하게 된다. 이러한 공정들의 마지막 단계로서 리드 프레임과 접속되는 본딩 패드(bonding pad)를 형성한 다. Generally, the conductive layer of a semiconductor element is formed by lamination | stacking of a metal layer and an insulating layer, and is manufactured by the process of connecting upper and lower conductive layers mutually. As the semiconductor devices become more compact and have higher integration, the number of conductive layers stacked on each other increases, and processes for stacking and patterning insulating layers and conductive layers as many as the required number of conductive layers are performed. As a final step of these processes, a bonding pad is formed in contact with the lead frame.

도 1은 종래기술에 따른 반도체 소자의 본딩 패드 형성방법을 도시한 단면도이다.1 is a cross-sectional view illustrating a bonding pad forming method of a semiconductor device according to the prior art.

도 1을 참조하면, 하부 구조물(미도시)이 형성된 반도체 기판(11) 상부에 본딩 패드용 하부 금속배선(13)을 형성한다. 그 다음, 상기 하부 금속배선(13) 사이를 매립하도록 제 1 층간절연막(15)을 전면에 형성하고, 상기 제 1 층간절연막(15) 상부에 상기 하부 금속배선(13)을 보호하기 위한 제 1 보호막(passivation)(17)을 형성한다. 이때, 상기 제 1 보호막(17)에 단차가 발생된다.Referring to FIG. 1, a lower metal wiring 13 for a bonding pad is formed on a semiconductor substrate 11 on which a lower structure (not shown) is formed. Next, a first interlayer insulating film 15 is formed on the entire surface of the first interlayer insulating film 15 so as to fill the gap between the lower metal wirings 13, and a first layer for protecting the lower metal wiring 13 on the first interlayer insulating film 15. A passivation 17 is formed. At this time, a step is generated in the first passivation layer 17.

그 다음, 상기 제 1 보호막(17) 상에 본딩 패드용 상부 금속배선(19)을 형성하고, 상기 상부 금속배선(19) 사이를 매립하도록 제 2 층간절연막(미도시)을 형성한다. Next, an upper metal wiring 19 for bonding pads is formed on the first passivation layer 17, and a second interlayer insulating film (not shown) is formed to fill the gaps between the upper metal wirings 19.

그 다음, 상기 제 2 층간절연막 상부에 상기 상부 금속배선(19)을 보호하기 위한 제 2 보호막(21)을 형성한 후, 본딩 패드가 형성되는 영역에 해당되는 상기 제 2 보호막(21) 및 상기 제 1 보호막(17)을 식각하여 상기 상부 금속배선(19)을 오픈(open)시켜 본딩패드를 형성한다. Next, after forming a second passivation layer 21 for protecting the upper metal interconnection 19 on the second interlayer insulating layer, the second passivation layer 21 and the corresponding portion where a bonding pad is formed. The first passivation layer 17 is etched to open the upper metal wiring 19 to form a bonding pad.

그 다음, 상기 제 2 보호막(21) 상부에 칩(chip)을 보호하기 위한 PIQ(Polymide Isoindro Quirazorindione)층(23)을 형성한다. Next, a PIQ (Polymide Isoindro Quirazorindione) layer 23 is formed on the second passivation layer 21 to protect the chip.

도 2는 종래기술에 따른 반도체 소자의 본딩 패드 형성방법에 따른 문제점을 설명하기 위한 사진도이다.2 is a photograph for explaining a problem according to a bonding pad forming method of a semiconductor device according to the prior art.

도 2를 참조하면, 패드에 와이어(wire)를 본딩할 때 인가되는 본딩 압력에 의해 상기 상부 금속배선(19)이 밀리게 된다. 이에 따라, 상기 상부 금속배선(19)의 에지부 아래에 있는 상기 하부 금속배선(13)이 어택(attack)을 받게 되어 크랙(crack)(A)이 유발되고, 주변 패턴간에 쇼트(short)(B)가 발생되는 문제점이 있다. Referring to FIG. 2, the upper metal wiring 19 is pushed back by the bonding pressure applied when the wire is bonded to the pad. Accordingly, the lower metal wiring 13 under the edge of the upper metal wiring 19 is attacked to cause a crack A, and a short between the peripheral patterns ( There is a problem that occurs B).

본 발명은 상기와 같은 문제점을 해결하기 위하여 창출된 것으로, 패드에 와이어(wire)를 본딩할 때 인가되는 본딩 압력에 의한 상부 금속배선의 스트레스를 완화시키고, 하부 금속배선에서 발생되는 크랙(crack) 및 주변 패턴간에 발생되는 쇼트(short)를 방지할 수 있는 반도체 소자의 본딩 패드 형성방법을 제공하는데 그 목적이 있다. The present invention has been made to solve the above problems, to reduce the stress of the upper metal wiring due to the bonding pressure applied when bonding the wire (wire) to the pad, the crack (cracks) generated in the lower metal wiring And a method for forming a bonding pad of a semiconductor device capable of preventing shorts occurring between peripheral patterns.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 본딩 패드 형성방법은, 하부 구조물이 형성된 반도체 기판 상부에 하부 금속배선을 형성하는 동시에, 본딩 패드가 형성되는 영역에 슬릿 형태를 갖는 다수개의 더미 하부 금속배선을 형성하는 단계; 하부 금속배선 및 더미 하부 금속배선 전면에 제 1 보호막을 형성하는 단계; 제 1 보호막 상에 상부 금속배선을 형성하는 단계; 상부 금속배선 전면에 제 2 층간절연막 및 제 2 보호막을 순차적으로 형성하는 단계; 본딩 패드가 형성되는 영역의 제 2 보호막 및 제 2 층간절연막을 식각하여 상부 금속 배선을 오픈시키는 단계; 및 상부 금속배선과 소정간격 중첩되도록 제 2 보호막 상부에 PIQ층을 형성하는 단계를 포함하는 것을 특징으로 한다.Bonding pad forming method of a semiconductor device of the present invention for achieving the above object, a plurality of dummy lower metal having a slit shape in the region where the bonding pad is formed, while forming a lower metal wiring on the semiconductor substrate on which the lower structure is formed. Forming a wiring; Forming a first passivation layer on the lower metal wiring and the dummy lower metal wiring; Forming an upper metal wiring on the first passivation layer; Sequentially forming a second interlayer insulating film and a second passivation film on the entire upper metal wiring; Etching the second passivation layer and the second interlayer insulating layer in the region where the bonding pad is formed to open the upper metal wiring; And forming a PIQ layer on the second passivation layer so as to overlap the upper metal wiring with a predetermined interval.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하도 록 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 3은 본 발명에 따른 반도체 소자의 본딩 패드 형성방법을 도시한 단면도이다.3 is a cross-sectional view illustrating a method of forming a bonding pad of a semiconductor device according to the present invention.

도 3을 참조하면, 하부 구조물(미도시)이 형성된 반도체 기판(111) 상부에 하부 금속배선(113)을 형성하는 동시에, 본딩 패드가 형성되는 영역에 슬릿 형태의 다수개의 더미 하부금속층(115)을 형성한다. Referring to FIG. 3, the lower metal wiring 113 is formed on the semiconductor substrate 111 on which the lower structure (not shown) is formed, and a plurality of dummy lower metal layers 115 having a slit shape are formed in a region where the bonding pad is formed. To form.

이때, 상기 하부 금속배선(113)은 이후에 형성되는 상부 금속배선의 일측단과 중첩되지 않도록 상기 상부 금속배선의 최외곽 라인에서 일정간격 이격시켜 형성하는 것이 바람직하다.In this case, the lower metal wiring 113 is preferably formed to be spaced apart from the outermost line of the upper metal wiring so as not to overlap with one end of the upper metal wiring formed later.

그 다음, 상기 하부 금속배선(113) 및 상기 더미 하부 금속배선(115) 사이를 매립하도록 제 1 층간절연막(117)을 전면에 형성하고, 상기 제 1 층간절연막(117) 상부에 상기 하부 금속배선(113)을 보호하기 위한 제 1 보호막(passivation)(119)을 형성한다. 이때, 상기 제 1 보호막(119)에 하부 구조물에 의한 단차가 발생된다.Next, a first interlayer insulating film 117 is formed on the entire surface to fill the gap between the lower metal wiring 113 and the dummy lower metal wiring 115, and the lower metal wiring on the first interlayer insulating film 117. A first passivation 119 is formed to protect 113. In this case, a step caused by a lower structure is generated in the first passivation layer 119.

그 다음, 상기 제 1 보호막(119) 상에 상부 금속배선(121)을 형성하고, 상기 상부 금속배선(121)을 덮는 제 2 층간절연막(123)을 형성한다.Next, an upper metal wiring 121 is formed on the first passivation layer 119, and a second interlayer insulating film 123 is formed to cover the upper metal wiring 121.

그 다음, 상기 제 2 층간절연막(123) 상부에 상기 상부 금속배선(121)을 보호하기 위한 제 2 보호막(125)을 형성한 후, 본딩 패드 영역에 해당되는 상기 제 2 보호막(125) 및 상기 제 2 층간절연막(123)을 식각하여 상기 상부 금속배선(121)을 오픈(open)시켜 본딩패드를 형성한다. Next, after forming the second passivation layer 125 for protecting the upper metal wiring 121 on the second interlayer insulating layer 123, the second passivation layer 125 and the bonding pad region. The second interlayer insulating layer 123 is etched to open the upper metal wiring 121 to form a bonding pad.

그 다음, 상기 제 2 보호막(125) 상부에 칩을 보호하기 위한 PIQ층(127)을 형성한다.Next, a PIQ layer 127 is formed on the second passivation layer 125 to protect the chip.

이때, 상기 PIQ층(127)은 상기 상부 금속배선(121)과 중첩(overlap)되도록 형성하되, 본딩 패드 영역은 확보할 수 있는 만큼만 중첩시켜 형성하는 것이 바람직하다.In this case, the PIQ layer 127 may be formed to overlap the upper metal wiring 121, but the bonding pad region may be formed to overlap only as much as possible.

상술한 바와 같이, 본 발명에 따른 반도체 소자의 본딩패드 형성방법은, 패드에 와이어(wire)를 본딩할 때 인가되는 본딩 압력에 의해 상기 상부 금속배선(121)이 밀리는 경우에도 상기 하부 금속배선(113)이 상기 상부 금속배선(121)과 중첩되지 않기 때문에 쇼트(short) 현상이 방지될 수 있다. 그리고, 본딩 패드가 형성되는 영역에 슬릿 형태의 다수개의 더미 하부 금속배선(115)을 형성함으로써 본딩 압력이 분산될 수 있다. 또한, 상기 PIQ층(127)을 상기 상부 금속배선(121)과 중첩(overlap)되도록 형성함으로써 상기 상부 금속배선(121)의 에지부에 본딩 압력이 직접적으로 가해지는 것을 방지할 수 있다. As described above, in the method of forming a bonding pad of the semiconductor device according to the present invention, even when the upper metal wiring 121 is pushed by a bonding pressure applied when bonding a wire to the pad, the lower metal wiring ( Since the 113 does not overlap the upper metal wiring 121, a short phenomenon can be prevented. In addition, the bonding pressure may be dispersed by forming a plurality of dummy lower metal interconnections 115 having a slit shape in a region where the bonding pad is formed. In addition, by forming the PIQ layer 127 so as to overlap the upper metal wiring 121, a bonding pressure may be directly prevented from being applied to an edge portion of the upper metal wiring 121.

이상에서 살펴본 바와 같이, 본 발명의 반도체 소자의 본딩 패드 형성방법은 다음과 같은 효과를 제공한다.As described above, the bonding pad forming method of the semiconductor device of the present invention provides the following effects.

첫째, 하부 금속배선을 상부 금속배선과 중첩되지 않도록 상부 금속배선의 최외곽 라인에서 일정간격 이격시켜 형성함으로써 주변 패턴간의 쇼트(short)를 방지할 수 있는 효과를 제공한다.First, the lower metal wiring is formed to be spaced apart from the outermost line of the upper metal wiring by a predetermined distance so as not to overlap with the upper metal wiring, thereby providing an effect of preventing short between peripheral patterns.

둘째, 본딩 패드가 형성되는 영역에 슬릿 형태의 다수개의 더미 하부 금속배 선을 형성함으로써 본딩 압력을 분산할 수 있는 효과를 제공한다.Second, by forming a plurality of dummy lower metal wires having a slit shape in a region where the bonding pad is formed, the bonding pressure may be distributed.

셋째, 칩을 보호하기 위한 PIQ층을 상부 금속 배선과 중첩되도록 형성함으로써 상부 금속배선에 본딩 압력에 의한 스트레스(stress)를 완화시킬 수 있는 효과를 제공한다. Third, the PIQ layer for protecting the chip is formed to overlap the upper metal wiring, thereby providing an effect of reducing stress caused by bonding pressure in the upper metal wiring.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (2)

하부 구조물이 형성된 반도체 기판 상부에 하부 금속배선을 형성하는 동시에, 본딩 패드가 형성되는 영역에 슬릿 형태를 갖는 다수개의 더미 하부 금속배선을 형성하는 단계;Forming a lower metal interconnection on the semiconductor substrate on which the lower structure is formed, and simultaneously forming a plurality of dummy lower metal interconnections having a slit shape in a region where the bonding pad is formed; 상기 하부 금속배선 및 상기 더미 하부 금속배선 전면에 제 1 보호막을 형성하는 단계;Forming a first passivation layer on an entire surface of the lower metal wiring and the dummy lower metal wiring; 상기 제 1 보호막 상에 상부 금속배선을 형성하는 단계;Forming an upper metal wiring on the first passivation layer; 상기 상부 금속배선 전면에 제 2 층간절연막 및 제 2 보호막을 순차적으로 형성하는 단계;Sequentially forming a second interlayer insulating film and a second passivation film on the entire upper metal wiring; 상기 본딩 패드가 형성되는 영역의 상기 제 2 보호막 및 상기 제 2 층간절연막을 식각하여 상기 상부 금속 배선을 오픈시키는 단계; 및Etching the second passivation layer and the second interlayer insulating layer in a region where the bonding pad is formed to open the upper metal wiring; And 상기 상부 금속배선과 소정간격 중첩되도록 상기 제 2 보호막 상부에 PIQ층을 형성하는 단계Forming a PIQ layer on the second passivation layer so as to overlap a predetermined interval with the upper metal wiring; 를 포함하는 것을 특징으로 하는 반도체 소자의 본딩 패드 형성방법.Bonding pad forming method of a semiconductor device comprising a. 제 1 항에 있어서, 상기 하부 금속배선은 상부 금속배선의 일측단과 중첩되지 않도록 상기 상부 금속배선의 최외곽 라인에서 일정간격 이격시켜 형성함을 특징으로 하는 반도체 소자의 본딩 패드 형성방법.The method of claim 1, wherein the lower metal wires are formed to be spaced apart from the outermost line of the upper metal wires so as not to overlap one end of the upper metal wires.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009042447A1 (en) * 2007-09-24 2009-04-02 Fairchild Semiconductor Corporation A bonding pad structure allowing wire bonding over an active area in a semiconductor die and method of manufacturing same
KR20140134130A (en) * 2013-05-13 2014-11-21 에스케이하이닉스 주식회사 Semiconductor deivce

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR200251534Y1 (en) * 1999-02-11 2001-11-16 이명호 Mold for manufacturing the IC chip
KR200423311Y1 (en) * 2006-05-19 2006-08-04 허철 Teaching material for energy conversion

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Publication number Priority date Publication date Assignee Title
KR200251534Y1 (en) * 1999-02-11 2001-11-16 이명호 Mold for manufacturing the IC chip
KR200423311Y1 (en) * 2006-05-19 2006-08-04 허철 Teaching material for energy conversion

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009042447A1 (en) * 2007-09-24 2009-04-02 Fairchild Semiconductor Corporation A bonding pad structure allowing wire bonding over an active area in a semiconductor die and method of manufacturing same
KR20140134130A (en) * 2013-05-13 2014-11-21 에스케이하이닉스 주식회사 Semiconductor deivce
KR102082466B1 (en) * 2013-05-13 2020-02-27 에스케이하이닉스 주식회사 Semiconductor deivce

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