JP2006318989A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an interlayer insulating film from coming off by reducing stress by a surface protection film. <P>SOLUTION: A semiconductor device comprises an element formed in a chip region on a substrate, a plurality of interlayer insulating films formed on the substrate, wiring formed at least in one of the plurality of interlayer insulating films, a plug that is formed at least in one of the plurality of interlayer insulating films and connects the element to the wire or connects the wiring mutually, and a surface protection film formed on the plurality of interlayer insulating films. The surface protection film is composed of a plurality of portions divided mutually. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a multilayer wiring structure.

  In recent years, with the development of the digital society, demands for miniaturization, high functionality, and high speed operation of semiconductor devices have increased, and semiconductor devices have become highly integrated on a large scale. For this reason, the number of wiring layers has been increased, and further the wiring has been miniaturized. In recent years, a low dielectric constant dielectric having a dielectric constant lower than that of a conventional dielectric material such as a silicon oxide film or silicon nitride film as an interlayer insulating film for the purpose of suppressing parasitic capacitance caused by miniaturization of wiring Materials (Low-k materials) have come to be used (see, for example, Patent Document 1).

  In addition, a surface protective film is usually provided on the surface of a semiconductor device for the purpose of protecting it from external stress such as contact with a filler contained in a mold resin, or protecting from the influence of an external atmosphere such as moisture or ions. Is provided.

  A conventional semiconductor device having a multilayer wiring structure using a Low-k film as an interlayer insulating film will be described below with reference to FIG. FIG. 10 is a cross-sectional view of the main part showing the structure of a conventional semiconductor device 100A.

As shown in FIG. 10, a first interlayer insulating film 101 is formed on a substrate 100 made of a semiconductor such as silicon. A first wiring layer 102 made of copper is formed on the first interlayer insulating film 101 by a damascene wiring process. On the first interlayer insulating film 101 and the first wiring layer 102, a first stopper material 103 made of, for example, a SiCN film for preventing the diffusion of copper is formed. On the first stopper material 103, a low-k film made of, for example, a SiOC film is formed as the second interlayer insulating film 104. In the stopper material 103 and the second interlayer insulating film 104, a contact via that penetrates the first stopper material 103 and the second interlayer insulating film 104 and has a lower end connected to the first wiring layer 102. 105 is formed. Further, a second wiring layer 106 connected to the upper end of the via 105 is formed on the second interlayer insulating film 104 by a damascene wiring process. On the second interlayer insulating film 104 and the second wiring layer 106, a second stopper material 107 made of, for example, a SiCN film for preventing the diffusion of copper is formed. On the second stopper material 107, a surface protective film 108 made of, for example, a polyimide layer or a PBO layer is formed. As described above, the conventional semiconductor device 100A shown in FIG. 10 has a two-layer damascene wiring structure.
JP 2004-172169 A

  By the way, in the conventional semiconductor device 100A using the low-k film described above, the second interlayer insulating film 104 is peeled off from the underlying first stopper material 103 at the corner portion of the semiconductor device 100A. Or cracks due to the peeling of the film. Below, the mechanism of the problem occurrence will be described in detail.

  Generally, a low-k film has physical properties such as a low Young's modulus, a low hardness, a high coefficient of thermal expansion, and a low film density, and therefore has low adhesion to other films. For this reason, the second interlayer insulating film 104 made of a low-k film has low adhesion to the underlying first stopper material 103. Therefore, the second interlayer insulating film 104 made of a low-k film is likely to cause film peeling with respect to the first stopper material 103 in terms of the physical characteristics described above.

  Furthermore, the surface protective film 108 formed on the surface of the semiconductor device 100A is a major factor that promotes film peeling of the second interlayer insulating film 104. That is, a stress due to thermal contraction of the surface protective film 108 is generated due to the difference between the thermal expansion coefficient of the surface protective film 108 and the thermal expansion coefficient of the lower layer, and the film in the second interlayer insulating film 104 is generated by this stress. It will cause peeling.

  FIGS. 11A and 11B are a cross-sectional view and a plan view of relevant parts for explaining the occurrence of film peeling in the second interlayer insulating film 104 made of a low-k film. As shown in FIG. 11A, an interface between the second interlayer insulating film 104 made of a low-k film and the first stopper material 103, and as shown in FIG. In the corner portion 110 of the device 100 </ b> A, the second interlayer insulating film 104 is peeled from the first stopper material 103. The reason why such film peeling occurs is as described above, and the reason why film peeling of the second interlayer insulating film 104 occurs in the corner portion 110 of the semiconductor device 100A is as follows. That is, the portion 111 damaged by dicing at the end portion of the semiconductor device 100A becomes the base point of film peeling, and the stress at the time of thermal contraction of the surface protective film 108 is the largest in the corner portion 110 of the semiconductor device 100A. The film peeling of the second interlayer insulating film 104 occurs selectively from the corner portion 110 of the semiconductor device 100A.

  The film peeling of the second interlayer insulating film 104 generated by the mechanism as described above causes disconnection in the wiring structure inside the semiconductor device 100A. As a result, defective wiring occurs and the yield decreases. Even if the film peeling of the second interlayer insulating film 104 is slight immediately after the assembly process, the film of the second interlayer insulating film 104 is caused by the thermal stress applied by the subsequent use of the semiconductor device 100A. Peeling progresses. Therefore, in this case as well, there is a possibility that the semiconductor device 100A will fail in the future, so that a problem occurs in the reliability of the semiconductor device 100A.

  In view of the above, an object of the present invention is to provide a semiconductor device capable of preventing the occurrence of film peeling of an interlayer insulating film by reducing the stress caused by a surface protective film.

  In order to achieve the above object, a first semiconductor device according to one aspect of the present invention includes an element formed in a chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, and a plurality of interlayers. A wiring formed in at least one of the insulating films, a plug formed in at least one of the plurality of interlayer insulating films and connecting the element and the wiring or connecting the wirings; and a plurality of A surface protective film formed on the interlayer insulating film, and the surface protective film in the chip region is constituted by a plurality of portions separated from each other.

  According to the first semiconductor device of one aspect of the present invention, since the surface protective film is constituted by a plurality of parts separated from each other, the shrinkage force of the surface protective film is dispersed in the plurality of parts. For this reason, generation | occurrence | production of the film peeling of the interlayer insulation film resulting from the contraction force of a surface protective film can be prevented, and generation | occurrence | production of a crack can be suppressed. As a result, it is possible to suppress the occurrence of failures in long-term use and improve the reliability of the semiconductor device.

  In the first semiconductor device according to one aspect of the present invention, the surface protective film is preferably divided at least between the corner portion in the chip region and the element formation region in the chip region.

  As described above, the surface protective film is divided between the corner portion of the chip region and the active region where the shrinkage force of the surface protective film is concentrated and the film is likely to be peeled off. Generation | occurrence | production can be prevented effectively.

  A second semiconductor device according to one aspect of the present invention includes at least one of an element formed in a chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, and a plurality of interlayer insulating films. Formed on at least one of the formed wiring and the plurality of interlayer insulating films, and formed on the plurality of interlayer insulating films and the plug for connecting the element and the wiring or connecting the wirings The surface protection film in the chip region is composed of a plurality of portions that are separated from each other by a plurality of slits and that are connected to each other by a connecting portion.

  According to the second semiconductor device of one aspect of the present invention, the surface protective film is composed of a plurality of portions partitioned from each other by the slit, so that the shrinkage force of the surface protective film is dispersed in the plurality of portions. . For this reason, generation | occurrence | production of the film peeling of the interlayer insulation film resulting from the contraction force of a surface protective film can be prevented, and generation | occurrence | production of a crack can be suppressed. As a result, it is possible to suppress the occurrence of failures in long-term use and improve the reliability of the semiconductor device. Further, since the plurality of parts partitioned from each other are connected by the connecting part, it is possible to prevent film peeling of each part that is likely to occur when divided into a plurality of parts.

  In the second semiconductor device according to one aspect of the present invention, the surface protective film is preferably at least partitioned between a corner portion in the chip region and an element formation region in the chip region.

  In this case, the surface protective film is partitioned between the corner portion of the chip region and the active region where the shrinkage force of the surface protective film concentrates and the film is likely to be peeled off. Can be effectively prevented.

  A third semiconductor device according to one aspect of the present invention includes at least one of an element formed in a chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, and a plurality of interlayer insulating films. Formed on at least one of the formed wiring and the plurality of interlayer insulating films, and formed on the plurality of interlayer insulating films and the plug for connecting the element and the wiring or connecting the wirings A surface protective film, and the surface protective film in the chip region is formed in a region excluding at least a corner portion of the chip region.

  According to the third semiconductor device of one aspect of the present invention, the surface protective film is not formed at the corner portion of the chip region where the shrinkage force of the surface protective film is concentrated and the film is likely to be peeled off. Generation | occurrence | production of the film peeling of the interlayer insulation film resulting from the contraction force of a protective film can be prevented effectively, and generation | occurrence | production of a crack can be suppressed. As a result, it is possible to suppress the occurrence of failures in long-term use and improve the reliability of the semiconductor device.

  In the first to third semiconductor devices according to one aspect of the present invention, a protective material is formed in an opening region that is a region on a plurality of interlayer insulating films and in which a surface protective film is not formed. Is preferred.

  As described above, since the opening region in the surface protective film is embedded with the protective material, it is possible to prevent the filler contained in the mold resin deposited later from entering the opening region and damaging the active region in the chip region. Can do.

  In this case, the surface protective film may be formed on the protective material so that the protective material is exposed below the opening region.

  Moreover, the structure formed on the surface protective film may be sufficient as the protective material so that the opening area | region in a surface protective film may be embedded.

  Here, the surface protective film is preferably made of a resin material, and the protective material is preferably made of a conductive material so that deformation due to shrinkage of the surface protective film does not propagate.

  According to the semiconductor device of the present invention, the surface protective film in the chip region is constituted by a plurality of parts separated from each other, so that the shrinkage force of the surface protective film is dispersed in the plurality of parts. For this reason, generation | occurrence | production of the film peeling of the interlayer insulation film resulting from the contraction force of a surface protective film can be prevented, and generation | occurrence | production of a crack can be suppressed. As a result, it is possible to suppress the occurrence of failures in long-term use and improve the reliability of the semiconductor device.

  Hereinafter, an embodiment of the present invention will be described. As a premise thereof, in order to explain definitions of terms used in the present application, description will be made with reference to FIGS. 1 and 2A and 2B.

  Generally, a semiconductor device is manufactured by arranging a large number of IC circuits composed of a plurality of elements and having a predetermined function on a semiconductor wafer such as silicon.

  FIG. 1 shows a plan view of a general semiconductor wafer 11.

  As shown in FIG. 1, a large number of semiconductor chips (chip regions) 12 on a semiconductor wafer 11 are separated from each other by scribe lines 13 provided in a lattice shape. After a large number of semiconductor chips 12 are formed on one semiconductor wafer 11 through a semiconductor manufacturing process, the semiconductor wafer 11 is diced into individual chips along a scribe line 13, thereby forming a semiconductor device.

  FIGS. 2A and 2B are enlarged plan views of main parts of the semiconductor chip 12.

  As shown in FIGS. 2A and 2B, electrode pads 22 are usually arranged in one or two rows (one row in the drawing) in the region excluding the corner portion 21 in the peripheral portion of the semiconductor chip 12. A region surrounded by the electrode pad 22 is an element formation region 23.

  As described above, the corner portion of the semiconductor chip (chip region) used in the present application is, for example, an electrode pad formed in the peripheral portion of the semiconductor chip (chip region) 12 as shown in FIGS. Say the corner area that is not.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described below.

  FIG. 3A is a plan view of the semiconductor device (semiconductor chip 12) according to the first embodiment of the present invention.

  As shown in FIG. 3A, in the semiconductor device according to the first embodiment of the present invention, a resin material is formed on the upper portion of one semiconductor chip 12 having a multilayer wiring structure (see FIG. 3B described later). A surface protective film 40 made of is formed. And the surface protective film 40 is divided | segmented into the some part 40a so that each may exist mutually independently. Note that a stopper material 39 formed under the surface protective film 40 is exposed between the plurality of portions 40 a constituting the surface protective film 40.

  FIG. 3B is a cross-sectional view of the main part showing the configuration of the semiconductor device according to the first embodiment of the present invention, and the main part of the semiconductor chip 12 shown in FIG. The figure is shown.

  As shown in FIG. 3B, a laminated structure of a plurality of interlayer insulating films 31, 32, 34, 35, 37, 38 is formed on a substrate 30 made of a semiconductor wafer 11 such as silicon. A stopper material 33 is formed between the interlayer insulating film 32 and the interlayer insulating film 34, and a stopper material 36 is formed between the interlayer insulating film 35 and the interlayer insulating film 37. A stopper material 39 is formed on the film 38, and a surface protective film 40 is formed on the stopper material 39. The surface protective film 40 is divided into a plurality of portions 40a so that each exists independently of each other, and a stopper material 39 is exposed between the plurality of portions 40a. Here, for example, a low-k film having a low dielectric constant (relative dielectric constant of 3.9 or less) such as a SiOC film is formed as the interlayer insulating films 31, 32, 34, 35, 37, 38, and the stopper material 33, An SiCN film is formed as 36 and 39, and a resin protective film made of a polyimide layer or a PBO layer is formed as the surface protective film 40.

  The interlayer insulating film 31 is formed with a plug 41 connected to an active region (not shown) such as a diffusion layer formed in the element forming region of the substrate 30. The interlayer insulating film 32 has a plug 41 connected thereto. A wiring 42 connected to the wiring 41 is formed, a plug 43 connected to the wiring 42 is formed in the stopper material 33 and the interlayer insulating film 34, and a wiring 44 connected to the plug 43 is formed in the interlayer insulating film 35. In the stopper material 36 and the interlayer insulating film 37, a plug 45 connected to the wiring 44 is formed, and in the interlayer insulating film 38, a wiring 46 connected to the plug 45 is formed. As a material for the plugs 41, 43, 45 and the wirings 42, 44, 46, for example, copper is used. An electrode pad 47 connected to the wiring 46 is formed on the wiring 46 through an opening in the stopper material 39 and the surface protective film 40. For example, aluminum or an aluminum alloy is used as the electrode pad 47.

  As described above, the feature of the semiconductor device according to the first embodiment of the present invention is that the surface protective film 40 is divided into a plurality of portions 40a so that each of them is present independently of each other. The thickness of the surface protective film 40 is preferably about 1 μm to 10 μm. Furthermore, each of the plurality of portions 40 a obtained by dividing the surface protective film 40 has a size of 0.5 mm × 0.5 mm. There are about ˜3 mm × 3 mm, and it is preferably divided into about 4 to 16 pieces on one chip.

  4A and 4B show the direction and magnitude of the contractile force acting on the surface protective film 40 using arrows.

  First, as shown in FIG. 4A, in the conventional configuration, since the surface protective film 40 is not divided on one semiconductor chip 12, the shrinkage force generated in the surface protective film 40 is reduced at the corners of the semiconductor chip 12. Concentrate on the department. On the other hand, as shown in FIG. 4B, in the configuration of the present embodiment, the surface protective film 40 is divided into a plurality of portions 40 a on one semiconductor chip 12. The resulting contraction force is distributed to each portion 40a and becomes relatively small. For this reason, it is possible to prevent the film peeling of the interlayer insulating film (for example, 34, 37, etc.) from occurring at the end of the semiconductor chip 12, particularly at the corner.

  According to the semiconductor device according to the first embodiment of the present invention, since the surface protective film 40 is divided into the plurality of portions 40a that are independent from each other, the shrinkage force of the surface protective film 40 has a plurality of divided parts. Dispersed in the portion 40a. For this reason, the concentration of the shrinkage force of the surface protective film 40 on the corners of the semiconductor chip 12 can be mitigated, so that the interlayer insulating film (for example, 34, 37, etc.) can be prevented from peeling off and cracks can be generated. Can be suppressed. As a result, it is possible to suppress the occurrence of failures in long-term use and improve the reliability of the semiconductor device.

  Therefore, it is more effective for a semiconductor device having a multilayer wiring structure using a Low-k film as an interlayer insulating film. That is, as described above, the Low-k film tends to cause film peeling due to its physical properties, but the Low-k film is used depending on the configuration of the semiconductor device according to the first embodiment of the present invention. This is particularly effective in a semiconductor device having a multilayer wiring structure.

  As a method for dividing the surface protective film 40, for example, an opening can be formed in the surface protective film 40 by using a standard lithography technique, and the surface protective film 40 can be divided into a plurality of portions 40a. Moreover, it is preferable that the width | variety of the opening part between the some parts 40a is about 5 micrometers-50 micrometers.

  Further, the surface protective film 40 is formed so as to open in a connection terminal portion (for example, the electrode pad 47 shown in FIG. 3B) or in the vicinity region including the connection terminal portion. Further, in order to avoid the influence of stress when dicing the semiconductor wafer 11 along the scribe line, it is desirable to form the surface protective film 40 so as to open in the scribe line. This also applies to the embodiments described later.

  In the present embodiment, as an interlayer insulating film between each wiring, a laminated structure such as an interlayer insulating film 31 and an interlayer insulating film 32, an interlayer insulating film 34 and an interlayer insulating film 35, and an interlayer insulating film 37 and an interlayer insulating film 38 are used. However, a single-layer interlayer insulating film may be used. The plugs 41, 43, and 45 and the wirings 42, 44, and 46 have different structures. However, the plug 41 and the wiring 42, the plug 43 and the wiring 44, and the plug 45 and the wiring 46 may be integrated by a dual damascene method. Good. In the present embodiment, the surface protective film 40 is formed directly on the stopper material 39. However, after forming an insulating film containing nitrogen having a high moisture-proof effect on the stopper material 39, such as a SiN film, the insulating film is formed. A surface protective film 40 may be formed thereon.

<Modification>
FIG. 5 is a plan view showing a modification of the semiconductor device according to the first embodiment of the present invention. In each of the following embodiments, the structure of the surface protective film 40 formed on the stopper material 39 is characteristic. Therefore, only the plan view is described, and the cross-sectional view is the same as described above. Omitted.

  As shown in FIG. 5, the surface protective film 40 is divided into a portion 40 b covering the corner portion of the semiconductor chip 12 and a portion 40 c covering the element forming region where the semiconductor element is formed in the semiconductor chip 12. ing. Thus, since the surface protective film 40 is divided into the portion 40b covering the corner portion and the portion 40c covering the element forming region, the shrinkage force of the surface protective film 40 can be dispersed and the corner of the semiconductor chip 12 can be dispersed. It is possible to prevent the stress concentrated on the portion from affecting the element formation region via the surface protective film 40. Thereby, peeling of the interlayer insulating film can be effectively prevented.

(Second Embodiment)
The semiconductor device according to the second embodiment of the present invention will be described below.

  As shown in FIG. 6A, in the semiconductor device according to the second embodiment of the present invention, the surface protective film 40 is formed on the top of one semiconductor chip 12 having a multilayer wiring structure (not shown). ing. The surface protective film 40 is partitioned into a plurality of portions 40a each by a slit 40d, and each of the plurality of portions 40a is integrated via a connecting portion 40e. According to such a configuration, the surface protective film 40 includes a plurality of portions 40a having an integral configuration by the connecting portion 40e. Therefore, the shrinkage force of the surface protective film 40 is dispersed to prevent the interlayer insulating film from peeling off. In addition, it is possible to prevent a part of the plurality of portions 40a from peeling off.

  Further, as shown in FIG. 6B, the surface protective film 40 includes a portion 40b covering the corner portion of the semiconductor chip 12 and a portion covering the element forming region where the semiconductor element is formed in the semiconductor chip 12. 40c is partitioned through a slit 40d that exposes the stopper member 39 at the bottom, and the portion 40b and the portion 40c are integrated by a connecting portion 40e. In this way, it is possible to prevent the influence of stress concentrated on the corner portion of the semiconductor chip 12 from reaching the element formation region via the surface protective film 40, and at the corner portion of the semiconductor chip 12 where stress is concentrated. It is possible to prevent the portion 40b from peeling off.

  FIG. 6C shows an enlarged view of the vicinity of the connecting portion 40e.

  As shown in FIG. 6C, the width A of the slit 40d is preferably about 5 μm to 50 μm, and the length of the slit 40d is preferably sufficiently longer than the width B of the connecting portion 40e. The width B of the connecting portion 40e is preferably about 1/2 to 2 times the width A of the slit 40d. The reason for this is to prevent the filler constituting the mold resin to be formed later from entering the slit 40d.

(Third embodiment)
The semiconductor device according to the third embodiment of the present invention will be described below.

  As shown in FIG. 7A, in the semiconductor device according to the third embodiment of the present invention, the upper portion of one semiconductor chip 12 having a multilayer wiring structure (not shown), above the stopper material 39. In addition, the surface protective film 40c is formed only on the element formation region of the semiconductor chip 12 where the semiconductor element is formed. Here, the range of the corner portion of the semiconductor chip 12 on which the surface protective film 40 is not formed is preferably a region surrounded by a portion having a distance of about 50 μm to 500 μm from the corners on each side.

  In this way, stress due to the surface protective film 40 concentrated on the corner portion of the semiconductor chip 12 is not generated in the first place, and therefore, peeling of the interlayer insulating film at the corner portion of the semiconductor chip 12 can be effectively prevented.

  Further, as shown in FIG. 7B, as a modification of the surface protective film 40c shown in FIG. 7A, the surface protective film 40c has a plurality of portions 40a, 40f so as to exist independently of each other. A divided configuration may be used. In this way, in addition to effectively preventing the interlayer insulating film from peeling off at the corners of the semiconductor chip 12, the stress can be dispersed by dividing it into a plurality of portions 40a and 40f. Film peeling of the film can be further prevented.

  Further, as shown in FIG. 7C, as a modification of the surface protective film 40c shown in FIG. 7B, the surface protective film 40c is divided into a plurality of portions 40a and 40f by slits 40d. In addition, each of the plurality of portions 40a and 40f is integrated with each other through a connecting portion 40e. In this way, in addition to preventing the interlayer insulating film from being peeled off due to the dispersion of stress, it is possible to prevent a part of the plurality of portions 40a and 40f from peeling compared to the case of FIG. 7B. be able to.

(Fourth embodiment)
The semiconductor device according to the fourth embodiment of the present invention will be described below.

  In the semiconductor device according to the fourth embodiment of the present invention, the protective material is formed inside the opening or the slit that is formed to divide the surface protective film or to partition the surface protective film via the connecting portion, exposing the stopper material to the bottom. Is deposited.

  For example, FIGS. 8A to 8C are views corresponding to FIG. 3A, FIG. 6A, and FIG. 7C, respectively, in the opening or the slit 40d. The structure in which the protective material 80 is deposited is shown. Further, it is preferable that the protective material 80 is deposited to a height similar to the height of the surface protective film 40. The protective material 80 may be a conductive material or an insulating material, but a conductive material such as Al is selected so that deformation due to the shrinkage force acting on the surface protective film 40 does not propagate. Good.

  In this way, in addition to obtaining the same effect as described with reference to FIGS. 3A, 6A, and 7C, the opening formed in the surface protective film 40 can be obtained. Alternatively, it is possible to prevent the filler contained in the mold resin deposited later from entering the slit 40d and damaging the element formation region in the chip region. In addition, although the structure which deposited the protective material on the structure of Fig.3 (a), FIG.6 (a), and FIG.7 (c) was demonstrated here, other FIG.5, FIG.6 (b), FIG.7 ( It goes without saying that the same effect can be obtained even when a protective material is deposited in the configurations of a) and (b).

  Here, as a configuration for depositing the protective material 80 inside the opening or the slit 40d, for example, as shown in FIG. 9A, for example, on the protective material 80 made of a patterned conductive material. Alternatively, after the surface protective film 40 is deposited, an opening or slit 40d may be formed in the surface protective film 40. Further, as shown in FIG. 9B, a protective material 80 made of, for example, a conductive material is deposited on the surface protective film 40 having the openings or slits 40d so as to embed the openings or slits 40d. It may be a configuration.

  The present invention is useful for a semiconductor device having a multilayer wiring structure, particularly a semiconductor device including an interlayer insulating film made of a low-k film.

It is a top view which shows the general structure of a semiconductor wafer. (A) And (b) is a principal part top view which shows the corner part of the semiconductor chip used for the definition of the term used by embodiment of this invention. (A) is a top view which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention, (b) is principal part cross section which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. (A) is a top view for demonstrating the shrinkage force which acts on the surface protective film of the conventional semiconductor device, (b) is the surface protective film of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a top view for demonstrating the contraction force which acts. It is a top view which shows the structure of the modification of the semiconductor device which concerns on 1st Embodiment of this invention. (A)-(c) is a top view which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is a top view which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. (A)-(c) is a top view which shows the structure of the semiconductor device which concerns on the 4th Embodiment of this invention. (A) And (b) is a top view which shows the structure of the semiconductor device which concerns on the 4th Embodiment of this invention. It is principal part sectional drawing which shows the structure of the conventional semiconductor device. (A) And (b) is principal part sectional drawing and a top view for demonstrating generation | occurrence | production of film | membrane peeling of the interlayer insulation film in the conventional semiconductor device, respectively.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Semiconductor wafer 12 Semiconductor chip 13 Scribe line 21 Corner part 22 Electrode pad 23 Element formation area 31, 32, 34, 35, 37, 38 Interlayer insulating film 33, 36, 39 Stopper material 40, 40a, 40b, 40c, 40f Surface Protective film 40d Slit 40e Connecting part (surface protective film)
41, 43, 45 Plug 42, 44, 46 Wiring 47 Electrode pad 80 Protective material

Claims (10)

An element formed in a chip region of the substrate;
A plurality of interlayer insulating films formed on the substrate;
Wiring formed in at least one of the plurality of interlayer insulating films;
A plug formed on at least one of the plurality of interlayer insulating films and connecting the element and the wiring or connecting the wirings;
A surface protective film formed on the plurality of interlayer insulating films,
The semiconductor device according to claim 1, wherein the surface protection film in the chip region includes a plurality of portions separated from each other.   The semiconductor device according to claim 1, wherein the surface protective film is divided at least between a corner portion in the chip region and an element formation region in the chip region. An element formed in a chip region of the substrate;
A plurality of interlayer insulating films formed on the substrate;
Wiring formed in at least one of the plurality of interlayer insulating films;
A plug formed on at least one of the plurality of interlayer insulating films and connecting the element and the wiring or connecting the wirings;
A surface protective film formed on the plurality of interlayer insulating films,
The surface protection film in the chip region is defined by a plurality of portions that are separated from each other by a plurality of slits and that are connected to each other by a connecting portion.   The semiconductor device according to claim 3, wherein the surface protective film is at least partitioned between a corner portion in the chip region and an element formation region in the chip region. An element formed in a chip region of the substrate;
A plurality of interlayer insulating films formed on the substrate;
Wiring formed in at least one of the plurality of interlayer insulating films;
A plug formed on at least one of the plurality of interlayer insulating films and connecting the element and the wiring or connecting the wirings;
A surface protective film formed on the plurality of interlayer insulating films,
The semiconductor device according to claim 1, wherein the surface protective film in the chip region is formed in a region excluding at least a corner portion of the chip region.   The protective material is formed in the opening area | region which is the area | region on these interlayer insulating films and the said surface protective film is not formed, The any one of Claims 1-5 characterized by the above-mentioned. The semiconductor device according to item.   The semiconductor device according to claim 6, wherein the surface protective film is formed on the protective material such that the protective material is exposed below the opening region.   The semiconductor device according to claim 6, wherein the protective material is formed on the surface protective film so as to embed the opening region in the surface protective film.   The semiconductor device according to claim 6, wherein the protective material is made of a conductive material. The semiconductor device according to claim 1, wherein the surface protective film is made of a resin material.

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