KR100668863B1 - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and a method for manufacturing the same are provided to prevent warpage and cracks by etching a PIX layer of a cell region with a line shape parallel to a minor axis of a chip while removing the PIX layer of a fuse and a pad regions. A semiconductor device has a rectangle chip having a cell region(C), a fuse region(F) and a pad region(P). PIX layers are formed on each regions. A first trench(T1) is formed by etching the PIX layer of the fuse region. A second trench(T2) is formed by etching the PIX layer of the pad region. A third trench(T3) is formed by etching the PIX layer of the cell region to have a line shape parallel to a minor axis of the chip.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

1 is a plan view of a semiconductor device manufactured according to the prior art.

2 is a cross-sectional view of a semiconductor device for explaining the conventional problem.

3A to 3C are cross-sectional views illustrating processes of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4 is a plan view of a semiconductor device manufactured in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

C: cell area F: fuse area

P: pad area SUB: semiconductor substrate

FL: Fuse line MC1: 1st contact plug

MC2: 2nd Contact Plug M1: 1st Metal Wiring

M2: Second metal wiring ILD1: First interlayer insulating film

ILD2: Second interlayer dielectric SNC: Storage node plug

SN: Storage Node DL: Dielectric Film

PN: plate node PN ': conductive film for plate node

PS1: first protective film PS2: second protective film

PIX: Fixed film T1: First trench

T2: second trench T3: third trench

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which can suppress cracking due to warping in manufacturing a semiconductor device having a rectangular chip.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. Accordingly, the manufacturing technology of semiconductor devices has been developed to improve the degree of integration, reliability, and response speed.

A semiconductor device mainly includes a fabrication (FAB) process of repeatedly forming a circuit pattern set on a silicon substrate to form cells having an integrated circuit, and packaging the substrate on which the cells are formed in chips. packaging and assembly process. In addition, a process for inspecting electrical characteristics of cells formed on the substrate is performed between the fabrication process and the assembly process.

The inspection step is a step of determining whether the cells formed on the substrate have an electrically good state or a bad state. This is to reduce the effort and cost consumed in the assembly process by removing the cells having a bad state through the inspection process before performing the assembly process. In order to detect the cells having the defective state at an early stage and regenerate them through a repair process.

Here, the repair process will be described in more detail as follows.

In order to improve the yield of the device in the event of a defect during the semiconductor device manufacturing process, a redundant circuit is added to replace the defective device or circuit in the device design, and the redundant circuit is connected to the integrated circuit. The fuse line is designed together, and the repair process is a process in which a cell, which has been found to be defective through an inspection process, is connected to an extra circuit embedded in a chip using the fuse line and a laser beam to regenerate.

In general, fabrication of a semiconductor device for the repair process proceeds in the following manner.

First, a semiconductor substrate having a rectangular chip divided into a cell region, a fuse region, and a pad region, and having a predetermined substructure including a fuse line, an interlayer insulating film, and a metal wiring is formed. Then, the metal wiring is formed on the substrate resultant. A passivation layer is formed to cover the gap.

Then, the first protective film formed on the pad region is etched by etching the thicknesses of the passivation layer and the interlayer insulating layer formed on the fuse region so that the fuse lines react with the laser, and the passivation layer formed on the pad region is etched. A second trench is formed to expose the wiring. An etching process for forming the first and second trenches is called a repair etching process, wherein the exposed metal wiring of the pad region is a portion to which wires are bonded in a subsequent package process.

Next, a chip protection fix layer (PIX layer) is formed on the entire surface of the resultant to fill the first and second trenches, and the fixation layer is densified through a thermal process, and then the fixes formed on the first and second trenches. Remove the membrane. Here, the fix film is a film containing carbon and serves to protect the chip from the process environment during the subsequent packaging process.

FIG. 1 is a plan view of a semiconductor chip in which a repair etching and a fix film etching process are performed according to the related art, and reference numeral C denotes a cell region, F denotes a fuse region, and P denotes a pad region. In the etching of the fix layer, as described above, the fix layer formed on the fuse region F and the pad region P except the cell region C is etched. Indicates an etched portion.

Thereafter, although not shown, a known inspection process and a repair process are sequentially performed.

However, in the above-described prior art, as shown in FIG. 1, when the chip shape is rectangular, the semiconductor chip is subsequently subjected to a die attach process or a printed circuit board (PCB) mounting of a package process. In the process, both sides of the chip along the long axis direction are bent around the center part. The warpage causes stress to concentrate on the films inside the chip, such as a protective film or an interlayer insulating film, thereby causing a fine crack. There is a problem.

The micro cracks induced inside the chip may grow into larger cracks during the pre-bake process, which is a water removal step for the inspection process, thereby lowering the reliability of the device, and in severe cases, illustrated in FIG. 2. As described above, the metal wires are electrically shorted to generate device fail. In the drawings, reference numeral SUB denotes a semiconductor substrate, ILD1 denotes a first interlayer insulating layer, PN ′ denotes a plate node conductive layer, ILD2 denotes a second interlayer insulating layer, MC1 denotes a first contact plug, and MC2 denotes a second layer. The contact plug, M1 represents the first metal interconnection, M2 represents the second metal interconnection, PS1 represents the first protective layer, and PS2 represents the second protective layer, respectively.

Accordingly, the present invention has been made to solve the above-described conventional problems, a semiconductor that can improve the reliability degradation of the device due to the crack caused by the warpage phenomenon of the semiconductor device having a rectangular chip shape An object thereof is to provide a device and a method of manufacturing the same.

In the semiconductor device of the present invention for achieving the above object, in the semiconductor device having a chip having a rectangular shape partitioned into a cell region, a fuse region and a pad region, wherein a fix film is formed on each region, the fuse region; A first trench formed by etching a fix film of the semiconductor film; A second trench formed by etching the fix layer of the pad region; And a third trench formed by etching the fix layer of the cell region in a line shape parallel to the short axis direction of the chip. Characterized in that it comprises a.

On the other hand, the semiconductor device manufacturing method of the present invention for achieving the above object, having a rectangular chip divided into a cell region, a fuse region and a pad region, a fuse line, an interlayer insulating film and a metal wiring is formed; Providing a semiconductor substrate having a protective film formed on a resultant to cover the metal wiring; Etching the passivation layer and the interlayer insulating layer formed on the fuse region to form a first trench for repair, and forming a second trench to expose the metal wiring by etching the passivation layer formed on the pad region; Forming a chip protection fix film on the entire surface of the resultant portion to fill the first and second trenches; And removing the fix films formed on the first and second trenches, and etching the fix films formed on the cell region in a line parallel to the short axis direction of the chip.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3C are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, the first interlayer insulating film ILD1 and the second interlayer insulating film (Chip) having a rectangular chip (Chip) divided into a cell region (C), a fuse region (F), and a pad region (P) are formed. A semiconductor substrate SUB having an ILD2, a fuse line FL, a first contact plug MC1, a second contact plug MC2, a first metal wiring M1, and a second metal wiring M2 is formed. . Unexplained reference numeral PN ′ denotes a conductive film for a plate node, SNC denotes a storage node plug, SN denotes a storage node which is a lower electrode of a capacitor, DL denotes a dielectric layer, and PN denotes a plate node that is an upper electrode of a capacitor. .

Then, the first passivation layer PS1 and the second passivation layer PS2 are sequentially formed on the entire surface of the resultant portion so as to cover the second metal wiring M2. Here, the first passivation layer PS1 is formed to fill the space between the second metal wirings M2, and serves as a buffer layer to buffer the stress caused by the second passivation layer PS2 of the subsequent nitride film material. Do it.

Referring to FIG. 3B, a mask pattern (not shown) of a photoresist material for repair etching is formed on the second passivation layer PS2, and the mask pattern is formed on the fuse region F by using the mask pattern as an etching barrier. 2 and the first protective films PS2 and PS1 and the second interlayer insulating film ILD2 and the first interlayer insulating film ILD1 having a partial thickness are sequentially etched to form the first trenches T1 for repair and pad regions ( The second and first passivation layers PS2 and PS1 formed on P are etched to form second trenches T2 exposing metal wires for wire bonding. Then, the mask pattern is removed.

Referring to FIG. 3C, a fix film PIX containing an organic material such as carbon for the purpose of protecting the chip from the packaging process environment on the entire surface of the resultant portion to fill the first and second trenches T1 and T2. The film quality is densified through heat treatment.

Thereafter, the fix layer formed on the first trenches T and the second trench T2 of the fuse region F and the pad region P is removed, and the fix layer formed on the cell region C is shortened. The third trench T3 is formed by etching in the form of a line parallel to the direction.

Thereafter, although not shown, a known inspection process and a repair process are sequentially performed in the same manner as in the prior art.

4 is a plan view of a semiconductor chip in which a repair etching and a fix film etching process are performed according to an exemplary embodiment of the present invention, and the hatched portions represent the fix film etching portions.

Comparing FIG. 4 with FIG. 2 showing a semiconductor device manufactured according to the related art, as described in the above embodiments, in the present invention, the first and second trenches of the fuse region F and the pad region P are provided in the present invention. In addition to etching and removing the fix film formed on the T1 and T2, the third trench T3 is formed by etching the fix film of the cell region C in a line parallel to the short axis direction of the chip.

In this case, the third trenches T3 formed parallel to the short axis direction of the chip on the cell region C serve to moderate the physical force applied to the chip in a subsequent packaging and mounting process, and thus warpage. The cracking phenomenon of the inner film of the chip due to) is suppressed. Therefore, in the manufacture of a semiconductor device having a chip having a rectangular shape, it is possible to suppress cracking of the chip inner films due to warpage, thereby improving reliability and manufacturing yield of the device.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, according to the present invention, in manufacturing a semiconductor device having a chip having a rectangular shape, by removing the fix film of the fuse region and the pad region, by etching the fix film of the cell region in the form of a line parallel to the short axis direction of the chip, In the subsequent packaging and mounting process, the physical force applied to both sides along the longitudinal direction of the chip can be moderately alleviated, so that crack generation of the chip inner films due to warpage can be suppressed.

Accordingly, the present invention can improve the reliability and manufacturing yield of the device by suppressing a failure due to cracking caused by bending, which is a disadvantage of a semiconductor device having a rectangular chip.

Claims (2)

A semiconductor device having a rectangular chip divided into a cell region, a fuse region, and a pad region, wherein a fix film is formed on each region. A first trench formed by etching a fix layer of the fuse region; A second trench formed by etching the fix layer of the pad region; And And a third trench formed by etching the fixed film of the cell region in a line shape parallel to the short axis direction of the chip. Providing a semiconductor substrate having a rectangular chip divided into a cell region, a fuse region, and a pad region, a fuse line, an interlayer insulating film, and a metal wiring are formed, and a protective film is formed on the resultant to cover the metal wiring; Etching the passivation layer and the interlayer insulating layer formed on the fuse region to form a first trench for repair, and forming a second trench to expose the metal wiring by etching the passivation layer formed on the pad region; Forming a chip protection fix film on the entire surface of the resultant portion to fill the first and second trenches; And Removing the fix films formed on the first and second trenches, and etching the fix films formed on the cell region in a line parallel to the short axis direction of the chip.

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