WO2011078319A1 - Semiconductor device, semiconductor wafer, and method for manufacturing a semiconductor device - Google Patents

Semiconductor device, semiconductor wafer, and method for manufacturing a semiconductor device Download PDF

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Publication number
WO2011078319A1
WO2011078319A1 PCT/JP2010/073320 JP2010073320W WO2011078319A1 WO 2011078319 A1 WO2011078319 A1 WO 2011078319A1 JP 2010073320 W JP2010073320 W JP 2010073320W WO 2011078319 A1 WO2011078319 A1 WO 2011078319A1
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Prior art keywords
semiconductor
protective layer
semiconductor device
scribe line
semiconductor substrate
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PCT/JP2010/073320
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French (fr)
Japanese (ja)
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允 村上
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株式会社フジクラ
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Publication of WO2011078319A1 publication Critical patent/WO2011078319A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device, a semiconductor wafer, and a method for manufacturing a semiconductor device, and more particularly, a semiconductor device, a semiconductor wafer, and a semiconductor capable of suppressing peeling of a protective layer that protects a circuit element formed on the semiconductor device.
  • the present invention relates to a device manufacturing method. This application claims priority based on Japanese Patent Application No. 2009-291717 for which it applied on December 24, 2009, and uses the content here.
  • a semiconductor package for example, a so-called dual inline package (DIP) or quad flat package (QFP) in which a silicon chip is sealed with a resin
  • DIP dual inline package
  • QFP quad flat package
  • the side surface of the resin package Peripheral terminal arrangement type in which metal leads are arranged in a part or a peripheral part has been mainly used.
  • a ball grid array (Ball Grid Array, BGA) is known as a semiconductor package structure that has been widely spread in recent years. This has a structure in which electrodes called solder bumps are two-dimensionally arranged on the flat surface of the package, so that it can be mounted with a higher density than DIP or QFP. For this reason, the BGA is used as a package for a CPU or a memory of a computer.
  • a conventional BGA type semiconductor package has a package size larger than the chip size.
  • a package that is miniaturized so that the package is almost the size of the chip is called a chip scale package (Chip Scale Package, CSP), which greatly contributes to the reduction in size and weight of electronic devices. Yes.
  • CSP Chip Scale Package
  • the BGA type semiconductor package is completed by cutting a wafer substrate on which a circuit is formed and mounting the obtained semiconductor chip on a substrate called an interposer.
  • a patterned interposer is required, and a process of mounting each of a plurality of semiconductor chips on the interposer is necessary. For this reason, a dedicated material or a manufacturing apparatus has to be used, which has a drawback of high cost.
  • CSP manufacturing method
  • a wafer level CSP an insulating resin layer, a rewiring layer, a sealing resin layer, a solder bump, etc. are formed on this wafer substrate, and a semiconductor wafer is formed in the final process.
  • a semiconductor device having a package structure can be obtained by cutting to a predetermined chip size (see, for example, Patent Document 1). Therefore, since the package structure is collectively formed on the semiconductor substrate formed in a wafer shape, an interposer is not required as in the prior art. Further, since the wafer is processed with the package structure mounted on the wafer, a conventional wafer processing apparatus can be diverted. For this reason, the manufacturing efficiency is high and the cost disadvantage is reduced.
  • the size of the divided chips is the same as the size of the packaged semiconductor device.
  • the wiring distance of the obtained semiconductor device is shorter than the wiring distance of the conventional package, and the parasitic capacitance of the wiring is also small.
  • a semiconductor device having these excellent features is extremely advantageous in that it can realize high-density mounting or high information processing speed, which is currently progressing rapidly.
  • a region serving as a scribe line is cut using a dicing blade.
  • dicing is controlled, for example, by adjusting the rotational speed or pressure of the dicing blade in order to prevent mechanical defects from occurring inside the circuit element.
  • FIG. 6 shows a conventionally known semiconductor device.
  • a circuit element 11 is formed on a semiconductor substrate 10 formed in a rectangular shape, and is formed in a rectangular shape so as to cover the circuit element 11.
  • a protective layer 120 is formed. The peripheral edge 121 of the protective layer 120 and the four sides 116 of the semiconductor substrate 10 are formed to be substantially parallel.
  • the conventional semiconductor device 100 when the semiconductor wafer is divided into a plurality of semiconductor devices in the final process of the wafer level CSP manufacturing process, when the dicing blade comes into contact with the resin layer 120 that protects the circuit element 11, There was a problem that the peripheral part 121 of the resin layer 120 peeled off.
  • the stress applied to the peripheral portion 121 of the resin layer 120 is not dispersed is the cause of peeling.
  • the semiconductor substrate 10 is deformed by heat or external stress, whereby stress is applied to the protective layer 120 that protects the circuit element 11, and the protective layer 120 is peeled off from the semiconductor substrate 10 at the peripheral portion 121 of the protective layer 120. There was a defect to do. This defect is also presumed to be caused by the stress applied to the protective layer 120 being concentrated in one place.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device and a semiconductor wafer that can suppress peeling of a protective layer that protects circuit elements constituting the semiconductor device.
  • a semiconductor device has a surface on which a circuit element is formed and a side portion, and is formed in a rectangular shape, and covers the surface of the semiconductor substrate and the circuit element. And a protective layer having a peripheral portion including at least a portion along the side portion. In the part of the semiconductor device, the distance between the peripheral portion and the side portion increases or decreases in the direction along the side portion.
  • the portion is formed in an S shape in a direction along a side portion of the semiconductor substrate.
  • the semiconductor wafer according to the second aspect of the present invention has a surface on which a plurality of circuit elements are formed so as to cover the semiconductor substrate formed in a wafer shape, the surface of the semiconductor substrate, and each of the circuit elements. And a protective layer having a peripheral edge portion and a region located between the circuit elements adjacent to each other and cut as a scribe line.
  • the distance between the peripheral portion and the scribe line increases or decreases in the direction along the scribe line.
  • the part is preferably formed in an S shape in a direction along the scribe line.
  • a semiconductor device manufacturing method comprising: a semiconductor substrate having a surface on which a plurality of circuit elements are formed; and a wafer-like semiconductor substrate; and the surface of the semiconductor substrate and the circuit elements.
  • a semiconductor wafer having a protective layer arranged to cover and having a peripheral portion and a region to be cut as a scribe line between the adjacent circuit elements is prepared, and at least the scribe portion of the peripheral portion is prepared. In a region along the line, the distance between the peripheral edge portion and the scribe line is increased or decreased in the direction along the scribe line, the region to be the scribe line is cut, and the plurality of circuit elements are divided, thereby providing a chip.
  • a plurality of semiconductor devices formed in a shape are formed.
  • a semiconductor substrate having a surface on which a circuit element is formed and a side part and formed in a rectangular shape, the surface of the semiconductor substrate, and the circuit element are provided.
  • a semiconductor substrate having a surface on which a plurality of circuit elements are formed and formed in a wafer shape, and covering each of the surface and the circuit elements of the semiconductor substrate.
  • a protective layer having a peripheral portion and a region that is located between the circuit elements adjacent to each other and is cut as a scribe line.
  • a semiconductor substrate having a surface on which a plurality of circuit elements are formed and formed in a wafer shape, each of the surface of the semiconductor substrate and the circuit elements
  • a semiconductor wafer provided with a protective layer arranged to cover the periphery and having a peripheral portion and a region to be cut as a scribe line located between the circuit elements adjacent to each other, and at least the peripheral portion
  • the distance between the peripheral edge portion and the scribe line is increased or decreased in the direction along the scribe line, the region that becomes the scribe line is cut, and the plurality of circuit elements are divided,
  • a plurality of semiconductor devices formed in a chip shape are formed.
  • FIG. 1 is a plan view schematically showing a first embodiment of a semiconductor device according to the present invention.
  • FIG. 2 is a cross-sectional view taken along the line II-II in FIG. It is a top view which shows 2nd Embodiment of the semiconductor device which concerns on this invention.
  • 1 is a plan view showing a semiconductor wafer according to the present invention. It is the schematic which shows the manufacturing method of a semiconductor device. It is the schematic which shows the manufacturing method of a semiconductor device. It is the schematic which shows the manufacturing method of a semiconductor device. It is the schematic which shows the manufacturing method of a semiconductor device. It is a top view which shows the conventional semiconductor device typically.
  • FIG. 1 is a plan view schematically showing an example of a semiconductor device according to the first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along the line II-II in FIG.
  • the semiconductor device 1 of the present invention is a semiconductor device obtained by dividing a semiconductor wafer in which circuit elements are formed in a dicing process.
  • a circuit element 11 is formed on a surface (one surface) of a semiconductor substrate 10 constituting the semiconductor device 1, and the circuit element 11 is covered with a protective layer 20.
  • the region R of the semiconductor wafer to be cut as a scribe line is cut by a dicing blade or the like.
  • the symbol L is the center line of the dicing line.
  • Each of the side portions 16 of the semiconductor substrate 10 formed in a rectangular shape is formed by cutting the region R.
  • the distance d (see FIG. 2) between each side portion 16 of the semiconductor substrate 10 formed in a rectangular shape and the peripheral portion of the protective layer 20 is not constant, and is easy to understand in FIG. As shown, it increases or decreases in the direction along the side 16.
  • the peripheral edge of the protective layer 20 has a corrugated shape as shown in FIG. Therefore, when a force is applied to the peripheral portion 21 of the protective layer 20, the force applied to the peripheral portion 21 is dispersed in a direction different from the direction of the force applied to the peripheral portion 21.
  • the magnitude of the force generated in one direction is smaller than that of a conventional protective layer having a peripheral edge portion formed in a straight line, and as a result, the protective layer 20 is hardly peeled off from the semiconductor substrate 10.
  • the wave shape here is a sine curve that is repeated periodically or aperiodically, and is a shape in which the vertex of the curve is formed in an R shape.
  • a portion near the corner of the semiconductor device 1 is drawn with a larger arc (R) than other portions (portions away from the corner of the semiconductor device 1).
  • R arc
  • it is formed in a rounded shape. That is, it is preferable that the radius of the R shape at a portion near the corner of the semiconductor device 1 is larger than the radius of the R shape at a portion away from the corner of the semiconductor device 1. According to this structure, it is possible to effectively prevent the protective layer 20 from peeling from the corners of the semiconductor device in which stress is easily applied to the protective layer 20.
  • the number of the peak parts in one side part is three or more.
  • the protective layer 20 By forming the protective layer 20 so as to have such a shape, the protective layer 20 has a shape in which the distance d is repeatedly increased or decreased, and as a result, the peeling of the protective layer 20 is more effectively suppressed. can do.
  • the distance d between each side 16 of the semiconductor substrate 10 and the peripheral edge of the protective layer 20 is preferably 50 ⁇ m or more. According to this structure, since the dicing blade does not easily come into contact with the protective layer 20, a problem that the protective layer 20 is peeled off during dicing can be avoided.
  • the protective layer 20 As a method of manufacturing the protective layer 20 having such a shape, a photolithography technique using a photosensitive resin can be applied.
  • the photomask pattern is designed so that the four corners of the protective layer 20 have an R shape as described above, and the four side portions 16 have a corrugated shape. It is possible to manufacture the protective layer 20. The manufacturing method will be described later.
  • the semiconductor substrate 10 is, for example, a semiconductor substrate such as silicon or GaAs, or an electrically insulating substrate such as glass or resin.
  • the material of the protective layer 20 is a resin, and a material having high insulation, excellent heat resistance and chemical resistance, and strong mechanical strength is preferable. Specifically, for example, polyimide resin, epoxy resin, phenol resin, silicone resin, ABS (acrylonitrile, butadiene, styrene copolymer synthesis) resin, PBO (polybenzoxazole) resin, BCB (benzocyclobutene) resin and the like can be mentioned. It is done. Furthermore, you may form the protective layer 20 by laminating
  • the thickness of the protective layer 20 is, for example, 5 to 100 ⁇ m.
  • the circuit element 11 is, for example, a semiconductor functional element such as a memory or an IC, or a rewiring formed on a WLP (wafer level package).
  • the rewiring is a wiring layer formed of a conductor (such as various metals or alloys) such as Cu, Al, Ni, Ag, Pb, Sn, Au, Co, Cr, Ti, or TiW.
  • the formation method of the circuit element 11 which is a wiring layer is not specifically limited, As the formation method, for example, a sputtering method, a vapor deposition method, a plating method, or a method in which two or more of these methods are combined is adopted. Is done.
  • the structure of the circuit element 11 which is a wiring layer may be a structure formed by a single conductor layer or a structure in which multiple conductor layers are laminated.
  • a photolithography technique is suitably used for patterning the wiring layer.
  • FIG. 3 is a plan view schematically showing an example of a semiconductor device according to the second embodiment of the present invention.
  • the differences between the first embodiment and the second embodiment described above will be mainly described, and the same members as those in the first embodiment will be denoted by the same reference numerals, and description thereof will be omitted or simplified. .
  • the semiconductor device 1b according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in the shape of the peripheral portion of the protective layer 20a.
  • the peripheral portion of the protective layer 20a of the second embodiment has an S-shape with an R shape forming a waveform having a constant period.
  • the radius of the R shape in the plurality of peak portions constituting the sine curve is substantially the same, and the radius of the R shape in the plurality of valley portions is also substantially the same. It is preferable that the radius of the R shape in the peak portion and the valley portion is the same. According to such a configuration, the stress applied to the protective layer 20a can be evenly dispersed, and the protective layer 20a can be further prevented from peeling off from the semiconductor device 1b.
  • FIG. 4 is a plan view schematically showing an example of the semiconductor wafer 2 according to the second embodiment of the present invention. By dividing (dividing into pieces) the semiconductor wafer 2 in the dicing process, a plurality of individual semiconductor devices 1 and 1b are obtained.
  • the surface of the semiconductor substrate 15 constituting the semiconductor wafer 2 is partitioned in a lattice shape by a center line L of a region that becomes a scribe line.
  • the circuit element 11 is formed in each of the sections, and further has a configuration in which the circuit element 11 is covered with the protective layer 20.
  • Each protective layer 20 is formed in a plurality of regions excluding the region R (see FIG. 1) to be cut as a scribe line.
  • the shape of the protective layer 20 is the same as the shape of the protective layer 20 constituting the semiconductor devices 1 and 1b of the first embodiment and the second embodiment.
  • 5A to 5D are cross-sectional views sequentially showing the method for manufacturing the protective layer 20 and the dicing process.
  • a resin film 20f is formed using a photosensitive resin on the surface of the semiconductor substrate 15 on which the circuit element 11 is formed.
  • a method for forming the resin film 20f for example, a spin coat coating method, a film laminating method, a spray coating method, or the like can be used.
  • pre-bake heat treatment
  • the solvent component contained in the resin film 20f can be volatilized and removed, and the adhesion between the photoresist and the semiconductor substrate 15 can be increased.
  • pre-baking is not always necessary.
  • the resin film 20f is patterned by using a photolithography technique. Specifically, as shown in FIG. 5B, the resin film 20f is irradiated with exposure light through a photomask 30, and the mask pattern is transferred to the resin film.
  • a light source a light source that emits light including the photosensitive wavelength of the resin is used.
  • the optimum photosensitive wavelength is selected according to the type of the resin material, but it is preferable to use light in a wavelength region including visible to ultraviolet wavelengths generally called g, h and i rays.
  • a mercury lamp is preferably used.
  • PEB Post Exposure Bake
  • the resin film 20f is developed to remove the unnecessary resin film, and the resin film is left only in a region where the protective layer 20 is provided later.
  • the developer used in this step can be determined according to the type of photosensitive resin.
  • the remaining resin film is cured to volatilize excess photosensitive group component or solvent component to form the protective layer 20.
  • the protective layer 20 is formed using a photosensitive resin has been described, but it is also possible to form the protective layer 20 using a non-photosensitive resin.
  • the protective layer 20 is patterned by forming the protective layer 20 on the entire surface of the semiconductor wafer, forming a patterned resist mask on the protective layer 20, and then performing an etching process for etching the protective layer 20. After the etching treatment, the protective layer 20 is obtained by removing the resist mask. (7) After forming the protective layer 20, the semiconductor device is processed as necessary. For example, processing (processing) such as forming external connection terminals (such as solder bumps) or forming a laser mark on the back surface of the semiconductor wafer is performed on the semiconductor device. (8) Finally, as shown in FIG. 5D, dicing is performed along the center line L to divide the semiconductor wafer 20 to obtain the semiconductor device 1.
  • the protective layer 20 of the present invention is formed using a coating technique in the semiconductor field as described above. Therefore, the protective layer 20 can be formed with a uniform thickness over the entire region of the semiconductor wafer, and the thickness can be easily controlled. In addition, since the protective layer 20 is patterned using a photolithography technique, the protective layer 20 can be formed in any region with high positional accuracy. Therefore, the protective layer 20 can protect the circuit element 11 stably and reliably.
  • the semiconductor device, the semiconductor wafer, and the method for manufacturing the semiconductor device of the present invention have been described.
  • the technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. It is possible to make changes.
  • the configuration in which the circuit element and the protective layer are formed on one surface of the semiconductor substrate has been described as an example.
  • the present invention is not limited to this, and both surfaces of the semiconductor substrate are formed. It is also possible to form a circuit element and a protective layer.
  • SYMBOLS 1, 1b ... Semiconductor device, 2 ... Semiconductor wafer, 10 ... Semiconductor substrate, 11 ... Circuit element, 15 ... Semiconductor substrate, 16 ... Side part, 20, 20a ... Protective layer, 21 ... Peripheral part, 30 ... Resist layer, R ... A region to be cut as a scribe line, L ... A center line of a region to be a scribe line.

Abstract

Provided is a semiconductor device that comprises: a rectangular semiconductor substrate (10) that has a surface on which a circuit element (11) is formed and a periphery (16); and a protective layer (20) that is disposed so as to cover the circuit element (11) and the aforementioned surface of the semiconductor substrate (10) and has an outer edge (21) that, at least, includes a region that follows the aforementioned periphery (16). In said region, the distance between the outer edge (21) and the periphery (16) varies along the periphery (16).

Description

半導体装置，半導体ウエハ，及び半導体装置の製造方法Semiconductor device, semiconductor wafer, and manufacturing method of semiconductor device
　本発明は、半導体装置，半導体ウエハ，及び半導体装置の製造方法に関し、特に、半導体装置上に形成された回路素子を保護する保護層の剥離を抑制することができる半導体装置，半導体ウエハ，及び半導体装置の製造方法に関する。
　本願は、２００９年１２月２４日に出願された特願２００９－２９１７７１号に基づき優先権を主張し、その内容をここに援用する。 The present invention relates to a semiconductor device, a semiconductor wafer, and a method for manufacturing a semiconductor device, and more particularly, a semiconductor device, a semiconductor wafer, and a semiconductor capable of suppressing peeling of a protective layer that protects a circuit element formed on the semiconductor device. The present invention relates to a device manufacturing method.
This application claims priority based on Japanese Patent Application No. 2009-291717 for which it applied on December 24, 2009, and uses the content here.
　従来、半導体パッケージ、例えば、シリコンチップが樹脂により封止された、いわゆるデュアル・インライン・パッケージ（Ｄｕａｌ　Ｉｎｌｉｎｅ　Ｐａｃｋａｇｅ、ＤＩＰ）又はクァド・フラット・パッケージ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ、ＱＦＰ）においては、樹脂パッケージの側面部又は周辺部に金属リードが配置された周辺端子配置型が主に用いられていた。 Conventionally, in a semiconductor package, for example, a so-called dual inline package (DIP) or quad flat package (QFP) in which a silicon chip is sealed with a resin, the side surface of the resin package Peripheral terminal arrangement type in which metal leads are arranged in a part or a peripheral part has been mainly used.
　これに対し、近年広く普及している半導体パッケージ構造として、たとえばボールグリットアレイ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ、ＢＧＡ）が知られている。これは、パッケージの平坦な表面に半田バンプと呼ばれる電極が二次元的に配置された構造を有しているため、ＤＩＰ又はＱＦＰと比較して高密度な実装が可能である。このため、ＢＧＡは、コンピュータのＣＰＵ又はメモリなどのパッケージとして使われている。従来のＢＧＡタイプの半導体パッケージは、パッケージサイズがチップサイズよりも大きい。この半導体パッケージの中でも、パッケージがほとんどチップサイズに近い大きさとなるように小型化されたパッケージは、チップスケールパッケージ（Ｃｈｉｐ　Ｓｃａｌｅ　Ｐａｃｋａｇｅ、ＣＳＰ）と呼ばれ、電子機器の小型軽量化に大きく貢献している。 On the other hand, for example, a ball grid array (Ball Grid Array, BGA) is known as a semiconductor package structure that has been widely spread in recent years. This has a structure in which electrodes called solder bumps are two-dimensionally arranged on the flat surface of the package, so that it can be mounted with a higher density than DIP or QFP. For this reason, the BGA is used as a package for a CPU or a memory of a computer. A conventional BGA type semiconductor package has a package size larger than the chip size. Among these semiconductor packages, a package that is miniaturized so that the package is almost the size of the chip is called a chip scale package (Chip Scale Package, CSP), which greatly contributes to the reduction in size and weight of electronic devices. Yes.
　ＢＧＡタイプの半導体パッケージは、回路が形成されたウエハ基板を切断し、得られた半導体チップをインターポーザと呼ばれる基板に搭載することによって完成されている。この半導体パッケージを製造する工程においては、パターニングされたインターポーザが必要である上に、複数の半導体チップの各々をインターポーザに実装する工程が必要である。このため、専用の材料又は製造装置を用いなければならず、コストが高くなるという欠点があった。 The BGA type semiconductor package is completed by cutting a wafer substrate on which a circuit is formed and mounting the obtained semiconductor chip on a substrate called an interposer. In the process of manufacturing this semiconductor package, a patterned interposer is required, and a process of mounting each of a plurality of semiconductor chips on the interposer is necessary. For this reason, a dedicated material or a manufacturing apparatus has to be used, which has a drawback of high cost.
　これに対し、ＣＳＰ、特に「ウエハレベルＣＳＰ」と呼ばれる製法においては、このウエハ基板上に、絶縁樹脂層、再配線層、封止樹脂層、はんだバンプ等を形成し、最終工程において半導体ウエハを所定のチップ寸法に切断することでパッケージ構造を具備した半導体装置を得ることができる（例えば、特許文献１参照）。したがって、ウエハ状に形成された半導体基板上にパッケージ構造を一括形成するため、従来のようにインターポーザを必要としない。また、パッケージ構造がウエハに搭載された状態でウエハが加工されるので、従来のウエハ加工用装置を転用することができる。このため製造効率が高く、コスト面の不利は低減している。しかも、ウエハ全面にパッケージ加工を施した後にダイシングによって、ウエハが複数のチップに分割（個片化）しているので、分割されたチップの大きさが、パッケージされた半導体装置の大きさと同じであり、実装基板に対して最小である投影面積を有する半導体装置を得ることが可能となる。また、得られた半導体装置の配線距離は、従来のパッケージの配線距離よりも短く、配線の寄生容量も小さい。これら優れた特徴を有する半導体装置は、現在急速に進んでいる実装の高密度化又は情報処理速度の高速化が実現できるという点において非常に優位である。 On the other hand, in the manufacturing method called CSP, especially “wafer level CSP”, an insulating resin layer, a rewiring layer, a sealing resin layer, a solder bump, etc. are formed on this wafer substrate, and a semiconductor wafer is formed in the final process. A semiconductor device having a package structure can be obtained by cutting to a predetermined chip size (see, for example, Patent Document 1). Therefore, since the package structure is collectively formed on the semiconductor substrate formed in a wafer shape, an interposer is not required as in the prior art. Further, since the wafer is processed with the package structure mounted on the wafer, a conventional wafer processing apparatus can be diverted. For this reason, the manufacturing efficiency is high and the cost disadvantage is reduced. Moreover, since the wafer is divided into a plurality of chips by dicing after the package processing is performed on the entire surface of the wafer, the size of the divided chips is the same as the size of the packaged semiconductor device. In addition, it is possible to obtain a semiconductor device having a minimum projected area with respect to the mounting substrate. Further, the wiring distance of the obtained semiconductor device is shorter than the wiring distance of the conventional package, and the parasitic capacitance of the wiring is also small. A semiconductor device having these excellent features is extremely advantageous in that it can realize high-density mounting or high information processing speed, which is currently progressing rapidly.
　上記ウエハレベルＣＳＰが採用された半導体装置の製造工程のうち、半導体ウエハを複数のチップに分割するダイシング工程においては、ダイシングブレードを用いて、スクライブラインとなる領域が切削される。ダイシング時は、回路素子内部に機械的欠陥が生じるのを防ぐために、ダイシングブレードの回転速度又は圧力等を調整する等、ダイシングが制御される。 Of the semiconductor device manufacturing processes employing the wafer level CSP, in a dicing process in which a semiconductor wafer is divided into a plurality of chips, a region serving as a scribe line is cut using a dicing blade. During dicing, dicing is controlled, for example, by adjusting the rotational speed or pressure of the dicing blade in order to prevent mechanical defects from occurring inside the circuit element.
　図６に、従来より知られる半導体装置を示す。ダイシングによって分割された（個片化）された一つの半導体装置１００においては、矩形状に形成された半導体基板１０上に回路素子１１が形成され、回路素子１１を覆うように矩形状に形成された保護層１２０が形成されている。保護層１２０の周縁部１２１と、半導体基板１０の４つの辺１１６は、略並行となるように形成されている。 FIG. 6 shows a conventionally known semiconductor device. In one semiconductor device 100 divided (divided into pieces) by dicing, a circuit element 11 is formed on a semiconductor substrate 10 formed in a rectangular shape, and is formed in a rectangular shape so as to cover the circuit element 11. A protective layer 120 is formed. The peripheral edge 121 of the protective layer 120 and the four sides 116 of the semiconductor substrate 10 are formed to be substantially parallel.
特開２００２－２８０４７６号公報JP 2002-280476 A
　しかしながら、従来の半導体装置１００においては、ウエハレベルＣＳＰの製造工程における最終工程で半導体ウエハを複数の半導体装置に分割する際に、ダイシングブレードが回路素子１１を保護する樹脂層１２０に接触した場合、樹脂層１２０の周縁部１２１が剥離するという問題があった。
　ダイシングブレードが樹脂層１２０に接触した際、樹脂層１２０の周縁部１２１に加えられる応力が分散されないことが、剥離の原因であると推測される。
　また、ダイシング後に、熱又は外部応力によって半導体基板１０が変形することによって、回路素子１１を保護する保護層１２０に応力が加わり、保護層１２０の周縁部１２１において保護層１２０が半導体基板１０から剥離する不良があった。この不良も、保護層１２０に加えられる応力が一箇所に集中することが原因であると推測される。 However, in the conventional semiconductor device 100, when the semiconductor wafer is divided into a plurality of semiconductor devices in the final process of the wafer level CSP manufacturing process, when the dicing blade comes into contact with the resin layer 120 that protects the circuit element 11, There was a problem that the peripheral part 121 of the resin layer 120 peeled off.
When the dicing blade comes into contact with the resin layer 120, it is presumed that the stress applied to the peripheral portion 121 of the resin layer 120 is not dispersed is the cause of peeling.
In addition, after the dicing, the semiconductor substrate 10 is deformed by heat or external stress, whereby stress is applied to the protective layer 120 that protects the circuit element 11, and the protective layer 120 is peeled off from the semiconductor substrate 10 at the peripheral portion 121 of the protective layer 120. There was a defect to do. This defect is also presumed to be caused by the stress applied to the protective layer 120 being concentrated in one place.
　本発明は、上記課題を解決するためになされたものであって、半導体装置を構成する回路素子を保護する保護層の剥離を抑制することができる半導体装置、及び半導体ウエハを提供することを目的とする。 The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device and a semiconductor wafer that can suppress peeling of a protective layer that protects circuit elements constituting the semiconductor device. And
　本発明の第１態様の半導体装置は、回路素子が形成された面と、辺部とを有して、矩形状に形成された半導体基板と、前記半導体基板の前記面及び前記回路素子を覆うように配置され、少なくとも前記辺部に沿う部位を含む周縁部を有する保護層とを含む。この半導体装置の前記部位においては、前記周縁部と前記辺部との距離は、前記辺部に沿う方向にて増減している。 A semiconductor device according to a first aspect of the present invention has a surface on which a circuit element is formed and a side portion, and is formed in a rectangular shape, and covers the surface of the semiconductor substrate and the circuit element. And a protective layer having a peripheral portion including at least a portion along the side portion. In the part of the semiconductor device, the distance between the peripheral portion and the side portion increases or decreases in the direction along the side portion.
　本発明の第１態様の半導体装置においては、前記部位は、前記半導体基板の辺部に沿う方向にてＳ字状に形成されていることが好ましい。 In the semiconductor device according to the first aspect of the present invention, it is preferable that the portion is formed in an S shape in a direction along a side portion of the semiconductor substrate.
　本発明の第２態様の半導体ウエハは、複数の回路素子が形成された面を有してウエハ状に形成された半導体基板と、前記半導体基板の前記面及び前記回路素子の各々を覆うように配置され、周縁部を有する保護層と、互いに隣接する前記回路素子の間に位置し、スクライブラインとして切削される領域とを含む。この半導体ウエハにおいて、前記周縁部のうち少なくとも前記スクライブラインに沿う部位においては、前記周縁部と前記スクライブラインとの距離は、前記スクライブラインに沿う方向にて増減している。 The semiconductor wafer according to the second aspect of the present invention has a surface on which a plurality of circuit elements are formed so as to cover the semiconductor substrate formed in a wafer shape, the surface of the semiconductor substrate, and each of the circuit elements. And a protective layer having a peripheral edge portion and a region located between the circuit elements adjacent to each other and cut as a scribe line. In this semiconductor wafer, in at least a portion along the scribe line in the peripheral portion, the distance between the peripheral portion and the scribe line increases or decreases in the direction along the scribe line.
　本発明の第２態様の半導体ウエハにおいては、前記部位は、前記スクライブラインに沿う方向にてＳ字状に形成されていることが好ましい。 In the semiconductor wafer according to the second aspect of the present invention, the part is preferably formed in an S shape in a direction along the scribe line.
　本発明の第３態様の半導体装置の製造方法は、複数の回路素子が形成された面を有してウエハ状に形成された半導体基板と、前記半導体基板の前記面及び前記回路素子の各々を覆うように配置され周縁部を有する保護層と、互いに隣接する前記回路素子の間に位置しスクライブラインとして切削される領域が設けられている半導体ウエハを準備し、前記周縁部のうち少なくとも前記スクライブラインに沿う部位において、前記周縁部と前記スクライブラインとの距離を、前記スクライブラインに沿う方向で増減させ、前記スクライブラインとなる領域を切削し、前記複数の回路素子を分割することにより、チップ状に形成された複数の半導体装置を形成する。 According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a semiconductor substrate having a surface on which a plurality of circuit elements are formed; and a wafer-like semiconductor substrate; and the surface of the semiconductor substrate and the circuit elements. A semiconductor wafer having a protective layer arranged to cover and having a peripheral portion and a region to be cut as a scribe line between the adjacent circuit elements is prepared, and at least the scribe portion of the peripheral portion is prepared. In a region along the line, the distance between the peripheral edge portion and the scribe line is increased or decreased in the direction along the scribe line, the region to be the scribe line is cut, and the plurality of circuit elements are divided, thereby providing a chip. A plurality of semiconductor devices formed in a shape are formed.
　本発明における第１態様の半導体装置においては、回路素子が形成された面と、辺部とを有して、矩形状に形成された半導体基板と、前記半導体基板の前記面及び前記回路素子を覆うように配置され、少なくとも前記辺部に沿う部位を含む周縁部を有する保護層とを含み、前記周縁部と前記辺部との距離は、前記辺部に沿う方向にて増減している。ゆえに、半導体基板又は保護層が変形した場合において、保護層の周縁部に加わる応力が分散され、保護層の剥離を抑制することができるという効果が得られる。 In the semiconductor device according to the first aspect of the present invention, a semiconductor substrate having a surface on which a circuit element is formed and a side part and formed in a rectangular shape, the surface of the semiconductor substrate, and the circuit element are provided. And a protective layer having a peripheral part including at least a part along the side part, and the distance between the peripheral part and the side part increases or decreases in the direction along the side part. Therefore, when the semiconductor substrate or the protective layer is deformed, the stress applied to the peripheral portion of the protective layer is dispersed, and the effect that the peeling of the protective layer can be suppressed is obtained.
　本発明における第２態様の半導体ウエハにおいては、複数の回路素子が形成された面を有してウエハ状に形成された半導体基板と、前記半導体基板の前記面及び前記回路素子の各々を覆うように配置され、周縁部を有する保護層と、互いに隣接する前記回路素子の間に位置し、スクライブラインとして切削される領域とを含む。この半導体ウエハにおいて、前記周縁部のうち少なくとも前記スクライブラインに沿う部位においては、前記周縁部と前記スクライブラインとの距離は、前記スクライブラインに沿う方向にて増減している。ゆえに、半導体基板又は保護層が変形した場合、又はダイシングの際にダイシングブレードが保護層に接触した場合において、保護層の周縁部に加わる応力が分散され、保護層の剥離を抑制することができるという効果が得られる。 In the semiconductor wafer according to the second aspect of the present invention, a semiconductor substrate having a surface on which a plurality of circuit elements are formed and formed in a wafer shape, and covering each of the surface and the circuit elements of the semiconductor substrate. And a protective layer having a peripheral portion and a region that is located between the circuit elements adjacent to each other and is cut as a scribe line. In this semiconductor wafer, in at least a portion along the scribe line in the peripheral portion, the distance between the peripheral portion and the scribe line increases or decreases in the direction along the scribe line. Therefore, when the semiconductor substrate or the protective layer is deformed, or when the dicing blade is in contact with the protective layer during dicing, the stress applied to the peripheral portion of the protective layer is dispersed, and peeling of the protective layer can be suppressed. The effect is obtained.
　本発明における第３態様の半導体装置の製造方法においては、複数の回路素子が形成された面を有してウエハ状に形成された半導体基板と、前記半導体基板の前記面及び前記回路素子の各々を覆うように配置され周縁部を有する保護層と、互いに隣接する前記回路素子の間に位置しスクライブラインとして切削される領域が設けられている半導体ウエハを準備し、前記周縁部のうち少なくとも前記スクライブラインに沿う部位において、前記周縁部と前記スクライブラインとの距離を、前記スクライブラインに沿う方向で増減させ、前記スクライブラインとなる領域を切削し、前記複数の回路素子を分割することにより、チップ状に形成された複数の半導体装置を形成する。ゆえに、半導体基板又は保護層が変形した場合、又はダイシングの際にダイシングブレードが保護層に接触した場合において、保護層の周縁部に加わる応力が分散され、保護層の剥離を抑制することができるという効果が得られる。 In the method for manufacturing a semiconductor device according to the third aspect of the present invention, a semiconductor substrate having a surface on which a plurality of circuit elements are formed and formed in a wafer shape, each of the surface of the semiconductor substrate and the circuit elements A semiconductor wafer provided with a protective layer arranged to cover the periphery and having a peripheral portion and a region to be cut as a scribe line located between the circuit elements adjacent to each other, and at least the peripheral portion In the region along the scribe line, the distance between the peripheral edge portion and the scribe line is increased or decreased in the direction along the scribe line, the region that becomes the scribe line is cut, and the plurality of circuit elements are divided, A plurality of semiconductor devices formed in a chip shape are formed. Therefore, when the semiconductor substrate or the protective layer is deformed, or when the dicing blade is in contact with the protective layer during dicing, the stress applied to the peripheral portion of the protective layer is dispersed, and peeling of the protective layer can be suppressed. The effect is obtained.
本発明に係る半導体装置の第１実施形態を模式的に示す平面図である。1 is a plan view schematically showing a first embodiment of a semiconductor device according to the present invention. 図１のＩＩ－ＩＩ線に沿う断面図である。FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 本発明に係る半導体装置の第２実施形態を示す平面図である。It is a top view which shows 2nd Embodiment of the semiconductor device which concerns on this invention. 本発明に係る半導体ウエハを示す平面図である。1 is a plan view showing a semiconductor wafer according to the present invention. 半導体装置の製造方法を示す概略図である。It is the schematic which shows the manufacturing method of a semiconductor device. 半導体装置の製造方法を示す概略図である。It is the schematic which shows the manufacturing method of a semiconductor device. 半導体装置の製造方法を示す概略図である。It is the schematic which shows the manufacturing method of a semiconductor device. 半導体装置の製造方法を示す概略図である。It is the schematic which shows the manufacturing method of a semiconductor device. 従来の半導体装置を模式的に示す平面図である。It is a top view which shows the conventional semiconductor device typically.
　以下、本発明に係る半導体装置の最良の形態について、図面に基づき説明する。
　以下の説明に用いる各図面では、各部材を認識可能な大きさとするため、各部材の縮尺を適宜変更している。 Hereinafter, the best mode of a semiconductor device according to the present invention will be described with reference to the drawings.
In each drawing used for the following description, the scale of each member is appropriately changed in order to make each member a recognizable size.
（第１実施形態）
　図１は、本発明の第１実施形態に係る半導体装置の一例を模式的に示す平面図であり、図２は、図１のＩＩ－ＩＩ線に沿う断面図である。
　本発明の半導体装置１は、回路素子が作り込まれた半導体ウエハをダイシング工程において分割することによって得られた半導体装置である。半導体装置１を構成する半導体基板１０の面（一面）上には回路素子１１が形成されており、回路素子１１は保護層２０によって被覆されている。 (First embodiment)
FIG. 1 is a plan view schematically showing an example of a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG.
The semiconductor device 1 of the present invention is a semiconductor device obtained by dividing a semiconductor wafer in which circuit elements are formed in a dicing process. A circuit element 11 is formed on a surface (one surface) of a semiconductor substrate 10 constituting the semiconductor device 1, and the circuit element 11 is covered with a protective layer 20.
　半導体ウエハを複数の半導体装置に分割する工程（個片化工程）においては、スクライブラインとして切削される半導体ウエハの領域Ｒがダイシングブレード等によって切削される。図１において、符号Ｌは、ダイシングラインの中心線である。矩形状に形成された半導体基板１０の辺部１６の各々は、前記領域Ｒを切削することによって形成される。 In the process of dividing the semiconductor wafer into a plurality of semiconductor devices (dividing process), the region R of the semiconductor wafer to be cut as a scribe line is cut by a dicing blade or the like. In FIG. 1, the symbol L is the center line of the dicing line. Each of the side portions 16 of the semiconductor substrate 10 formed in a rectangular shape is formed by cutting the region R.
　本発明の半導体装置１においては、矩形状に形成された半導体基板１０の各辺部１６と、保護層２０の周縁部との距離ｄ（図２参照）は一定ではなく、図１に分かり易く示されているように、辺部１６に沿う方向において、増減している。この構造により、保護層２０の周縁部の形状は、図１に示すように波型形状となる。ゆえに、保護層２０の周縁部２１に力が加わると、周縁部２１に付与された力は、周縁部２１に付与された力の方向とは異なる方向に分散される。このような構造においては、直線状に形成された周縁部を有する従来の保護層よりも一方向に生じる力の大きさが小さくなり、結果として、半導体基板１０から保護層２０が剥がれにくくなる。
　ここでいう波型形状とは、周期的または非周期的に繰り返されるサインカーブであり、カーブの頂点がＲ形状に形成された形状である。 In the semiconductor device 1 of the present invention, the distance d (see FIG. 2) between each side portion 16 of the semiconductor substrate 10 formed in a rectangular shape and the peripheral portion of the protective layer 20 is not constant, and is easy to understand in FIG. As shown, it increases or decreases in the direction along the side 16. With this structure, the peripheral edge of the protective layer 20 has a corrugated shape as shown in FIG. Therefore, when a force is applied to the peripheral portion 21 of the protective layer 20, the force applied to the peripheral portion 21 is dispersed in a direction different from the direction of the force applied to the peripheral portion 21. In such a structure, the magnitude of the force generated in one direction is smaller than that of a conventional protective layer having a peripheral edge portion formed in a straight line, and as a result, the protective layer 20 is hardly peeled off from the semiconductor substrate 10.
The wave shape here is a sine curve that is repeated periodically or aperiodically, and is a shape in which the vertex of the curve is formed in an R shape.
　また、保護層２０の周縁部のうち、半導体装置１の角部に近い部位は、他の部位（半導体装置１の角部から離れた部位）と比較して、大きい弧（Ｒ）を描くようなＲ形状で形成されていることが好ましい。即ち、半導体装置１の角部に近い部位におけるＲ形状の半径は、半導体装置１の角部から離れた部位におけるＲ形状の半径よりも大きいことが好ましい。この構造によれば、保護層２０に応力が加わり易い半導体装置の角部から保護層２０が剥離することを効果的に抑制することができる。
　また、４つの辺部に形成された波形においては、一つの辺部における山部の数が３つ以上であることが好ましい。このような形状を有するように保護層２０を形成することによって、保護層２０は、距離ｄが繰り返して増減されている形状を有し、この結果、保護層２０の剥離をより効果的に抑制することができる。
　また、半導体基板１０の各辺部１６と保護層２０の周縁部との距離ｄは、５０μｍ以上であることが好ましい。この構造によれば、ダイシングブレードが保護層２０と接触し難くなるため、ダイシング時に保護層２０が剥がれる不具合を避けることができる。 Further, in the peripheral portion of the protective layer 20, a portion near the corner of the semiconductor device 1 is drawn with a larger arc (R) than other portions (portions away from the corner of the semiconductor device 1). Preferably, it is formed in a rounded shape. That is, it is preferable that the radius of the R shape at a portion near the corner of the semiconductor device 1 is larger than the radius of the R shape at a portion away from the corner of the semiconductor device 1. According to this structure, it is possible to effectively prevent the protective layer 20 from peeling from the corners of the semiconductor device in which stress is easily applied to the protective layer 20.
Moreover, in the waveform formed in four side parts, it is preferable that the number of the peak parts in one side part is three or more. By forming the protective layer 20 so as to have such a shape, the protective layer 20 has a shape in which the distance d is repeatedly increased or decreased, and as a result, the peeling of the protective layer 20 is more effectively suppressed. can do.
The distance d between each side 16 of the semiconductor substrate 10 and the peripheral edge of the protective layer 20 is preferably 50 μm or more. According to this structure, since the dicing blade does not easily come into contact with the protective layer 20, a problem that the protective layer 20 is peeled off during dicing can be avoided.
　このような形状を有する保護層２０を製作する方法としては、感光性樹脂を用いたフォトリソグラフィ技術を適用することができる。保護層２０の四隅の形状が上記のようにＲ形状となるように、かつ、４つの辺部１６が波形形状を有するようにフォトマスクのパターンを設計し、このフォトマスクを用いることで上記の保護層２０を製作することが可能である。製造方法に関しては後述する。 As a method of manufacturing the protective layer 20 having such a shape, a photolithography technique using a photosensitive resin can be applied. The photomask pattern is designed so that the four corners of the protective layer 20 have an R shape as described above, and the four side portions 16 have a corrugated shape. It is possible to manufacture the protective layer 20. The manufacturing method will be described later.
　半導体基板１０は、例えば、シリコン又はＧａＡｓ等の半導体基板、ガラス、樹脂等の電気絶縁性基板である。
　保護層２０の材料は、樹脂であり、絶縁性が高く、耐熱性・耐薬品性に優れ、機械的強度が強い材料が好ましい。具体的には、例えば、ポリイミド樹脂、エポキシ樹脂、フェノール樹脂、シリコーン樹脂、ＡＢＳ（アクリロニトリル、ブタジエン、スチレン共重合合成）樹脂、ＰＢＯ（ポリベンゾオキサゾール）樹脂、ＢＣＢ（ベンゾシクロブテン）樹脂などが挙げられる。更に、それら複数の樹脂を積層することによって保護層２０を形成してもよい。保護層２０の厚さは、例えば、５～１００μｍである。 The semiconductor substrate 10 is, for example, a semiconductor substrate such as silicon or GaAs, or an electrically insulating substrate such as glass or resin.
The material of the protective layer 20 is a resin, and a material having high insulation, excellent heat resistance and chemical resistance, and strong mechanical strength is preferable. Specifically, for example, polyimide resin, epoxy resin, phenol resin, silicone resin, ABS (acrylonitrile, butadiene, styrene copolymer synthesis) resin, PBO (polybenzoxazole) resin, BCB (benzocyclobutene) resin and the like can be mentioned. It is done. Furthermore, you may form the protective layer 20 by laminating | stacking these some resin. The thickness of the protective layer 20 is, for example, 5 to 100 μm.
　回路素子１１は、例えばメモリ又はＩＣなどの半導体機能素子、あるいは、ＷＬＰ（ウエハレベルパッケージ）に形成される再配線などである。前記再配線は、Ｃｕ、Ａｌ、Ｎｉ、Ａｇ、Ｐｂ、Ｓｎ、Ａｕ、Ｃｏ、Ｃｒ、Ｔｉ、ＴｉＷ等の導体（各種の金属又は合金等）から形成された配線層である。配線層である回路素子１１の形成方法は、特に限定されず、その形成方法としては、例えば、スパッタリング法、蒸着法、めっき法等、或いはこれらの２つ以上の方法が組み合わされた方法が採用される。また、配線層である回路素子１１の構造としては、単層の導体層によって形成された構造又は多層の導体層が積層された構造であってもよい。また、配線層のパターニングには、フォトリソグラフィ技術が好適に用いられる。 The circuit element 11 is, for example, a semiconductor functional element such as a memory or an IC, or a rewiring formed on a WLP (wafer level package). The rewiring is a wiring layer formed of a conductor (such as various metals or alloys) such as Cu, Al, Ni, Ag, Pb, Sn, Au, Co, Cr, Ti, or TiW. The formation method of the circuit element 11 which is a wiring layer is not specifically limited, As the formation method, for example, a sputtering method, a vapor deposition method, a plating method, or a method in which two or more of these methods are combined is adopted. Is done. Further, the structure of the circuit element 11 which is a wiring layer may be a structure formed by a single conductor layer or a structure in which multiple conductor layers are laminated. Moreover, a photolithography technique is suitably used for patterning the wiring layer.
（第２実施形態）
　図３は、本発明の第２実施形態に係る半導体装置の一例を模式的に示す平面図である。
　以下の説明においては、上述した第１実施形態と第２実施形態との相違点を中心に述べ、第１実施形態と同一部材には同一符号を付して、その説明は省略または簡略化する。 (Second Embodiment)
FIG. 3 is a plan view schematically showing an example of a semiconductor device according to the second embodiment of the present invention.
In the following description, the differences between the first embodiment and the second embodiment described above will be mainly described, and the same members as those in the first embodiment will be denoted by the same reference numerals, and description thereof will be omitted or simplified. .
　第２実施形態の半導体装置１ｂは、第１実施形態の半導体装置１と比較して、保護層２０ａの周縁部の形状が異なる。第２実施形態の保護層２０ａの周縁部は、波形を構成するＲ形状が一定の周期を有するＳ字型形状である。
　サインカーブを構成する複数の山部におけるＲ形状の半径は略同じであり、また、複数の谷部におけるＲ形状の半径も略同じである。山部及び谷部におけるＲ形状の半径も同じであることが好ましい。
　このような構成によれば、保護層２０ａに加えられる応力を均一に分散し、半導体装置１ｂから保護層２０ａが剥離することをさらに抑制することができる。 The semiconductor device 1b according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in the shape of the peripheral portion of the protective layer 20a. The peripheral portion of the protective layer 20a of the second embodiment has an S-shape with an R shape forming a waveform having a constant period.
The radius of the R shape in the plurality of peak portions constituting the sine curve is substantially the same, and the radius of the R shape in the plurality of valley portions is also substantially the same. It is preferable that the radius of the R shape in the peak portion and the valley portion is the same.
According to such a configuration, the stress applied to the protective layer 20a can be evenly dispersed, and the protective layer 20a can be further prevented from peeling off from the semiconductor device 1b.
（半導体ウエハ）
　図４は、本発明の第２実施形態に係る半導体ウエハ２の一例を模式的に示す平面図である。ダイシング工程において半導体ウエハ２を分割（個片化）することにより、複数の個別の半導体装置１、１ｂが得られる。 (Semiconductor wafer)
FIG. 4 is a plan view schematically showing an example of the semiconductor wafer 2 according to the second embodiment of the present invention. By dividing (dividing into pieces) the semiconductor wafer 2 in the dicing process, a plurality of individual semiconductor devices 1 and 1b are obtained.
　半導体ウエハ２を構成する半導体基板１５の面は、スクライブラインとなる領域の中心線Ｌによって格子状に区画されている。回路素子１１は、区画の各々に形成されており、さらに、回路素子１１が保護層２０によって覆われた構成を有する。 The surface of the semiconductor substrate 15 constituting the semiconductor wafer 2 is partitioned in a lattice shape by a center line L of a region that becomes a scribe line. The circuit element 11 is formed in each of the sections, and further has a configuration in which the circuit element 11 is covered with the protective layer 20.
　個々の保護層２０は、スクライブラインとして切削される領域Ｒ（図１参照）を除いた複数の領域に形成されている。保護層２０の形状は、上記第１実施形態及び第２実施形態の半導体装置１、１ｂを構成する保護層２０の形状と同じである。 Each protective layer 20 is formed in a plurality of regions excluding the region R (see FIG. 1) to be cut as a scribe line. The shape of the protective layer 20 is the same as the shape of the protective layer 20 constituting the semiconductor devices 1 and 1b of the first embodiment and the second embodiment.
　次に、図４に示した半導体ウエハ２の複数の領域に形成された保護層２０の製造方法及びダイシング工程について説明する。
　図５Ａ～図５Ｄは、保護層２０の製造方法、及びダイシング工程について、順に示した断面図である。 Next, a manufacturing method and a dicing process of the protective layer 20 formed in a plurality of regions of the semiconductor wafer 2 shown in FIG. 4 will be described.
5A to 5D are cross-sectional views sequentially showing the method for manufacturing the protective layer 20 and the dicing process.
（１）まず、図５Ａに示すように、回路素子１１が形成された半導体基板１５の面に、感光性樹脂を用いて樹脂膜２０ｆを形成する。樹脂膜２０ｆの形成方法としては、例えば、スピンコート塗布法、フィルムラミネート法、スプレー塗布法等を用いることができる。
（２）次に、形成された感光性の樹脂膜２０ｆには、プリベーク（加熱処理）を施すのが好ましい。これにより、樹脂膜２０ｆに含まれる溶媒成分を揮発及び除去することができ、フォトレジストと半導体基板１５との間の密着力を増加させることが可能である。なお、樹脂の種類によっては、プリベークは必ずしも必要ではない。
（３）続いて、フォトリソグラフィ技術を用いて、樹脂膜２０ｆをパターニングする。具体的には、図５Ｂに示すように、樹脂膜２０ｆにフォトマスク３０を通して露光光を照射し、マスクパターンを樹脂膜に転写する。光源としては、樹脂の感光波長を含む光を発する光源が用いられる。最適な感光波長は、樹脂材料の種類に応じて選択されるが、一般的にはｇ、ｈ、ｉ線と呼ばれる可視線波長～紫外線波長を含む波長領域の光を用いることが好ましい。光源としては、水銀ランプを用いることが好適である。
（４）露光後のフォトレジストに対しては、必要に応じてＰＥＢ（Ｐｏｓｔ　Ｅｘｐｏｓｕｒｅ　Ｂａｋｅ）を実施する。これは、感光性樹脂の光反応を熱的に補うための工程であり、樹脂の種類によっては不要の場合もある。
（５）次いで、図５Ｃに示すように、樹脂膜２０ｆを現像して不要な樹脂膜を除去し、後に保護層２０が設けられる領域にのみ樹脂膜を残す。この工程において用いる現像液は、感光性樹脂の種類に応じて定めることができる。
（６）その後、残した樹脂膜をキュアして余分な感光基成分或いは溶剤成分などを揮発させ、保護層２０を形成する。
　上記の（１）～（６）においては、感光性樹脂を用いて保護層２０を形成する場合について説明したが、非感光性樹脂を用いて保護層２０を形成することも可能である。その場合、保護層２０のパターニングは、保護層２０を半導体ウエハ全面に形成した後、パターニングされたレジストマスクを保護層２０上に形成し、次いで保護層２０をエッチングするエッチング処理を行う。エッチング処理後、レジストマスクを除去することにより、保護層２０が得られる。
（７）保護層２０を形成した後に、必要に応じて半導体装置の加工を行う。例えば、外部接続用端子（はんだバンプ等）を形成したり、半導体ウエハの裏面にレーザーマークを形成したり、といった処理（加工）を半導体装置に行う。
（８）最後に、図５Ｄに示すように、中心線Ｌに沿ってダイシングを行い、半導体ウエハ２０を分割し、半導体装置１を得る。 (1) First, as shown in FIG. 5A, a resin film 20f is formed using a photosensitive resin on the surface of the semiconductor substrate 15 on which the circuit element 11 is formed. As a method for forming the resin film 20f, for example, a spin coat coating method, a film laminating method, a spray coating method, or the like can be used.
(2) Next, it is preferable to pre-bake (heat treatment) the formed photosensitive resin film 20f. Thereby, the solvent component contained in the resin film 20f can be volatilized and removed, and the adhesion between the photoresist and the semiconductor substrate 15 can be increased. Depending on the type of resin, pre-baking is not always necessary.
(3) Subsequently, the resin film 20f is patterned by using a photolithography technique. Specifically, as shown in FIG. 5B, the resin film 20f is irradiated with exposure light through a photomask 30, and the mask pattern is transferred to the resin film. As the light source, a light source that emits light including the photosensitive wavelength of the resin is used. The optimum photosensitive wavelength is selected according to the type of the resin material, but it is preferable to use light in a wavelength region including visible to ultraviolet wavelengths generally called g, h and i rays. As the light source, a mercury lamp is preferably used.
(4) For exposed photoresist, PEB (Post Exposure Bake) is performed as necessary. This is a process for thermally supplementing the photoreaction of the photosensitive resin, and may be unnecessary depending on the type of resin.
(5) Next, as shown in FIG. 5C, the resin film 20f is developed to remove the unnecessary resin film, and the resin film is left only in a region where the protective layer 20 is provided later. The developer used in this step can be determined according to the type of photosensitive resin.
(6) Thereafter, the remaining resin film is cured to volatilize excess photosensitive group component or solvent component to form the protective layer 20.
In the above (1) to (6), the case where the protective layer 20 is formed using a photosensitive resin has been described, but it is also possible to form the protective layer 20 using a non-photosensitive resin. In this case, the protective layer 20 is patterned by forming the protective layer 20 on the entire surface of the semiconductor wafer, forming a patterned resist mask on the protective layer 20, and then performing an etching process for etching the protective layer 20. After the etching treatment, the protective layer 20 is obtained by removing the resist mask.
(7) After forming the protective layer 20, the semiconductor device is processed as necessary. For example, processing (processing) such as forming external connection terminals (such as solder bumps) or forming a laser mark on the back surface of the semiconductor wafer is performed on the semiconductor device.
(8) Finally, as shown in FIG. 5D, dicing is performed along the center line L to divide the semiconductor wafer 20 to obtain the semiconductor device 1.
　本発明の保護層２０は、上述したように半導体分野のコーティング技術を用いて形成される。そのため、半導体ウエハの全領域において保護層２０を均一な厚さに形成することが可能であり、厚さの制御も容易である。また、フォトリソグラフィ技術を用いて保護層２０をパターニングするため、任意の領域に位置精度良く保護層２０を形成することが可能である。ゆえに、保護層２０は、回路素子１１を安定して確実に保護することができる。 The protective layer 20 of the present invention is formed using a coating technique in the semiconductor field as described above. Therefore, the protective layer 20 can be formed with a uniform thickness over the entire region of the semiconductor wafer, and the thickness can be easily controlled. In addition, since the protective layer 20 is patterned using a photolithography technique, the protective layer 20 can be formed in any region with high positional accuracy. Therefore, the protective layer 20 can protect the circuit element 11 stably and reliably.
　以上、本発明の半導体装置及び半導体ウエハ、並びに半導体装置の製造方法について説明してきたが、本発明の技術範囲は、上記実施形態に限定されることなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。
　例えば、前述した実施形態においては、半導体基板の一方の面に回路素子及び保護層を形成する構成を例に挙げて説明したが、本発明はこれに限定されるものではなく、半導体基板の両面に回路素子及び保護層を形成することも可能である。 As described above, the semiconductor device, the semiconductor wafer, and the method for manufacturing the semiconductor device of the present invention have been described. However, the technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. It is possible to make changes.
For example, in the above-described embodiment, the configuration in which the circuit element and the protective layer are formed on one surface of the semiconductor substrate has been described as an example. However, the present invention is not limited to this, and both surfaces of the semiconductor substrate are formed. It is also possible to form a circuit element and a protective layer.
１、１ｂ…半導体装置、２…半導体ウエハ、１０…半導体基板、１１…回路素子、１５…半導体基板、１６…辺部、２０、２０ａ…保護層、２１…周縁部、３０…レジスト層、Ｒ…スクライブラインとして切削される領域、Ｌ…スクライブラインとなる領域の中心線。 DESCRIPTION OF SYMBOLS 1, 1b ... Semiconductor device, 2 ... Semiconductor wafer, 10 ... Semiconductor substrate, 11 ... Circuit element, 15 ... Semiconductor substrate, 16 ... Side part, 20, 20a ... Protective layer, 21 ... Peripheral part, 30 ... Resist layer, R ... A region to be cut as a scribe line, L ... A center line of a region to be a scribe line.

Claims (5)

  1. 　半導体装置であって、
    　回路素子が形成された面と、辺部とを有して、矩形状に形成された半導体基板と、
    　前記半導体基板の前記面及び前記回路素子を覆うように配置され、少なくとも前記辺部に沿う部位を含む周縁部を有する保護層と、
    　前記部位においては、前記周縁部と前記辺部との距離は、前記辺部に沿う方向にて増減していることを特徴とする半導体装置。     A semiconductor device,
    A semiconductor substrate having a surface formed with a circuit element and a side portion and formed in a rectangular shape;
    A protective layer that is disposed so as to cover the surface of the semiconductor substrate and the circuit element, and has a peripheral portion including at least a portion along the side;
    In the portion, the distance between the peripheral portion and the side portion increases or decreases in a direction along the side portion.
  2. 　請求項１に記載の半導体装置であって、
    　前記部位は、前記半導体基板の辺部に沿う方向にてＳ字状に形成されていることを特徴とする半導体装置。     The semiconductor device according to claim 1,
    The semiconductor device is characterized in that the portion is formed in an S shape in a direction along a side portion of the semiconductor substrate.
  3. 　半導体ウエハであって、
    　複数の回路素子が形成された面を有してウエハ状に形成された半導体基板と、
    　前記半導体基板の前記面及び前記回路素子の各々を覆うように配置され、周縁部を有する保護層と、
    　互いに隣接する前記回路素子の間に位置し、スクライブラインとして切削される領域と、
    　を含み、
    　前記周縁部のうち少なくとも前記スクライブラインに沿う部位においては、前記周縁部と前記スクライブラインとの距離は、前記スクライブラインに沿う方向にて増減していることを特徴とする半導体ウエハ。     A semiconductor wafer,
    A semiconductor substrate formed in a wafer shape having a surface on which a plurality of circuit elements are formed;
    A protective layer disposed to cover each of the surface of the semiconductor substrate and the circuit element, and having a peripheral edge;
    A region located between the circuit elements adjacent to each other and cut as a scribe line;
    Including
    A semiconductor wafer, wherein a distance between the peripheral portion and the scribe line is increased or decreased in a direction along the scribe line at least in a portion along the scribe line in the peripheral portion.
  4. 　請求項３に記載の半導体ウエハであって、
    　前記部位は、前記スクライブラインに沿う方向にてＳ字状に形成されていることを特徴とする半導体ウエハ。     The semiconductor wafer according to claim 3,
    The semiconductor wafer is characterized in that the portion is formed in an S shape in a direction along the scribe line.
  5. 　半導体装置の製造方法であって、
    　複数の回路素子が形成された面を有してウエハ状に形成された半導体基板と、前記半導体基板の前記面及び前記回路素子の各々を覆うように配置され周縁部を有する保護層と、互いに隣接する前記回路素子の間に位置しスクライブラインとして切削される領域が設けられている半導体ウエハを準備し、
    　前記周縁部のうち少なくとも前記スクライブラインに沿う部位において、前記周縁部と前記スクライブラインとの距離を、前記スクライブラインに沿う方向で増減させ、
    　前記スクライブラインとなる領域を切削し、前記複数の回路素子を分割することにより、チップ状に形成された複数の半導体装置を形成する
    　ことを特徴とする半導体装置の製造方法。
     
          A method for manufacturing a semiconductor device, comprising:
    A semiconductor substrate formed in a wafer shape having a surface on which a plurality of circuit elements are formed; a protective layer having a peripheral edge portion disposed to cover each of the surface of the semiconductor substrate and the circuit elements; and Preparing a semiconductor wafer provided with a region to be cut as a scribe line located between the adjacent circuit elements;
    In at least a portion along the scribe line in the peripheral portion, the distance between the peripheral portion and the scribe line is increased or decreased in a direction along the scribe line,
    A method of manufacturing a semiconductor device, wherein a plurality of semiconductor devices formed in a chip shape are formed by cutting a region to be the scribe line and dividing the plurality of circuit elements.

PCT/JP2010/073320 2009-12-24 2010-12-24 Semiconductor device, semiconductor wafer, and method for manufacturing a semiconductor device WO2011078319A1 (en)

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